TroubleElectrical/FPGA_Uni
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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

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TroubleElectrical committed 2026-10-13 15:12:00 +11:00
1 parent 19b07b649d
commit 353923eadf
64 files changed
+386 -395
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Quartus/A2/db/assignment2.tmw_info
+2 -2
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@@ -1,7 +1,7 @@
start_full_compilation:s:00:00:55
start_full_compilation:s:00:00:52
start_analysis_synthesis:s:00:00:12-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:28-start_full_compilation
start_fitter:s:00:00:25-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation