Updated instruction counter to have an enable/disable port

modules/assignment2.sv

@@ -56,7 +56,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
 	
-	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, 1'b1, pc_we, pc_addr_write, pc_addr);
 	
 	`ifdef QUARTUS_SYNTH
 		rom #("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);

modules/assignment3.sv

@@ -22,7 +22,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	// TODO: Verify if we need a clk gating on pc_addr
-	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, 1'b1, pc_we, pc_addr_write, pc_addr);
 	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, pc_addr_1);
 	gatereg #(width, 1) gate_pc_addr_1(clk, rst, 1'b1, pc_addr_1, pc_addr_2);
 

modules/instruction_counter.sv

@@ -2,7 +2,7 @@
 `define INSTRUCTION_COUNTER_H
 
 module instruction_counter #(parameter width=5)(
-    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en, input logic [0:0] we,
     input logic [2**width-1:0] W,
     output logic [2**width-1:0] addr
 );
@@ -10,7 +10,9 @@ module instruction_counter #(parameter width=5)(
     logic [2**width-1:0] pc;
     
     always_ff @(posedge clk or posedge rst) begin
-        if (rst) begin
+        if (~en) begin
+            // Skip any cycles where we are disabled
+        end else if (rst) begin
             pc <= {(2**width){1'b0}};
         end else if (we) begin
             pc <= W;