From 2f3ecb9a3c3f283c55c346bf1121e8005311ea84 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Wed, 11 Nov 2026 15:24:41 +1100 Subject: [PATCH] Updated instruction counter to have an enable/disable port --- modules/assignment2.sv | 2 +- modules/assignment3.sv | 2 +- modules/instruction_counter.sv | 6 ++++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/modules/assignment2.sv b/modules/assignment2.sv index 39e2d94..4bb2e2e 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -56,7 +56,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( logic [2**width-1:0] rd_alu; logic [2**width-1:0] rt_alu; - instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); + instruction_counter #(width) PC (clk, rst, 1'b1, pc_we, pc_addr_write, pc_addr); `ifdef QUARTUS_SYNTH rom #("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction); diff --git a/modules/assignment3.sv b/modules/assignment3.sv index 92c54cb..1a8d2e8 100644 --- a/modules/assignment3.sv +++ b/modules/assignment3.sv @@ -22,7 +22,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)( logic [2**width-1:0] pc_addr_write; logic [0:0] pc_we; // TODO: Verify if we need a clk gating on pc_addr - instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); + instruction_counter #(width) PC (clk, rst, 1'b1, pc_we, pc_addr_write, pc_addr); gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, pc_addr_1); gatereg #(width, 1) gate_pc_addr_1(clk, rst, 1'b1, pc_addr_1, pc_addr_2); diff --git a/modules/instruction_counter.sv b/modules/instruction_counter.sv index 773d81b..2927688 100644 --- a/modules/instruction_counter.sv +++ b/modules/instruction_counter.sv @@ -2,7 +2,7 @@ `define INSTRUCTION_COUNTER_H module instruction_counter #(parameter width=5)( - input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we, + input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en, input logic [0:0] we, input logic [2**width-1:0] W, output logic [2**width-1:0] addr ); @@ -10,7 +10,9 @@ module instruction_counter #(parameter width=5)( logic [2**width-1:0] pc; always_ff @(posedge clk or posedge rst) begin - if (rst) begin + if (~en) begin + // Skip any cycles where we are disabled + end else if (rst) begin pc <= {(2**width){1'b0}}; end else if (we) begin pc <= W;