Updated instruction counter to have an enable/disable port

modules/assignment3.sv

@@ -22,7 +22,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	// TODO: Verify if we need a clk gating on pc_addr
-	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	instruction_counter #(width) PC (clk, rst, 1'b1, pc_we, pc_addr_write, pc_addr);
 	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, pc_addr_1);
 	gatereg #(width, 1) gate_pc_addr_1(clk, rst, 1'b1, pc_addr_1, pc_addr_2);