TroubleElectrical/FPGA_Uni
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Added 4 digit 7seg display module (confirmed working for now),

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Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
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TroubleElectrical committed 2026-10-13 16:32:15 +11:00
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commit 25a953cdc6
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Quartus/A2/output_files/assignment2.map.summary
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Analysis & Synthesis Status : Successful - Tue Oct 13 15:08:28 2026
Analysis & Synthesis Status : Successful - Tue Oct 13 16:18:22 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 1
Total pins : 40
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0