Added 4 digit 7seg display module (confirmed working for now),
Added Inputs for displaying registers / Program Counter high and low bits, Assigned pins for Display digits, inputs (Labeled HID) and the clk button
This commit is contained in:
138 files changed
+2431
-744
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@@ -1,5 +1,5 @@
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Analysis & Synthesis report for assignment2
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Tue Oct 13 15:08:28 2026
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Tue Oct 13 16:18:22 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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@@ -23,15 +23,20 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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15. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit
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16. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit
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17. Parameter Settings for User Entity Instance: shifter:SHIFTER
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18. Port Connectivity Checks: "shifter:SHIFTER"
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19. Port Connectivity Checks: "alu:ALU"
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20. Port Connectivity Checks: "register_file:REGS"
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21. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER"
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22. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER"
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23. Port Connectivity Checks: "instruction_counter:PC"
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24. Post-Synthesis Netlist Statistics for Top Partition
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25. Elapsed Time Per Partition
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26. Analysis & Synthesis Messages
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18. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3"
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19. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2"
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20. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1"
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21. Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0"
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22. Port Connectivity Checks: "seven_seg_4digit:display"
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23. Port Connectivity Checks: "shifter:SHIFTER"
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24. Port Connectivity Checks: "alu:ALU"
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25. Port Connectivity Checks: "register_file:REGS"
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26. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER"
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27. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER"
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28. Port Connectivity Checks: "instruction_counter:PC"
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29. Post-Synthesis Netlist Statistics for Top Partition
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30. Elapsed Time Per Partition
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31. Analysis & Synthesis Messages
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@@ -58,14 +63,14 @@ on the Quartus Prime software download page.
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+-----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+---------------------------------+-------------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Tue Oct 13 15:08:28 2026 ;
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; Analysis & Synthesis Status ; Successful - Tue Oct 13 16:18:22 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; assignment2 ;
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; Top-level Entity Name ; assignment2 ;
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; Family ; Cyclone V ;
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; Logic utilization (in ALMs) ; N/A ;
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; Total registers ; 0 ;
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; Total pins ; 1 ;
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; Total pins ; 40 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 ;
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; Total DSP Blocks ; 0 ;
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@@ -197,6 +202,8 @@ on the Quartus Prime software download page.
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; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ;
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; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
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; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ;
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; ../../modules/seven_seg.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv ; ;
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; ../../modules/seven_seg_4digit.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv ; ;
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; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ;
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+----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
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@@ -217,13 +224,13 @@ on the Quartus Prime software download page.
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; ; ;
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; Dedicated logic registers ; 0 ;
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; ; ;
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; I/O pins ; 1 ;
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; I/O pins ; 40 ;
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; ; ;
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; Total DSP Blocks ; 0 ;
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; ; ;
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; Maximum fan-out node ; clk[0] ;
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; Maximum fan-out ; 1 ;
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; Total fan-out ; 1 ;
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; Total fan-out ; 40 ;
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; Average fan-out ; 0.50 ;
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+---------------------------------------------+--------+
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@@ -233,7 +240,7 @@ on the Quartus Prime software download page.
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ;
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; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 40 ; 0 ; |assignment2 ; assignment2 ; work ;
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+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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@@ -347,6 +354,58 @@ Note: In order to hide this table in the UI and the text report file, please set
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Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
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+-----------------------------------------------------------------------+
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; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit3" ;
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+---------+-------+----------+------------------------------------------+
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; Port ; Type ; Severity ; Details ;
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+---------+-------+----------+------------------------------------------+
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; rbi_inv ; Input ; Info ; Stuck at GND ;
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+---------+-------+----------+------------------------------------------+
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+-----------------------------------------------------------------------+
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; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit2" ;
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+---------+-------+----------+------------------------------------------+
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; Port ; Type ; Severity ; Details ;
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+---------+-------+----------+------------------------------------------+
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; rbi_inv ; Input ; Info ; Stuck at GND ;
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+---------+-------+----------+------------------------------------------+
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+-----------------------------------------------------------------------+
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; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit1" ;
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+---------+-------+----------+------------------------------------------+
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; Port ; Type ; Severity ; Details ;
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+---------+-------+----------+------------------------------------------+
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; rbi_inv ; Input ; Info ; Stuck at GND ;
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+---------+-------+----------+------------------------------------------+
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+-----------------------------------------------------------------------+
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; Port Connectivity Checks: "seven_seg_4digit:display|seven_seg:digit0" ;
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+---------+-------+----------+------------------------------------------+
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; Port ; Type ; Severity ; Details ;
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+---------+-------+----------+------------------------------------------+
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; rbi_inv ; Input ; Info ; Stuck at GND ;
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+---------+-------+----------+------------------------------------------+
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+------------------------------------------------------+
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; Port Connectivity Checks: "seven_seg_4digit:display" ;
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+-------------+-------+----------+---------------------+
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; Port ; Type ; Severity ; Details ;
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+-------------+-------+----------+---------------------+
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; num[15..14] ; Input ; Info ; Stuck at VCC ;
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; num[9..8] ; Input ; Info ; Stuck at VCC ;
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; num[13..10] ; Input ; Info ; Stuck at GND ;
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; num[5..2] ; Input ; Info ; Stuck at GND ;
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; num[7] ; Input ; Info ; Stuck at GND ;
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; num[6] ; Input ; Info ; Stuck at VCC ;
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; num[1] ; Input ; Info ; Stuck at VCC ;
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; num[0] ; Input ; Info ; Stuck at GND ;
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+-------------+-------+----------+---------------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Port Connectivity Checks: "shifter:SHIFTER" ;
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+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
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@@ -415,14 +474,17 @@ Note: In order to hide this table in the UI and the text report file, please set
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+-----------------------------------------------------+
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; Post-Synthesis Netlist Statistics for Top Partition ;
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+-------------------+---------------------------------+
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; Type ; Count ;
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+-------------------+---------------------------------+
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; boundary_port ; 1 ;
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; ; ;
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; Max LUT depth ; 0.00 ;
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; Average LUT depth ; 0.00 ;
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+-------------------+---------------------------------+
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+-----------------------+-----------------------------+
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; Type ; Count ;
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+-----------------------+-----------------------------+
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; arriav_lcell_comb ; 2 ;
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; normal ; 2 ;
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; 0 data inputs ; 2 ;
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; boundary_port ; 40 ;
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; ; ;
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; Max LUT depth ; 0.00 ;
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; Average LUT depth ; 0.00 ;
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+-----------------------+-----------------------------+
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+-------------------------------+
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@@ -440,11 +502,11 @@ Note: In order to hide this table in the UI and the text report file, please set
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Tue Oct 13 15:08:17 2026
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Info: Processing started: Tue Oct 13 16:18:11 2026
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
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Info (12021): Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
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Info (12021): Found 13 design units, including 13 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
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Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
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Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
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Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4
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@@ -455,200 +517,244 @@ Info (12021): Found 11 design units, including 11 entities, in source file /home
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Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
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Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
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Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
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Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
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Info (12023): Found entity 11: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3
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Info (12023): Found entity 12: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5
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Info (12023): Found entity 13: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
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Info (12127): Elaborating entity "assignment2" for the top level hierarchy
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Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(37): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 37
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Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 40
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Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 41
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Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(54): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54
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Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 57
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Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 59
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Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
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Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
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Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 42
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Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 43
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Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 49
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Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
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Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 61
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Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 68
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Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 74
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Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 77
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Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18
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Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21
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Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55
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Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 80
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Info (12128): Elaborating entity "seven_seg_4digit" for hierarchy "seven_seg_4digit:display" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 93
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Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg_4digit:display|seven_seg:digit0" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 18
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Warning (12011): Net is missing source, defaulting to GND
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Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
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Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12011): Net is missing source, defaulting to GND
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 35
|
||||
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
|
||||
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "out_seg_0[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_0[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 21
|
||||
Warning (13410): Pin "out_seg_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[1]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[4]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_1[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 22
|
||||
Warning (13410): Pin "out_seg_2[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[5]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[6]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_2[7]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 23
|
||||
Warning (13410): Pin "out_seg_3[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[2]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[3]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[4]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[5]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[6]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Warning (13410): Pin "out_seg_3[7]" is stuck at VCC File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 25
|
||||
Info (17049): 32 registers lost all their fanouts during netlist optimizations.
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 15
|
||||
Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 1 input pins
|
||||
Info (21059): Implemented 0 output pins
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings
|
||||
Info: Peak virtual memory: 425 megabytes
|
||||
Info: Processing ended: Tue Oct 13 15:08:28 2026
|
||||
Warning (21074): Design contains 8 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16
|
||||
Warning (15610): No output dependent on input pin "HID_Register[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_Register[4]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 17
|
||||
Warning (15610): No output dependent on input pin "HID_PC[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 18
|
||||
Warning (15610): No output dependent on input pin "HID_Hi_Low[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 19
|
||||
Info (21057): Implemented 40 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 8 input pins
|
||||
Info (21059): Implemented 32 output pins
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 214 warnings
|
||||
Info: Peak virtual memory: 423 megabytes
|
||||
Info: Processing ended: Tue Oct 13 16:18:22 2026
|
||||
Info: Elapsed time: 00:00:11
|
||||
Info: Total CPU time (on all processors): 00:00:24
|
||||
Info: Total CPU time (on all processors): 00:00:25
|
||||
|
||||
|
||||
Reference in new issue
Block a user