TroubleElectrical/FPGA_Uni
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Added 4 digit 7seg display module (confirmed working for now),

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Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
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TroubleElectrical committed 2026-10-13 16:32:15 +11:00
1 parent 353923eadf
commit 25a953cdc6
138 files changed
+2431 -744
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Quartus/A2/output_files/assignment2.flow.rpt
+11 -11
View File
@@ -1,5 +1,5 @@
Flow report for assignment2
Tue Oct 13 15:09:08 2026
Tue Oct 13 16:19:10 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Oct 13 15:09:08 2026 ;
; Flow Status ; Successful - Tue Oct 13 16:19:10 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -50,7 +50,7 @@ on the Quartus Prime software download page.
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 1 / 364 ( < 1 % ) ;
; Total pins ; 40 / 364 ( 11 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/13/2026 15:08:18 ;
; Start date & time ; 10/13/2026 16:18:11 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 117114050183607.179186449807774 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 117114050183607.179186869111054 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -102,12 +102,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 412 MB ; 00:00:24 ;
; Fitter ; 00:00:24 ; 1.0 ; 1336 MB ; 00:00:36 ;
; Assembler ; 00:00:06 ; 1.0 ; 521 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ;
; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 410 MB ; 00:00:25 ;
; Fitter ; 00:00:30 ; 1.0 ; 1337 MB ; 00:00:42 ;
; Assembler ; 00:00:06 ; 1.0 ; 508 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 757 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:53 ; -- ; -- ; 00:01:19 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+