Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection.
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@@ -9,11 +9,14 @@
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`include "instruction_module_classifier.sv"
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`include "alu.sv"
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`include "shifter.sv"
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`include "sign_extender.sv"
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`include "seven_seg_4digit.sv"
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module assignment2 #(width=5, ramsz=9, romsz=10) (
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input logic [0:0] clk,
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input logic [0:0] clk
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`ifdef SYNTHESIS
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,
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input logic [4:0] HID_Register,
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input logic [0:0] HID_PC,
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input logic [0:0] HID_Hi_Low,
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@@ -22,6 +25,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
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output logic[7:0] out_seg_1,
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output logic[7:0] out_seg_2,
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output logic[7:0] out_seg_3
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`endif
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);
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// Intermediate for displaying high / low of PC or Register
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logic[15:0] PC_Reg_Display;
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@@ -48,7 +52,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
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logic [0:0] en_alu;
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// Register File intermediates
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logic [1:0] flags;
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logic [2:0] flags;
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logic [2**width-1:0] rs;
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logic [2**width-1:0] rt;
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logic [2**width-1:0] rd;
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@@ -72,6 +76,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
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rs, instruction[25:21],
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rt, instruction[20:16]
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);
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// Always use sign-extension
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logic [2**width-1:0] rt_imm;
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sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
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// TODO:
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// - ALU srcB
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// - PCBranch (rel jump of 4-byte words)
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logic [2**width-1:0] rd_alu;
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alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
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@@ -79,8 +89,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
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logic [2**width-1:0] rd_shifter;
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shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
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assign rd = en_alu ? rd_alu : (en_shifter ? rd_shifter : {2**width{1'b0}});
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assign rd = (I | (R & en_alu)) ? rd_alu : ( (R & en_shifter) ? rd_shifter : {2**width{1'b1}});
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assign rd_we = M; // TODO: Verify if diagram is in order
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// Temporary Test output
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assign PC_Reg_Display = 16'hC342;
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