From 1e13de93012457bf91f01e4df6794bcb1ce1916c Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Tue, 13 Oct 2026 22:26:52 +1100
Subject: [PATCH] Updated assignment2. Created file for testing R-type
 instructions, still needs to be implemented. Consider using bind to be able
 to extract inner-scoped variables out for inspection.

---
 modules/assignment2.sv | 24 ++++++++++++++++++++----
 tests/mips-rtype.sv    |  6 ++++++
 2 files changed, 26 insertions(+), 4 deletions(-)
 create mode 100644 tests/mips-rtype.sv

diff --git a/modules/assignment2.sv b/modules/assignment2.sv
index c70ebf1..6a8d9c5 100644
--- a/modules/assignment2.sv
+++ b/modules/assignment2.sv
@@ -9,11 +9,14 @@
 `include "instruction_module_classifier.sv"
 `include "alu.sv"
 `include "shifter.sv"
+`include "sign_extender.sv"
 `include "seven_seg_4digit.sv"
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (
-	input logic [0:0] clk,
+	input logic [0:0] clk
+`ifdef SYNTHESIS
+    ,
 	input logic [4:0] HID_Register,
 	input logic [0:0] HID_PC,
 	input logic [0:0] HID_Hi_Low,
@@ -22,6 +25,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	output logic[7:0] out_seg_1,
 	output logic[7:0] out_seg_2,
 	output logic[7:0] out_seg_3
+`endif
 	);
 	// Intermediate for displaying high / low of PC or Register
 	logic[15:0] PC_Reg_Display;
@@ -48,7 +52,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [0:0] en_alu;
 	
 	// Register File intermediates
-	logic [1:0] flags;
+	logic [2:0] flags;
 	logic [2**width-1:0] rs;
 	logic [2**width-1:0] rt;
 	logic [2**width-1:0] rd;
@@ -72,6 +76,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		rs, instruction[25:21],
 		rt, instruction[20:16]
    );
+    // Always use sign-extension
+    logic [2**width-1:0] rt_imm;
+    sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
+    // TODO:
+    //  - ALU srcB
+    //  - PCBranch (rel jump of 4-byte words)
 
 	logic [2**width-1:0] rd_alu;
 	alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
@@ -79,8 +89,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd_shifter;
 	shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
-	assign rd = en_alu ? rd_alu : (en_shifter ? rd_shifter : {2**width{1'b0}});
-	
+
+	assign rd = (I | (R & en_alu)) ? rd_alu : ( (R & en_shifter) ? rd_shifter : {2**width{1'b1}});
+	assign rd_we = M; // TODO: Verify if diagram is in order
+
+
+
+
+
 	// Temporary Test output
 	assign PC_Reg_Display = 16'hC342;
 	
diff --git a/tests/mips-rtype.sv b/tests/mips-rtype.sv
new file mode 100644
index 0000000..36608c0
--- /dev/null
+++ b/tests/mips-rtype.sv
@@ -0,0 +1,6 @@
+`include "assignment2.sv"
+
+
+module mips_rtype_tb(input logic [0:0] clk);
+    assignment2 #(5) CPU (clk);
+endmodule
\ No newline at end of file