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Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

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TroubleElectrical committed 2026-10-13 13:24:44 +11:00
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Quartus/A2/output_files/assignment2.asm.rpt
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Assembler report for assignment2
Tue Oct 13 13:24:02 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: assignment2.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Oct 13 13:24:02 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+----------------------------------------------------------------------------------+
; Assembler Generated Files ;
+----------------------------------------------------------------------------------+
; File Name ;
+----------------------------------------------------------------------------------+
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/output_files/assignment2.sof ;
+----------------------------------------------------------------------------------+
+-------------------------------------------+
; Assembler Device Options: assignment2.sof ;
+----------------+--------------------------+
; Option ; Setting ;
+----------------+--------------------------+
; JTAG usercode ; 0x0077D665 ;
; Checksum ; 0x0077D665 ;
+----------------+--------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 13:23:57 2026
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 521 megabytes
Info: Processing ended: Tue Oct 13 13:24:02 2026
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
Quartus/A2/output_files/assignment2.done
+1
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@@ -0,0 +1 @@
Tue Oct 13 13:24:11 2026
Quartus/A2/output_files/assignment2.eda.rpt
+94
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@@ -0,0 +1,94 @@
EDA Netlist Writer report for assignment2
Tue Oct 13 13:24:10 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Oct 13 13:24:10 2026 ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Tool Name ; Questa Altera FPGA (SystemVerilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
+---------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------------+
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/assignment2.svo ;
+---------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 13:24:09 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 666 megabytes
Info: Processing ended: Tue Oct 13 13:24:10 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Quartus/A2/output_files/assignment2.fit.rpt
+1294
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File diff suppressed because it is too large. Load diff
Quartus/A2/output_files/assignment2.fit.summary
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Fitter Status : Successful - Tue Oct 13 13:23:55 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 1 / 364 ( < 1 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Total DSP Blocks : 0 / 150 ( 0 % )
Total HSSI RX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )
Total HSSI TX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )
Quartus/A2/output_files/assignment2.flow.rpt
+41 -23
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@@ -1,5 +1,5 @@
Flow report for assignment2
Tue Oct 13 12:21:52 2026
Tue Oct 13 13:24:10 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -38,24 +38,29 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------------+-------------------------------------------------+
; Flow Status ; Flow Failed - Tue Oct 13 12:21:52 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-------------------------------------------------+
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Oct 13 13:24:10 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 1 / 364 ( < 1 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ;
; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ;
; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ;
; Total PLLs ; 0 / 12 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+-------------------------------------------------+
+-----------------------------------------+
@@ -63,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/13/2026 12:21:43 ;
; Start date & time ; 10/13/2026 13:23:17 ;
; Main task ; Compilation ;
; Revision Name ; assignment2 ;
+-------------------+---------------------+
@@ -74,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.179185450204071 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 152226744081900.179185819706755 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -88,6 +93,7 @@ on the Quartus Prime software download page.
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; VERILOG_MACRO ; QUARTUS_SYNTH ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
@@ -96,8 +102,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:25 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:25 ;
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 410 MB ; 00:00:24 ;
; Fitter ; 00:00:26 ; 1.0 ; 1336 MB ; 00:00:36 ;
; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ;
; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
@@ -107,6 +117,10 @@ on the Quartus Prime software download page.
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+---------------------+------------+------------+----------------+
; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
+----------------------+---------------------+------------+------------+----------------+
@@ -114,6 +128,10 @@ on the Quartus Prime software download page.
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
quartus_sta assignment2 -c assignment2
quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
Quartus/A2/output_files/assignment2.jdi
+8
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@@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="5180cceddd4354cbfc68"/>
</project>
<file_info>
<file device="5CGXFC5C6F27C7" path="assignment2.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>
Quartus/A2/output_files/assignment2.map.rpt
+504 -33
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for assignment2
Tue Oct 13 12:21:52 2026
Tue Oct 13 13:23:28 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -10,7 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Messages
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Parameter Settings for User Entity Instance: Top-level Entity: |assignment2
11. Parameter Settings for User Entity Instance: instruction_counter:PC
12. Parameter Settings for User Entity Instance: rom:ROM
13. Parameter Settings for User Entity Instance: register_file:REGS
14. Parameter Settings for User Entity Instance: alu:ALU
15. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit
16. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit
17. Parameter Settings for User Entity Instance: shifter:SHIFTER
18. Port Connectivity Checks: "shifter:SHIFTER"
19. Port Connectivity Checks: "alu:ALU"
20. Port Connectivity Checks: "register_file:REGS"
21. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER"
22. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER"
23. Port Connectivity Checks: "instruction_counter:PC"
24. Post-Synthesis Netlist Statistics for Top Partition
25. Elapsed Time Per Partition
26. Analysis & Synthesis Messages
@@ -34,22 +55,27 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Failed - Tue Oct 13 12:21:52 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-------------------------------------------------+
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Oct 13 13:23:27 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 1 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
@@ -155,29 +181,474 @@ on the Quartus Prime software download page.
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
; ../../modules/assignment2.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv ; ;
; ../../modules/rom.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv ; ;
; ../../modules/ram.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv ; ;
; ../../modules/register_file.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv ; ;
; ../../modules/instruction_counter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv ; ;
; ../../modules/instruction_classifier.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv ; ;
; ../../modules/instruction_module_classifier.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv ; ;
; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ;
; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ;
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ;
+----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------+
; Resource ; Usage ;
+---------------------------------------------+--------+
; Estimate of Logic utilization (ALMs needed) ; 0 ;
; ; ;
; Combinational ALUT usage for logic ; 0 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 0 ;
; -- <=3 input functions ; 0 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 1 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; clk[0] ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 1 ;
; Average fan-out ; 0.50 ;
+---------------------------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+--------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+--------------------+
; instruction_counter:PC|pc[0..31] ; Lost fanout ;
; Total Number of Removed Registers = 32 ; ;
+----------------------------------------+--------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |assignment2 ;
+----------------+-------+----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------------------------+
; width ; 5 ; Signed Integer ;
; ramsz ; 9 ; Signed Integer ;
; romsz ; 10 ; Signed Integer ;
+----------------+-------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: instruction_counter:PC ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------+
; width ; 5 ; Signed Integer ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom:ROM ;
+----------------+-------+-----------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------+
; m ; 10 ; Signed Integer ;
; p ; 32 ; Signed Integer ;
+----------------+-------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: register_file:REGS ;
+----------------+-------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------------+
; width ; 5 ; Signed Integer ;
; nregs ; 5 ; Signed Integer ;
+----------------+-------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------+
; Parameter Settings for User Entity Instance: alu:ALU ;
+----------------+-------+-----------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------+
; width ; 5 ; Signed Integer ;
+----------------+-------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------+
; width ; 5 ; Signed Integer ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit ;
+----------------+-------+-------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------+
; width ; 5 ; Signed Integer ;
+----------------+-------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: shifter:SHIFTER ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------+
; width ; 5 ; Signed Integer ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "shifter:SHIFTER" ;
+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
; B ; Input ; Warning ; Input port expression (5 bits) is smaller than the input port (32 bits) it drives. Extra input bit(s) "B[31..5]" will be connected to GND. ;
; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "alu:ALU" ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; flags ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "register_file:REGS" ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; RD2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; en_shifter ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; en_jmp ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; en_mul ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; en_alu ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER" ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; R ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; B1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; J ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; B2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; I ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; F ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; M ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "instruction_counter:PC" ;
+------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; W ; Input ; Warning ; Input port expression (10 bits) is smaller than the input port (32 bits) it drives. Extra input bit(s) "W[31..10]" will be connected to GND. ;
; addr ; Output ; Warning ; Output or bidir port (32 bits) is wider than the port expression (10 bits) it drives; bit(s) "addr[31..10]" have no fanouts ;
+------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-------------------+---------------------------------+
; Type ; Count ;
+-------------------+---------------------------------+
; boundary_port ; 1 ;
; ; ;
; Max LUT depth ; 0.00 ;
; Average LUT depth ; 0.00 ;
+-------------------+---------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 12:21:42 2026
Info: Processing started: Tue Oct 13 13:23:17 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_we" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_addr" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Error (10170): Verilog HDL syntax error at assignment2.sv(27) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 27
Error (10170): Verilog HDL syntax error at assignment2.sv(28) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28
Error (10170): Verilog HDL syntax error at assignment2.sv(29) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 29
Error (10112): Ignored design unit "assignment2" at assignment2.sv(20) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20
Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning
Error: Peak virtual memory: 400 megabytes
Error: Processing ended: Tue Oct 13 12:21:52 2026
Error: Elapsed time: 00:00:10
Error: Total CPU time (on all processors): 00:00:25
Info (12021): Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4
Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4
Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3
Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4
Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4
Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Info (12127): Elaborating entity "assignment2" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(48): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 48
Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 51
Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52
Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 53
Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54
Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 60
Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 63
Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18
Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21
Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 66
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12011): Net is missing source, defaulting to GND
Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (17049): 32 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26
Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 0 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings
Info: Peak virtual memory: 423 megabytes
Info: Processing ended: Tue Oct 13 13:23:28 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:25
Quartus/A2/output_files/assignment2.map.summary
+13 -8
View File
@@ -1,12 +1,17 @@
Analysis & Synthesis Status : Failed - Tue Oct 13 12:21:52 2026
Analysis & Synthesis Status : Successful - Tue Oct 13 13:23:27 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : assignment2
Top-level Entity Name : assignment2
Family : Cyclone V
Logic utilization (in ALMs) : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 1
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0
Quartus/A2/output_files/assignment2.pin
+750
View File
@@ -0,0 +1,750 @@
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
-- Bank 3B: 2.5V
-- Bank 4A: 2.5V
-- Bank 5A: 2.5V
-- Bank 5B: 2.5V
-- Bank 6A: 2.5V
-- Bank 7A: 2.5V
-- Bank 8A: 2.5V
-- Bank 9A: Dedicated configuration pins only, no VCCIO required.
-- RREF : External reference resistor for the quad, MUST be connected to
-- GND via a 2k Ohm resistor.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND*
-- either individually through a 10k Ohm resistor to GND or tie all pins
-- together and connect through a single 10k Ohm resistor to GND.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
-- must not be connected.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
CHIP "assignment2" ASSIGNED TO AN: 5CGXFC5C6F27C7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
MSEL2 : A2 : : : : 9A :
DNU : A3 : : : : :
DNU : A4 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
CONF_DONE : A6 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A :
VCCIO7A : A10 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A :
GND : A15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
VCCIO7A : A20 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
GND : A25 : gnd : : : :
GND : AA1 : gnd : : : :
GND : AA2 : gnd : : : :
GXB_NC : AA3 : : : : B0L :
GXB_NC : AA4 : : : : B0L :
GND : AA5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
VCC_AUX : AA8 : power : : 2.5V : :
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCIO3B : AA10 : power : : 2.5V : 3B :
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
NC : AA12 : : : : :
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4A :
GND : AA15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
VCCIO4A : AA20 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B :
GND : AA25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
GND : AB1 : : : : B0L :
GND : AB2 : : : : B0L :
GND : AB3 : gnd : : : :
GND : AB4 : gnd : : : :
AS_DATA2, DATA2 : AB5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A :
NC : AB7 : : : : :
GND : AB8 : gnd : : : :
VCCPD3A : AB9 : power : : 2.5V : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
VCCIO4A : AB13 : power : : 2.5V : 4A :
VCC_AUX : AB14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
GND : AB18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A :
VCC_AUX : AB20 : power : : 2.5V : :
VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A :
VCCIO5A : AB23 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B :
GND : AC1 : gnd : : : :
GND : AC2 : gnd : : : :
GXB_NC : AC3 : : : : B0L :
GXB_NC : AC4 : : : : B0L :
GND : AC5 : gnd : : : :
VCCIO3A : AC6 : power : : 2.5V : 3A :
VREFB3AN0 : AC7 : power : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
GND : AC11 : gnd : : : :
VREFB3BN0 : AC12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
VCCIO4A : AC16 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
GND : AC21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B :
GND : AC26 : gnd : : : :
GND : AD1 : : : : B0L :
GND : AD2 : : : : B0L :
GND : AD3 : gnd : : : :
GND : AD4 : gnd : : : :
AS_DATA1, DATA1 : AD5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
VCCIO3B : AD9 : power : : 2.5V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A :
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
VCCIO4A : AD19 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
GND : AD24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A :
GND : AE1 : gnd : : : :
GND : AE2 : gnd : : : :
GXB_NC : AE3 : : : : B0L :
GXB_NC : AE4 : : : : B0L :
GND : AE5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B :
GND : AE7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
VCCIO4A : AE12 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
GND : AE17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
VCCIO4A : AE22 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A :
GND : AF2 : gnd : : : :
GND : AF3 : gnd : : : :
GND : AF4 : gnd : : : :
AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B :
GND : AF10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
VCCIO4A : AF15 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
GND : AF20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
GND : AF25 : gnd : : : :
RREF : B1 : : : : :
GND : B2 : gnd : : : :
GND : B3 : gnd : : : :
GND : B4 : gnd : : : :
nSTATUS : B5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A :
GND : B8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A :
VCCIO7A : B13 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A :
VREFB7AN0 : B16 : power : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A :
GND : B18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
VCCIO7A : B23 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
GND : C1 : gnd : : : :
GND : C2 : gnd : : : :
NC : C3 : : : : :
NC : C4 : : : : :
GND : C5 : gnd : : : :
VCCIO8A : C6 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
VREFB8AN0 : C8 : power : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7A :
GND : C11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A :
VCCIO7A : C16 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A :
GND : C21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
DNU : C24 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 6A :
VCCIO6A : C26 : power : : 2.5V : 6A :
NC : D1 : : : : :
NC : D2 : : : : :
GND : D3 : gnd : : : :
GND : D4 : gnd : : : :
nCE : D5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A :
VCCIO8A : D9 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A :
GND : D14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A :
VCCIO7A : D19 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A :
GND : D23 : : : : 7A :
GND : D24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A :
GND : E1 : gnd : : : :
GND : E2 : gnd : : : :
NC : E3 : : : : :
NC : E4 : : : : :
GND : E5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A :
GND : E7 : gnd : : : :
VCCBAT : E8 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A :
VCCIO7A : E12 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
VCC_AUX : E14 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7A :
GND : E17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6A :
VCCIO6A : E22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A :
NC : F1 : : : : :
NC : F2 : : : : :
GND : F3 : gnd : : : :
GND : F4 : gnd : : : :
nCONFIG : F5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
GND : F10 : gnd : : : :
VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A :
DNU : F14 : : : : :
VCCIO7A : F15 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A :
VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A :
VCCPD7A8A : F19 : power : : 2.5V : 7A, 8A :
GND : F20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A :
VCCIO6A : F25 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
GND : G1 : gnd : : : :
GND : G2 : gnd : : : :
NC : G3 : : : : :
NC : G4 : : : : :
GND : G5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
VCCIO8A : G8 : power : : 2.5V : 8A :
VCC_AUX : G9 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7A :
GND : G13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A :
VCCIO7A : G18 : power : : 2.5V : 7A :
VCC_AUX : G19 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A :
VCCA_FPLL : G21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A :
GND : G23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
NC : H1 : : : : :
NC : H2 : : : : :
GND : H3 : gnd : : : :
GND : H4 : gnd : : : :
GND : H5 : : : : 9A :
GND : H6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
VCCIO7A : H11 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A :
GND : H16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A :
VCCIO6A : H21 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
GND : H26 : gnd : : : :
GND : J1 : gnd : : : :
GND : J2 : gnd : : : :
VCCL_GXBL : J3 : power : : 1.1V : :
GND : J4 : gnd : : : :
MSEL4 : J5 : : : : 9A :
VCCA_FPLL : J6 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A :
GND : J9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7A :
VCC : J13 : power : : 1.1V : :
GND : J14 : gnd : : : :
VCC : J15 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7A :
VCC : J17 : power : : 1.1V : :
GND : J18 : gnd : : : :
VCC : J19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A :
VCCPD6A : J22 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
VCCIO6A : J24 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
GXB_NC : K1 : : : : B1L :
GXB_NC : K2 : : : : B1L :
GND : K3 : gnd : : : :
VCCE_GXBL : K4 : power : : 1.1V : :
MSEL3 : K5 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 8A :
VCCIO8A : K7 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
VCC : K14 : power : : 1.1V : :
GND : K15 : gnd : : : :
VCC : K16 : power : : 1.1V : :
GND : K17 : gnd : : : :
VCC : K18 : power : : 1.1V : :
GND : K19 : gnd : : : :
VCC : K20 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
GND : K22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
GND : L1 : gnd : : : :
GND : L2 : gnd : : : :
VCCH_GXBL : L3 : power : : 2.5V : :
GND : L4 : gnd : : : :
NC : L5 : : : : :
MSEL1 : L6 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 8A :
GND : L10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 7A :
VCC : L13 : power : : 1.1V : :
GND : L14 : gnd : : : :
VCC : L15 : power : : 1.1V : :
GND : L16 : gnd : : : :
VCC : L17 : power : : 1.1V : :
GND : L18 : gnd : : : :
VCC : L19 : power : : 1.1V : :
GND : L20 : gnd : : : :
VCCPD6A : L21 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
GND : L25 : gnd : : : :
VREFB6AN0 : L26 : power : : : 6A :
GND : M1 : : : : B1L :
GND : M2 : : : : B1L :
GND : M3 : gnd : : : :
VCCE_GXBL : M4 : power : : 1.1V : :
GND : M5 : gnd : : : :
NC : M6 : : : : :
MSEL0 : M7 : : : : 9A :
GND : M8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 7A :
GND : M13 : gnd : : : :
VCC : M14 : power : : 1.1V : :
GND : M15 : gnd : : : :
VCC : M16 : power : : 1.1V : :
GND : M17 : gnd : : : :
VCC : M18 : power : : 1.1V : :
GND : M19 : gnd : : : :
VCC : M20 : power : : 1.1V : :
clk[0] : M21 : input : 2.5 V : : 6A : N
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
VCCIO6A : M23 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
GND : N1 : gnd : : : :
GND : N2 : gnd : : : :
VCCL_GXBL : N3 : power : : 1.1V : :
GND : N4 : gnd : : : :
VCCE_GXBL : N5 : power : : 1.1V : :
GND : N6 : gnd : : : :
GND : N7 : : : : B1L :
DCLK : N8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N10 : : : : 3B :
GND : N11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 7A :
VCC : N13 : power : : 1.1V : :
GND : N14 : gnd : : : :
VCC : N15 : power : : 1.1V : :
GND : N16 : gnd : : : :
VCC : N17 : power : : 1.1V : :
GND : N18 : gnd : : : :
VCC : N19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A :
GND : N21 : gnd : : : :
VCCPD5B : N22 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 5B :
VCCIO5B : N26 : power : : 2.5V : 5B :
GXB_NC : P1 : : : : B1L :
GXB_NC : P2 : : : : B1L :
GND : P3 : gnd : : : :
VCCE_GXBL : P4 : power : : 1.1V : :
GND : P5 : gnd : : : :
GND : P6 : : : : B1L :
GND : P7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A :
GND : P9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B :
GND : P13 : gnd : : : :
VCC : P14 : power : : 1.1V : :
GND : P15 : gnd : : : :
VCC : P16 : power : : 1.1V : :
GND : P17 : gnd : : : :
VCC : P18 : power : : 1.1V : :
GND : P19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B :
GND : P24 : gnd : : : :
VREFB5BN0 : P25 : power : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 5B :
GND : R1 : gnd : : : :
GND : R2 : gnd : : : :
VCCH_GXBL : R3 : power : : 2.5V : :
GND : R4 : gnd : : : :
VCCE_GXBL : R5 : power : : 1.1V : :
TMS : R6 : input : : : 3A :
GND : R7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B :
GND : R12 : gnd : : : :
VCC : R13 : power : : 1.1V : :
GND : R14 : gnd : : : :
VCC : R15 : power : : 1.1V : :
GND : R16 : gnd : : : :
VCC : R17 : power : : 1.1V : :
GND : R18 : gnd : : : :
VCC : R19 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5B :
VCCPD5B : R21 : power : : 2.5V : 5B :
VCCIO5B : R22 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5B :
GND : T1 : : : : B1L :
GND : T2 : : : : B1L :
GND : T3 : gnd : : : :
VCCH_GXBL : T4 : power : : 2.5V : :
GND : T5 : gnd : : : :
TDI : T6 : input : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B :
GND : T10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B :
VCC : T14 : power : : 1.1V : :
GND : T15 : gnd : : : :
VCC : T16 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 4A :
VCC : T18 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5A :
GND : T20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B :
VCCIO5B : T25 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5B :
GND : U1 : gnd : : : :
GND : U2 : gnd : : : :
VCCL_GXBL : U3 : power : : 1.1V : :
GND : U4 : gnd : : : :
VCCE_GXBL : U5 : power : : 1.1V : :
AS_DATA3, DATA3 : U6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
VCCIO3B : U8 : power : : 2.5V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A :
GND : U13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
VCCIO4A : U18 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
VCCPD5A : U21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A :
GND : U23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B :
GND : V1 : : : : B1L :
GND : V2 : : : : B1L :
GND : V3 : gnd : : : :
GND : V4 : gnd : : : :
GND : V5 : gnd : : : :
GND : V6 : : : : B0L :
TDO : V7 : output : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
VCCIO3B : V11 : power : : 2.5V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
GND : V16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
VCCIO5A : V21 : power : : 2.5V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
GND : V26 : gnd : : : :
GND : W1 : gnd : : : :
GND : W2 : gnd : : : :
GXB_NC : W3 : : : : B1L :
GXB_NC : W4 : : : : B1L :
GND : W5 : gnd : : : :
GND : W6 : : : : B0L :
VCCA_FPLL : W7 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
GND : W9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
VCCIO4A : W14 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A :
GND : W19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : :
VREFB5AN0 : W23 : power : : : 5A :
VCCIO5B : W24 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B :
GND : Y1 : : : : B0L :
GND : Y2 : : : : B0L :
GND : Y3 : gnd : : : :
GND : Y4 : gnd : : : :
TCK : Y5 : input : : : 3A :
nCSO, DATA4 : Y6 : : : : 3A :
VCCIO3A : Y7 : power : : 2.5V : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
VCCIO4A : Y17 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A :
VCCA_FPLL : Y21 : power : : 2.5V : :
GND : Y22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
Quartus/A2/output_files/assignment2.sld
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Quartus/A2/output_files/assignment2.sof
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Timing Analyzer report for assignment2
Tue Oct 13 13:24:08 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1100mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1100mV 85C Model Setup Summary
8. Slow 1100mV 85C Model Hold Summary
9. Slow 1100mV 85C Model Recovery Summary
10. Slow 1100mV 85C Model Removal Summary
11. Slow 1100mV 85C Model Minimum Pulse Width Summary
12. Slow 1100mV 85C Model Metastability Summary
13. Slow 1100mV 0C Model Fmax Summary
14. Slow 1100mV 0C Model Setup Summary
15. Slow 1100mV 0C Model Hold Summary
16. Slow 1100mV 0C Model Recovery Summary
17. Slow 1100mV 0C Model Removal Summary
18. Slow 1100mV 0C Model Minimum Pulse Width Summary
19. Slow 1100mV 0C Model Metastability Summary
20. Fast 1100mV 85C Model Setup Summary
21. Fast 1100mV 85C Model Hold Summary
22. Fast 1100mV 85C Model Recovery Summary
23. Fast 1100mV 85C Model Removal Summary
24. Fast 1100mV 85C Model Minimum Pulse Width Summary
25. Fast 1100mV 85C Model Metastability Summary
26. Fast 1100mV 0C Model Setup Summary
27. Fast 1100mV 0C Model Hold Summary
28. Fast 1100mV 0C Model Recovery Summary
29. Fast 1100mV 0C Model Removal Summary
30. Fast 1100mV 0C Model Minimum Pulse Width Summary
31. Fast 1100mV 0C Model Metastability Summary
32. Multicorner Timing Analysis Summary
33. Board Trace Model Assignments
34. Input Transition Times
35. Signal Integrity Metrics (Slow 1100mv 0c Model)
36. Signal Integrity Metrics (Slow 1100mv 85c Model)
37. Signal Integrity Metrics (Fast 1100mv 0c Model)
38. Signal Integrity Metrics (Fast 1100mv 85c Model)
39. Clock Transfers
40. Report TCCS
41. Report RSKM
42. Unconstrained Paths Summary
43. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+---------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------+
; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; assignment2 ;
; Device Family ; Cyclone V ;
; Device Name ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+---------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.1% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1100mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
---------------------------------------
; Slow 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1100mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
---------------------------------------
; Fast 1100mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Fast 1100mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Fast 1100mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Fast 1100mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1100mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1100mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1100mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1100mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1100mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-----------------------------------------------------------+
; Input Transition Times ;
+--------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------+--------------+-----------------+-----------------+
; clk[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
+--------+--------------+-----------------+-----------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 0 ; 0 ;
; Unconstrained Output Port Paths ; 0 ; 0 ;
+---------------------------------+-------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Oct 13 13:24:04 2026
Info: Command: quartus_sta assignment2 -c assignment2
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1100mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1100mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 85C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1100mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 718 megabytes
Info: Processing ended: Tue Oct 13 13:24:08 2026
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
Quartus/A2/output_files/assignment2.sta.summary
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Timing Analyzer Summary
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