diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf index d08adfc..43e3ff2 100644 --- a/Quartus/A2/assignment2.qsf +++ b/Quartus/A2/assignment2.qsf @@ -35,6 +35,7 @@ # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # +set_global_assignment -name VERILOG_MACRO QUARTUS_SYNTH set_global_assignment -name FAMILY "Cyclone V" @@ -58,4 +59,5 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/A2/c5_pin_model_dump.txt b/Quartus/A2/c5_pin_model_dump.txt new file mode 100644 index 0000000..3a3970c --- /dev/null +++ b/Quartus/A2/c5_pin_model_dump.txt @@ -0,0 +1,88 @@ +io_4iomodule_c5_index: 61gpio_index: 2 +io_4iomodule_c5_index: 62gpio_index: 348 +io_4iomodule_c5_index: 40gpio_index: 6 +io_4iomodule_c5_index: 59gpio_index: 344 +io_4iomodule_c5_index: 31gpio_index: 10 +io_4iomodule_c5_index: 35gpio_index: 340 +io_4iomodule_c5_index: 42gpio_index: 14 +io_4iomodule_c5_index: 19gpio_index: 336 +io_4iomodule_c5_index: 29gpio_index: 19 +io_4iomodule_c5_index: 9gpio_index: 332 +io_4iomodule_c5_index: 34gpio_index: 22 +io_4iomodule_c5_index: 25gpio_index: 328 +io_4iomodule_c5_index: 17gpio_index: 27 +io_4iomodule_c5_index: 44gpio_index: 324 +io_4iomodule_c5_index: 57gpio_index: 30 +io_4iomodule_c5_index: 13gpio_index: 320 +io_4iomodule_c5_index: 5gpio_index: 35 +io_4iomodule_c5_index: 39gpio_index: 316 +io_4iomodule_c5_index: 14gpio_index: 38 +io_4iomodule_c5_index: 27gpio_index: 312 +io_4iomodule_c5_index: 21gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 308 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 26gpio_index: 304 +io_4iomodule_c5_index: 1gpio_index: 51 +io_4iomodule_c5_index: 38gpio_index: 300 +io_4iomodule_c5_index: 50gpio_index: 54 +io_4iomodule_c5_index: 36gpio_index: 296 +io_4iomodule_c5_index: 11gpio_index: 59 +io_4iomodule_c5_index: 2gpio_index: 292 +io_4iomodule_c5_index: 4gpio_index: 62 +io_4iomodule_c5_index: 6gpio_index: 288 +io_4iomodule_c5_index: 48gpio_index: 67 +io_4iomodule_c5_index: 24gpio_index: 284 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 12gpio_index: 280 +io_4iomodule_c5_index: 49gpio_index: 75 +io_4iomodule_c5_index: 63gpio_index: 276 +io_4iomodule_c5_index: 41gpio_index: 78 +io_4iomodule_c5_index: 37gpio_index: 272 +io_4iomodule_c5_index: 3gpio_index: 83 +io_4iomodule_c5_index: 33gpio_index: 268 +io_4iomodule_c5_index: 22gpio_index: 86 +io_4iomodule_c5_index: 54gpio_index: 264 +io_4iomodule_c5_index: 56gpio_index: 91 +io_4iomodule_c5_index: 32gpio_index: 260 +io_4iomodule_c5_index: 53gpio_index: 94 +io_4iomodule_c5_index: 52gpio_index: 256 +io_4iomodule_c5_index: 28gpio_index: 99 +io_4iomodule_c5_index: 45gpio_index: 252 +io_4iomodule_c5_index: 10gpio_index: 102 +io_4iomodule_c5_index: 43gpio_index: 248 +io_4iomodule_c5_index: 15gpio_index: 107 +io_4iomodule_c5_index: 7gpio_index: 244 +io_4iomodule_c5_index: 55gpio_index: 110 +io_4iomodule_c5_index: 60gpio_index: 240 +io_4iomodule_c5_index: 18gpio_index: 115 +io_4iomodule_c5_index: 58gpio_index: 236 +io_4iomodule_c5_index: 46gpio_index: 118 +io_4iomodule_c5_index: 30gpio_index: 232 +io_4iomodule_c5_index: 16gpio_index: 123 +io_4iomodule_c5_index: 47gpio_index: 228 +io_4iomodule_c5_index: 51gpio_index: 126 +io_4iomodule_c5_index: 23gpio_index: 224 +io_4iomodule_h_c5_index: 0gpio_index: 129 +io_4iomodule_h_c5_index: 18gpio_index: 133 +io_4iomodule_h_c5_index: 15gpio_index: 137 +io_4iomodule_h_c5_index: 16gpio_index: 141 +io_4iomodule_h_c5_index: 20gpio_index: 144 +io_4iomodule_h_c5_index: 23gpio_index: 148 +io_4iomodule_h_c5_index: 12gpio_index: 152 +io_4iomodule_h_c5_index: 9gpio_index: 156 +io_4iomodule_h_c5_index: 1gpio_index: 160 +io_4iomodule_h_c5_index: 5gpio_index: 164 +io_4iomodule_h_c5_index: 21gpio_index: 168 +io_4iomodule_h_c5_index: 6gpio_index: 172 +io_4iomodule_h_c5_index: 17gpio_index: 176 +io_4iomodule_h_c5_index: 2gpio_index: 180 +io_4iomodule_h_c5_index: 4gpio_index: 184 +io_4iomodule_h_c5_index: 3gpio_index: 188 +io_4iomodule_h_c5_index: 14gpio_index: 192 +io_4iomodule_h_c5_index: 7gpio_index: 196 +io_4iomodule_h_c5_index: 19gpio_index: 200 +io_4iomodule_h_c5_index: 11gpio_index: 204 +io_4iomodule_h_c5_index: 8gpio_index: 208 +io_4iomodule_h_c5_index: 13gpio_index: 212 +io_4iomodule_h_c5_index: 22gpio_index: 216 +io_4iomodule_h_c5_index: 10gpio_index: 220 diff --git a/Quartus/A2/db/.cmp.kpt b/Quartus/A2/db/.cmp.kpt new file mode 100644 index 0000000..26cea02 Binary files /dev/null and b/Quartus/A2/db/.cmp.kpt differ diff --git a/Quartus/A2/db/assignment2.(0).cnf.cdb b/Quartus/A2/db/assignment2.(0).cnf.cdb new file mode 100644 index 0000000..86191e5 Binary files /dev/null and b/Quartus/A2/db/assignment2.(0).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(0).cnf.hdb b/Quartus/A2/db/assignment2.(0).cnf.hdb new file mode 100644 index 0000000..fe7757f Binary files /dev/null and b/Quartus/A2/db/assignment2.(0).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(1).cnf.cdb b/Quartus/A2/db/assignment2.(1).cnf.cdb new file mode 100644 index 0000000..42a27d0 Binary files /dev/null and b/Quartus/A2/db/assignment2.(1).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(1).cnf.hdb b/Quartus/A2/db/assignment2.(1).cnf.hdb new file mode 100644 index 0000000..2add43c Binary files /dev/null and b/Quartus/A2/db/assignment2.(1).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(10).cnf.cdb b/Quartus/A2/db/assignment2.(10).cnf.cdb new file mode 100644 index 0000000..5ead60b Binary files /dev/null and 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0000000..47bbcda Binary files /dev/null and b/Quartus/A2/db/assignment2.(7).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(8).cnf.cdb b/Quartus/A2/db/assignment2.(8).cnf.cdb new file mode 100644 index 0000000..2a604ae Binary files /dev/null and b/Quartus/A2/db/assignment2.(8).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(8).cnf.hdb b/Quartus/A2/db/assignment2.(8).cnf.hdb new file mode 100644 index 0000000..1a73fee Binary files /dev/null and b/Quartus/A2/db/assignment2.(8).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.(9).cnf.cdb b/Quartus/A2/db/assignment2.(9).cnf.cdb new file mode 100644 index 0000000..74fd5e2 Binary files /dev/null and b/Quartus/A2/db/assignment2.(9).cnf.cdb differ diff --git a/Quartus/A2/db/assignment2.(9).cnf.hdb b/Quartus/A2/db/assignment2.(9).cnf.hdb new file mode 100644 index 0000000..298e937 Binary files /dev/null and b/Quartus/A2/db/assignment2.(9).cnf.hdb differ diff --git a/Quartus/A2/db/assignment2.asm.qmsg b/Quartus/A2/db/assignment2.asm.qmsg new file mode 100644 index 0000000..6039628 --- /dev/null +++ b/Quartus/A2/db/assignment2.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858237264 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858237264 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:23:57 2026 " "Processing started: Tue Oct 13 13:23:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858237264 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1791858237264 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1791858237265 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1791858237920 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1791858242577 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:02 2026 " "Processing ended: Tue Oct 13 13:24:02 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858242788 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1791858242788 ""} diff --git a/Quartus/A2/db/assignment2.asm.rdb b/Quartus/A2/db/assignment2.asm.rdb new file mode 100644 index 0000000..c2890f5 Binary files /dev/null and b/Quartus/A2/db/assignment2.asm.rdb differ diff --git a/Quartus/A2/db/assignment2.cbx.xml b/Quartus/A2/db/assignment2.cbx.xml new file mode 100644 index 0000000..6f19457 --- /dev/null +++ b/Quartus/A2/db/assignment2.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Quartus/A2/db/assignment2.cmp.bpm b/Quartus/A2/db/assignment2.cmp.bpm new file mode 100644 index 0000000..c7f3f4e Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp.bpm differ diff --git a/Quartus/A2/db/assignment2.cmp.cdb b/Quartus/A2/db/assignment2.cmp.cdb new file mode 100644 index 0000000..972f0fe Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp.cdb differ diff --git a/Quartus/A2/db/assignment2.cmp.hdb b/Quartus/A2/db/assignment2.cmp.hdb new file mode 100644 index 0000000..65d3d5f Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp.hdb differ diff --git a/Quartus/A2/db/assignment2.cmp.idb b/Quartus/A2/db/assignment2.cmp.idb new file mode 100644 index 0000000..22d6cc5 Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp.idb differ diff --git a/Quartus/A2/db/assignment2.cmp.logdb b/Quartus/A2/db/assignment2.cmp.logdb new file mode 100644 index 0000000..ade96ef --- /dev/null +++ b/Quartus/A2/db/assignment2.cmp.logdb @@ -0,0 +1,40 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Outputs with single-ended I/O Standard or Differential I/O Standard assignments found.,,I/O,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;1;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;1;1;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,1;1;1;1;1;0;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;0;0;1, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,clk[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,28, +IO_RULES_SUMMARY,Number of I/O Rules Passed,3, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,25, diff --git a/Quartus/A2/db/assignment2.cmp.rdb b/Quartus/A2/db/assignment2.cmp.rdb index 3d32a8e..5e57a07 100644 Binary files a/Quartus/A2/db/assignment2.cmp.rdb and b/Quartus/A2/db/assignment2.cmp.rdb differ diff --git a/Quartus/A2/db/assignment2.cmp_merge.kpt b/Quartus/A2/db/assignment2.cmp_merge.kpt new file mode 100644 index 0000000..b0aa5d0 Binary files /dev/null and b/Quartus/A2/db/assignment2.cmp_merge.kpt differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..b19b6d1 Binary files /dev/null and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_85c_fast.hsd new file mode 100644 index 0000000..b6ce56d Binary files /dev/null and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ff_85c_fast.hsd differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_0c_slow.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..9729dee Binary files /dev/null and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_0c_slow.hsd differ diff --git a/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..118df22 Binary files /dev/null and b/Quartus/A2/db/assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A2/db/assignment2.db_info b/Quartus/A2/db/assignment2.db_info index d4bd959..5ad97f3 100644 --- a/Quartus/A2/db/assignment2.db_info +++ b/Quartus/A2/db/assignment2.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Tue Oct 13 12:03:19 2026 +Creation_Time = Tue Oct 13 13:03:37 2026 diff --git a/Quartus/A2/db/assignment2.eda.qmsg b/Quartus/A2/db/assignment2.eda.qmsg new file mode 100644 index 0000000..760072d --- /dev/null +++ b/Quartus/A2/db/assignment2.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858250029 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858250030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:24:09 2026 " "Processing started: Tue Oct 13 13:24:09 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858250030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250030 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250030 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1791858250784 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "assignment2.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/ simulation " "Generated file assignment2.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1791858250806 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "666 " "Peak virtual memory: 666 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:10 2026 " "Processing ended: Tue Oct 13 13:24:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858250847 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1791858250847 ""} diff --git a/Quartus/A2/db/assignment2.fit.qmsg b/Quartus/A2/db/assignment2.fit.qmsg new file mode 100644 index 0000000..32f7ed4 --- /dev/null +++ b/Quartus/A2/db/assignment2.fit.qmsg @@ -0,0 +1,44 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1791858210293 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1791858210293 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "assignment2 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"assignment2\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1791858210299 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791858210371 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1791858210371 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1791858210811 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1791858210862 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1791858211023 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 1 " "No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1791858211324 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1791858218162 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858218200 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1791858218218 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791858218218 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1791858218218 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1791858218219 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1791858218219 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1791858218219 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1791858218219 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1791858218219 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1791858218219 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858218231 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1791858224323 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1791858224324 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1791858224324 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1791858224327 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1791858224328 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1791858224328 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1791858224328 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1791858224332 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1791858224375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858224856 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1791858225113 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1791858225375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858225375 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1791858225943 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1791858231476 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1791858231476 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1791858231618 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1791858231618 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1791858231618 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858231621 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1791858232496 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791858232532 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791858232916 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1791858232916 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1791858233422 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1791858234687 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1336 " "Peak virtual memory: 1336 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:23:55 2026 " "Processing ended: Tue Oct 13 13:23:55 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Elapsed time: 00:00:26" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858235491 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1791858235491 ""} diff --git a/Quartus/A2/db/assignment2.hier_info b/Quartus/A2/db/assignment2.hier_info new file mode 100644 index 0000000..522df96 --- /dev/null +++ b/Quartus/A2/db/assignment2.hier_info @@ -0,0 +1,1554 @@ +|assignment2 +clk[0] => clk[0].IN2 + + +|assignment2|instruction_counter:PC +clk[0] => pc[0].CLK +clk[0] => pc[1].CLK +clk[0] => pc[2].CLK +clk[0] => pc[3].CLK +clk[0] => pc[4].CLK +clk[0] => pc[5].CLK +clk[0] => pc[6].CLK +clk[0] => pc[7].CLK +clk[0] => pc[8].CLK +clk[0] => pc[9].CLK +clk[0] => pc[10].CLK +clk[0] => pc[11].CLK +clk[0] => pc[12].CLK +clk[0] => pc[13].CLK +clk[0] => pc[14].CLK +clk[0] => pc[15].CLK +clk[0] => pc[16].CLK +clk[0] => pc[17].CLK +clk[0] => pc[18].CLK +clk[0] => pc[19].CLK +clk[0] => pc[20].CLK +clk[0] => pc[21].CLK +clk[0] => pc[22].CLK +clk[0] => pc[23].CLK +clk[0] => pc[24].CLK +clk[0] => pc[25].CLK +clk[0] => pc[26].CLK +clk[0] => pc[27].CLK +clk[0] => pc[28].CLK +clk[0] => pc[29].CLK +clk[0] => pc[30].CLK +clk[0] => pc[31].CLK +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc.OUTPUTSELECT +we[0] => pc[0].ENA +we[0] => pc[1].ENA +W[0] => pc[0].DATAIN +W[1] => pc[1].DATAIN +W[2] => pc.DATAB +W[3] => pc.DATAB +W[4] => pc.DATAB +W[5] => pc.DATAB +W[6] => pc.DATAB +W[7] => pc.DATAB +W[8] => pc.DATAB +W[9] => pc.DATAB +W[10] => pc.DATAB +W[11] => pc.DATAB +W[12] => pc.DATAB +W[13] => pc.DATAB +W[14] => pc.DATAB +W[15] => pc.DATAB +W[16] => pc.DATAB +W[17] => pc.DATAB +W[18] => pc.DATAB +W[19] => pc.DATAB +W[20] => pc.DATAB +W[21] => pc.DATAB +W[22] => pc.DATAB +W[23] => pc.DATAB +W[24] => pc.DATAB +W[25] => pc.DATAB +W[26] => pc.DATAB +W[27] => pc.DATAB +W[28] => pc.DATAB +W[29] => pc.DATAB +W[30] => pc.DATAB +W[31] => pc.DATAB +addr[0] <= pc[0].DB_MAX_OUTPUT_PORT_TYPE +addr[1] <= pc[1].DB_MAX_OUTPUT_PORT_TYPE +addr[2] <= pc[2].DB_MAX_OUTPUT_PORT_TYPE +addr[3] <= pc[3].DB_MAX_OUTPUT_PORT_TYPE +addr[4] <= pc[4].DB_MAX_OUTPUT_PORT_TYPE +addr[5] <= pc[5].DB_MAX_OUTPUT_PORT_TYPE +addr[6] <= pc[6].DB_MAX_OUTPUT_PORT_TYPE +addr[7] <= pc[7].DB_MAX_OUTPUT_PORT_TYPE +addr[8] <= pc[8].DB_MAX_OUTPUT_PORT_TYPE +addr[9] <= pc[9].DB_MAX_OUTPUT_PORT_TYPE +addr[10] <= pc[10].DB_MAX_OUTPUT_PORT_TYPE +addr[11] <= pc[11].DB_MAX_OUTPUT_PORT_TYPE +addr[12] <= pc[12].DB_MAX_OUTPUT_PORT_TYPE +addr[13] <= pc[13].DB_MAX_OUTPUT_PORT_TYPE +addr[14] <= pc[14].DB_MAX_OUTPUT_PORT_TYPE +addr[15] <= pc[15].DB_MAX_OUTPUT_PORT_TYPE +addr[16] <= pc[16].DB_MAX_OUTPUT_PORT_TYPE +addr[17] <= pc[17].DB_MAX_OUTPUT_PORT_TYPE +addr[18] <= pc[18].DB_MAX_OUTPUT_PORT_TYPE +addr[19] <= pc[19].DB_MAX_OUTPUT_PORT_TYPE +addr[20] <= pc[20].DB_MAX_OUTPUT_PORT_TYPE +addr[21] <= pc[21].DB_MAX_OUTPUT_PORT_TYPE +addr[22] <= pc[22].DB_MAX_OUTPUT_PORT_TYPE +addr[23] <= pc[23].DB_MAX_OUTPUT_PORT_TYPE +addr[24] <= pc[24].DB_MAX_OUTPUT_PORT_TYPE +addr[25] <= pc[25].DB_MAX_OUTPUT_PORT_TYPE +addr[26] <= pc[26].DB_MAX_OUTPUT_PORT_TYPE +addr[27] <= pc[27].DB_MAX_OUTPUT_PORT_TYPE +addr[28] <= pc[28].DB_MAX_OUTPUT_PORT_TYPE +addr[29] <= pc[29].DB_MAX_OUTPUT_PORT_TYPE +addr[30] <= pc[30].DB_MAX_OUTPUT_PORT_TYPE +addr[31] <= pc[31].DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|rom:ROM +Ad[0] => mem.RADDR +Ad[1] => mem.RADDR1 +Ad[2] => mem.RADDR2 +Ad[3] => mem.RADDR3 +Ad[4] => mem.RADDR4 +Ad[5] => mem.RADDR5 +Ad[6] => mem.RADDR6 +Ad[7] => mem.RADDR7 +Ad[8] => mem.RADDR8 +Ad[9] => mem.RADDR9 +Dout[0] <= mem.DATAOUT +Dout[1] <= mem.DATAOUT1 +Dout[2] <= mem.DATAOUT2 +Dout[3] <= mem.DATAOUT3 +Dout[4] <= mem.DATAOUT4 +Dout[5] <= mem.DATAOUT5 +Dout[6] <= mem.DATAOUT6 +Dout[7] <= mem.DATAOUT7 +Dout[8] <= mem.DATAOUT8 +Dout[9] <= mem.DATAOUT9 +Dout[10] <= mem.DATAOUT10 +Dout[11] <= mem.DATAOUT11 +Dout[12] <= mem.DATAOUT12 +Dout[13] <= mem.DATAOUT13 +Dout[14] <= mem.DATAOUT14 +Dout[15] <= mem.DATAOUT15 +Dout[16] <= mem.DATAOUT16 +Dout[17] <= mem.DATAOUT17 +Dout[18] <= mem.DATAOUT18 +Dout[19] <= mem.DATAOUT19 +Dout[20] <= mem.DATAOUT20 +Dout[21] <= mem.DATAOUT21 +Dout[22] <= mem.DATAOUT22 +Dout[23] <= mem.DATAOUT23 +Dout[24] <= mem.DATAOUT24 +Dout[25] <= mem.DATAOUT25 +Dout[26] <= mem.DATAOUT26 +Dout[27] <= mem.DATAOUT27 +Dout[28] <= mem.DATAOUT28 +Dout[29] <= mem.DATAOUT29 +Dout[30] <= mem.DATAOUT30 +Dout[31] <= mem.DATAOUT31 + + +|assignment2|instruction_classifier:INSTRUCTION_CLASSIFIER +op[0] => Equal0.IN5 +op[0] => Equal1.IN0 +op[1] => Equal0.IN4 +op[1] => Equal1.IN5 +op[1] => Equal2.IN0 +op[2] => Equal0.IN3 +op[2] => Equal1.IN4 +op[2] => Equal2.IN4 +op[2] => Equal3.IN0 +op[3] => Equal0.IN2 +op[3] => Equal1.IN3 +op[3] => Equal2.IN3 +op[3] => Equal3.IN3 +op[3] => Equal4.IN0 +op[4] => Equal0.IN1 +op[4] => Equal1.IN2 +op[4] => Equal2.IN2 +op[4] => Equal3.IN2 +op[4] => Equal4.IN2 +op[4] => Equal5.IN0 +op[5] => M[0].DATAIN +op[5] => Equal0.IN0 +op[5] => Equal1.IN1 +op[5] => Equal2.IN1 +op[5] => Equal3.IN1 +op[5] => Equal4.IN1 +op[5] => Equal5.IN1 +R[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE +B1[0] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE +J[0] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE +B2[0] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE +I[0] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE +F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE +M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER +op[0] => Equal0.IN2 +op[0] => Equal1.IN0 +op[1] => Equal0.IN1 +op[1] => Equal1.IN2 +op[1] => Equal2.IN0 +op[2] => en_alu.DATAIN +op[2] => Equal0.IN0 +op[2] => Equal1.IN1 +op[2] => Equal2.IN1 +en_shifter <= Equal0.DB_MAX_OUTPUT_PORT_TYPE +en_jmp <= Equal1.DB_MAX_OUTPUT_PORT_TYPE +en_mul <= Equal2.DB_MAX_OUTPUT_PORT_TYPE +en_alu <= op[2].DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|register_file:REGS +clk[0] => regs.we_a.CLK +clk[0] => regs.waddr_a[4].CLK +clk[0] => regs.waddr_a[3].CLK +clk[0] => regs.waddr_a[2].CLK +clk[0] => regs.waddr_a[1].CLK +clk[0] => regs.waddr_a[0].CLK +clk[0] => regs.data_a[31].CLK +clk[0] => regs.data_a[30].CLK +clk[0] => regs.data_a[29].CLK +clk[0] => regs.data_a[28].CLK +clk[0] => regs.data_a[27].CLK +clk[0] => regs.data_a[26].CLK +clk[0] => regs.data_a[25].CLK +clk[0] => regs.data_a[24].CLK +clk[0] => regs.data_a[23].CLK +clk[0] => regs.data_a[22].CLK +clk[0] => regs.data_a[21].CLK +clk[0] => regs.data_a[20].CLK +clk[0] => regs.data_a[19].CLK +clk[0] => regs.data_a[18].CLK +clk[0] => regs.data_a[17].CLK +clk[0] => regs.data_a[16].CLK +clk[0] => regs.data_a[15].CLK +clk[0] => regs.data_a[14].CLK +clk[0] => regs.data_a[13].CLK +clk[0] => regs.data_a[12].CLK +clk[0] => regs.data_a[11].CLK +clk[0] => regs.data_a[10].CLK +clk[0] => regs.data_a[9].CLK +clk[0] => regs.data_a[8].CLK +clk[0] => regs.data_a[7].CLK +clk[0] => regs.data_a[6].CLK +clk[0] => regs.data_a[5].CLK +clk[0] => regs.data_a[4].CLK +clk[0] => regs.data_a[3].CLK +clk[0] => regs.data_a[2].CLK +clk[0] => regs.data_a[1].CLK +clk[0] => regs.data_a[0].CLK +clk[0] => regs.CLK0 +we[0] => always0.IN1 +WA[0] => regs.waddr_a[0].DATAIN +WA[0] => Equal0.IN31 +WA[0] => regs.WADDR +WA[1] => regs.waddr_a[1].DATAIN +WA[1] => Equal0.IN30 +WA[1] => regs.WADDR1 +WA[2] => regs.waddr_a[2].DATAIN +WA[2] => Equal0.IN29 +WA[2] => regs.WADDR2 +WA[3] => regs.waddr_a[3].DATAIN +WA[3] => Equal0.IN28 +WA[3] => regs.WADDR3 +WA[4] => regs.waddr_a[4].DATAIN +WA[4] => Equal0.IN27 +WA[4] => regs.WADDR4 +WD[0] => regs.data_a[0].DATAIN +WD[0] => regs.DATAIN +WD[1] => regs.data_a[1].DATAIN +WD[1] => regs.DATAIN1 +WD[2] => regs.data_a[2].DATAIN +WD[2] => regs.DATAIN2 +WD[3] => regs.data_a[3].DATAIN +WD[3] => regs.DATAIN3 +WD[4] => regs.data_a[4].DATAIN +WD[4] => regs.DATAIN4 +WD[5] => regs.data_a[5].DATAIN +WD[5] => regs.DATAIN5 +WD[6] => regs.data_a[6].DATAIN +WD[6] => regs.DATAIN6 +WD[7] => regs.data_a[7].DATAIN +WD[7] => regs.DATAIN7 +WD[8] => regs.data_a[8].DATAIN +WD[8] => regs.DATAIN8 +WD[9] => regs.data_a[9].DATAIN +WD[9] => regs.DATAIN9 +WD[10] => regs.data_a[10].DATAIN +WD[10] => regs.DATAIN10 +WD[11] => regs.data_a[11].DATAIN +WD[11] => regs.DATAIN11 +WD[12] => regs.data_a[12].DATAIN +WD[12] => regs.DATAIN12 +WD[13] => regs.data_a[13].DATAIN +WD[13] => regs.DATAIN13 +WD[14] => regs.data_a[14].DATAIN +WD[14] => regs.DATAIN14 +WD[15] => regs.data_a[15].DATAIN +WD[15] => regs.DATAIN15 +WD[16] => regs.data_a[16].DATAIN +WD[16] => regs.DATAIN16 +WD[17] => regs.data_a[17].DATAIN +WD[17] => regs.DATAIN17 +WD[18] => regs.data_a[18].DATAIN +WD[18] => regs.DATAIN18 +WD[19] => regs.data_a[19].DATAIN +WD[19] => regs.DATAIN19 +WD[20] => regs.data_a[20].DATAIN +WD[20] => regs.DATAIN20 +WD[21] => regs.data_a[21].DATAIN +WD[21] => regs.DATAIN21 +WD[22] => regs.data_a[22].DATAIN +WD[22] => regs.DATAIN22 +WD[23] => regs.data_a[23].DATAIN +WD[23] => regs.DATAIN23 +WD[24] => regs.data_a[24].DATAIN +WD[24] => regs.DATAIN24 +WD[25] => regs.data_a[25].DATAIN +WD[25] => regs.DATAIN25 +WD[26] => regs.data_a[26].DATAIN +WD[26] => regs.DATAIN26 +WD[27] => regs.data_a[27].DATAIN +WD[27] => regs.DATAIN27 +WD[28] => regs.data_a[28].DATAIN +WD[28] => regs.DATAIN28 +WD[29] => regs.data_a[29].DATAIN +WD[29] => regs.DATAIN29 +WD[30] => regs.data_a[30].DATAIN +WD[30] => regs.DATAIN30 +WD[31] => regs.data_a[31].DATAIN +WD[31] => regs.DATAIN31 +RA1[0] => regs.RADDR +RA1[1] => regs.RADDR1 +RA1[2] => regs.RADDR2 +RA1[3] => regs.RADDR3 +RA1[4] => regs.RADDR4 +RD1[0] <= regs.DATAOUT +RD1[1] <= regs.DATAOUT1 +RD1[2] <= regs.DATAOUT2 +RD1[3] <= regs.DATAOUT3 +RD1[4] <= regs.DATAOUT4 +RD1[5] <= regs.DATAOUT5 +RD1[6] <= regs.DATAOUT6 +RD1[7] <= regs.DATAOUT7 +RD1[8] <= regs.DATAOUT8 +RD1[9] <= regs.DATAOUT9 +RD1[10] <= regs.DATAOUT10 +RD1[11] <= regs.DATAOUT11 +RD1[12] <= regs.DATAOUT12 +RD1[13] <= regs.DATAOUT13 +RD1[14] <= regs.DATAOUT14 +RD1[15] <= regs.DATAOUT15 +RD1[16] <= regs.DATAOUT16 +RD1[17] <= regs.DATAOUT17 +RD1[18] <= regs.DATAOUT18 +RD1[19] <= regs.DATAOUT19 +RD1[20] <= regs.DATAOUT20 +RD1[21] <= regs.DATAOUT21 +RD1[22] <= regs.DATAOUT22 +RD1[23] <= regs.DATAOUT23 +RD1[24] <= regs.DATAOUT24 +RD1[25] <= regs.DATAOUT25 +RD1[26] <= regs.DATAOUT26 +RD1[27] <= regs.DATAOUT27 +RD1[28] <= regs.DATAOUT28 +RD1[29] <= regs.DATAOUT29 +RD1[30] <= regs.DATAOUT30 +RD1[31] <= regs.DATAOUT31 +RA2[0] => regs.PORTBRADDR +RA2[1] => regs.PORTBRADDR1 +RA2[2] => regs.PORTBRADDR2 +RA2[3] => regs.PORTBRADDR3 +RA2[4] => regs.PORTBRADDR4 +RD2[0] <= regs.PORTBDATAOUT +RD2[1] <= regs.PORTBDATAOUT1 +RD2[2] <= regs.PORTBDATAOUT2 +RD2[3] <= regs.PORTBDATAOUT3 +RD2[4] <= regs.PORTBDATAOUT4 +RD2[5] <= regs.PORTBDATAOUT5 +RD2[6] <= regs.PORTBDATAOUT6 +RD2[7] <= regs.PORTBDATAOUT7 +RD2[8] <= regs.PORTBDATAOUT8 +RD2[9] <= regs.PORTBDATAOUT9 +RD2[10] <= regs.PORTBDATAOUT10 +RD2[11] <= regs.PORTBDATAOUT11 +RD2[12] <= regs.PORTBDATAOUT12 +RD2[13] <= regs.PORTBDATAOUT13 +RD2[14] <= regs.PORTBDATAOUT14 +RD2[15] <= regs.PORTBDATAOUT15 +RD2[16] <= regs.PORTBDATAOUT16 +RD2[17] <= regs.PORTBDATAOUT17 +RD2[18] <= regs.PORTBDATAOUT18 +RD2[19] <= regs.PORTBDATAOUT19 +RD2[20] <= regs.PORTBDATAOUT20 +RD2[21] <= regs.PORTBDATAOUT21 +RD2[22] <= regs.PORTBDATAOUT22 +RD2[23] <= regs.PORTBDATAOUT23 +RD2[24] <= regs.PORTBDATAOUT24 +RD2[25] <= regs.PORTBDATAOUT25 +RD2[26] <= regs.PORTBDATAOUT26 +RD2[27] <= regs.PORTBDATAOUT27 +RD2[28] <= regs.PORTBDATAOUT28 +RD2[29] <= regs.PORTBDATAOUT29 +RD2[30] <= regs.PORTBDATAOUT30 +RD2[31] <= regs.PORTBDATAOUT31 + + +|assignment2|alu:ALU +op[0] => op[0].IN1 +op[1] => op[1].IN1 +op[2] => Mux0.IN3 +op[2] => Mux1.IN3 +op[2] => Mux2.IN3 +op[2] => Mux3.IN3 +op[2] => Mux4.IN3 +op[2] => Mux5.IN3 +op[2] => Mux6.IN3 +op[2] => Mux7.IN3 +op[2] => Mux8.IN3 +op[2] => Mux9.IN3 +op[2] => Mux10.IN3 +op[2] => Mux11.IN3 +op[2] => Mux12.IN3 +op[2] => Mux13.IN3 +op[2] => Mux14.IN3 +op[2] => Mux15.IN3 +op[2] => Mux16.IN3 +op[2] => Mux17.IN3 +op[2] => Mux18.IN3 +op[2] => Mux19.IN3 +op[2] => Mux20.IN3 +op[2] => Mux21.IN3 +op[2] => Mux22.IN3 +op[2] => Mux23.IN3 +op[2] => Mux24.IN3 +op[2] => Mux25.IN3 +op[2] => Mux26.IN3 +op[2] => Mux27.IN3 +op[2] => Mux28.IN3 +op[2] => Mux29.IN3 +op[2] => Mux30.IN3 +op[2] => Mux31.IN9 +op[3] => Mux0.IN2 +op[3] => Mux1.IN2 +op[3] => Mux2.IN2 +op[3] => Mux3.IN2 +op[3] => Mux4.IN2 +op[3] => Mux5.IN2 +op[3] => Mux6.IN2 +op[3] => Mux7.IN2 +op[3] => Mux8.IN2 +op[3] => Mux9.IN2 +op[3] => Mux10.IN2 +op[3] => Mux11.IN2 +op[3] => Mux12.IN2 +op[3] => Mux13.IN2 +op[3] => Mux14.IN2 +op[3] => Mux15.IN2 +op[3] => Mux16.IN2 +op[3] => Mux17.IN2 +op[3] => Mux18.IN2 +op[3] => Mux19.IN2 +op[3] => Mux20.IN2 +op[3] => Mux21.IN2 +op[3] => Mux22.IN2 +op[3] => Mux23.IN2 +op[3] => Mux24.IN2 +op[3] => Mux25.IN2 +op[3] => Mux26.IN2 +op[3] => Mux27.IN2 +op[3] => Mux28.IN2 +op[3] => Mux29.IN2 +op[3] => Mux30.IN2 +op[3] => Mux31.IN8 +A[0] => A[0].IN2 +A[1] => A[1].IN2 +A[2] => A[2].IN2 +A[3] => A[3].IN2 +A[4] => A[4].IN2 +A[5] => A[5].IN2 +A[6] => A[6].IN2 +A[7] => A[7].IN2 +A[8] => A[8].IN2 +A[9] => A[9].IN2 +A[10] => A[10].IN2 +A[11] => A[11].IN2 +A[12] => A[12].IN2 +A[13] => A[13].IN2 +A[14] => A[14].IN2 +A[15] => A[15].IN2 +A[16] => A[16].IN2 +A[17] => A[17].IN2 +A[18] => A[18].IN2 +A[19] => A[19].IN2 +A[20] => A[20].IN2 +A[21] => A[21].IN2 +A[22] => A[22].IN2 +A[23] => A[23].IN2 +A[24] => A[24].IN2 +A[25] => A[25].IN2 +A[26] => A[26].IN2 +A[27] => A[27].IN2 +A[28] => A[28].IN2 +A[29] => A[29].IN2 +A[30] => A[30].IN2 +A[31] => A[31].IN2 +B[0] => B[0].IN2 +B[1] => B[1].IN2 +B[2] => B[2].IN2 +B[3] => B[3].IN2 +B[4] => B[4].IN2 +B[5] => B[5].IN2 +B[6] => B[6].IN2 +B[7] => B[7].IN2 +B[8] => B[8].IN2 +B[9] => B[9].IN2 +B[10] => B[10].IN2 +B[11] => B[11].IN2 +B[12] => B[12].IN2 +B[13] => B[13].IN2 +B[14] => B[14].IN2 +B[15] => B[15].IN2 +B[16] => B[16].IN2 +B[17] => B[17].IN2 +B[18] => B[18].IN2 +B[19] => B[19].IN2 +B[20] => B[20].IN2 +B[21] => B[21].IN2 +B[22] => B[22].IN2 +B[23] => B[23].IN2 +B[24] => B[24].IN2 +B[25] => B[25].IN2 +B[26] => B[26].IN2 +B[27] => B[27].IN2 +B[28] => B[28].IN2 +B[29] => B[29].IN2 +B[30] => B[30].IN2 +B[31] => B[31].IN2 +OUT_1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +flags[0] <= asu:adder_unit.port4 +flags[1] <= asu:adder_unit.port5 + + +|assignment2|alu:ALU|asu:adder_unit +op[0] => operand[31].OUTPUTSELECT +op[0] => operand[30].OUTPUTSELECT +op[0] => operand[29].OUTPUTSELECT +op[0] => operand[28].OUTPUTSELECT +op[0] => operand[27].OUTPUTSELECT +op[0] => operand[26].OUTPUTSELECT +op[0] => operand[25].OUTPUTSELECT +op[0] => operand[24].OUTPUTSELECT +op[0] => operand[23].OUTPUTSELECT +op[0] => operand[22].OUTPUTSELECT +op[0] => operand[21].OUTPUTSELECT +op[0] => operand[20].OUTPUTSELECT +op[0] => operand[19].OUTPUTSELECT +op[0] => operand[18].OUTPUTSELECT +op[0] => operand[17].OUTPUTSELECT +op[0] => operand[16].OUTPUTSELECT +op[0] => operand[15].OUTPUTSELECT +op[0] => operand[14].OUTPUTSELECT +op[0] => operand[13].OUTPUTSELECT +op[0] => operand[12].OUTPUTSELECT +op[0] => operand[11].OUTPUTSELECT +op[0] => operand[10].OUTPUTSELECT +op[0] => operand[9].OUTPUTSELECT +op[0] => operand[8].OUTPUTSELECT +op[0] => operand[7].OUTPUTSELECT +op[0] => operand[6].OUTPUTSELECT +op[0] => operand[5].OUTPUTSELECT +op[0] => operand[4].OUTPUTSELECT +op[0] => operand[3].OUTPUTSELECT +op[0] => operand[2].OUTPUTSELECT +op[0] => operand[1].OUTPUTSELECT +op[0] => operand[0].OUTPUTSELECT +op[0] => _.DATAB +A[0] => _.DATAD +A[1] => _.DATAD +A[2] => _.DATAD +A[3] => _.DATAD +A[4] => _.DATAD +A[5] => _.DATAD +A[6] => _.DATAD +A[7] => _.DATAD +A[8] => _.DATAD +A[9] => _.DATAD +A[10] => _.DATAD +A[11] => _.DATAD +A[12] => _.DATAD +A[13] => _.DATAD +A[14] => _.DATAD +A[15] => _.DATAD +A[16] => _.DATAD +A[17] => _.DATAD +A[18] => _.DATAD +A[19] => _.DATAD +A[20] => _.DATAD +A[21] => _.DATAD +A[22] => _.DATAD +A[23] => _.DATAD +A[24] => _.DATAD +A[25] => _.DATAD +A[26] => _.DATAD +A[27] => _.DATAD +A[28] => _.DATAD +A[29] => _.DATAD +A[30] => _.DATAD +A[31] => OUT_CIN.IN1 +A[31] => _.DATAD +B[0] => operand[0].DATAB +B[0] => operand[0].DATAA +B[1] => operand[1].DATAB +B[1] => operand[1].DATAA +B[2] => operand[2].DATAB +B[2] => operand[2].DATAA +B[3] => operand[3].DATAB +B[3] => operand[3].DATAA +B[4] => operand[4].DATAB +B[4] => operand[4].DATAA +B[5] => operand[5].DATAB +B[5] => operand[5].DATAA +B[6] => operand[6].DATAB +B[6] => operand[6].DATAA +B[7] => operand[7].DATAB +B[7] => operand[7].DATAA +B[8] => operand[8].DATAB +B[8] => operand[8].DATAA +B[9] => operand[9].DATAB +B[9] => operand[9].DATAA +B[10] => operand[10].DATAB +B[10] => operand[10].DATAA +B[11] => operand[11].DATAB +B[11] => operand[11].DATAA +B[12] => operand[12].DATAB +B[12] => operand[12].DATAA +B[13] => operand[13].DATAB +B[13] => operand[13].DATAA +B[14] => operand[14].DATAB +B[14] => operand[14].DATAA +B[15] => operand[15].DATAB +B[15] => operand[15].DATAA +B[16] => operand[16].DATAB +B[16] => operand[16].DATAA +B[17] => operand[17].DATAB +B[17] => operand[17].DATAA +B[18] => operand[18].DATAB +B[18] => operand[18].DATAA +B[19] => operand[19].DATAB +B[19] => operand[19].DATAA +B[20] => operand[20].DATAB +B[20] => operand[20].DATAA +B[21] => operand[21].DATAB +B[21] => operand[21].DATAA +B[22] => operand[22].DATAB +B[22] => operand[22].DATAA +B[23] => operand[23].DATAB +B[23] => operand[23].DATAA +B[24] => operand[24].DATAB +B[24] => operand[24].DATAA +B[25] => operand[25].DATAB +B[25] => operand[25].DATAA +B[26] => operand[26].DATAB +B[26] => operand[26].DATAA +B[27] => operand[27].DATAB +B[27] => operand[27].DATAA +B[28] => operand[28].DATAB +B[28] => operand[28].DATAA +B[29] => operand[29].DATAB +B[29] => operand[29].DATAA +B[30] => operand[30].DATAB +B[30] => operand[30].DATAA +B[31] => operand[31].DATAB +B[31] => operand[31].DATAA +OUT_1[0] <= _.SUM_OUT +OUT_1[1] <= _.SUM_OUT +OUT_1[2] <= _.SUM_OUT +OUT_1[3] <= _.SUM_OUT +OUT_1[4] <= _.SUM_OUT +OUT_1[5] <= _.SUM_OUT +OUT_1[6] <= _.SUM_OUT +OUT_1[7] <= _.SUM_OUT +OUT_1[8] <= _.SUM_OUT +OUT_1[9] <= _.SUM_OUT +OUT_1[10] <= _.SUM_OUT +OUT_1[11] <= _.SUM_OUT +OUT_1[12] <= _.SUM_OUT +OUT_1[13] <= _.SUM_OUT +OUT_1[14] <= _.SUM_OUT +OUT_1[15] <= _.SUM_OUT +OUT_1[16] <= _.SUM_OUT +OUT_1[17] <= _.SUM_OUT +OUT_1[18] <= _.SUM_OUT +OUT_1[19] <= _.SUM_OUT +OUT_1[20] <= _.SUM_OUT +OUT_1[21] <= _.SUM_OUT +OUT_1[22] <= _.SUM_OUT +OUT_1[23] <= _.SUM_OUT +OUT_1[24] <= _.SUM_OUT +OUT_1[25] <= _.SUM_OUT +OUT_1[26] <= _.SUM_OUT +OUT_1[27] <= _.SUM_OUT +OUT_1[28] <= _.SUM_OUT +OUT_1[29] <= _.SUM_OUT +OUT_1[30] <= _.SUM_OUT +OUT_1[31] <= _.SUM_OUT +COUT[0] <= _.SUM_OUT +OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|alu:ALU|lu:logic_unit +op[0] => Mux0.IN5 +op[0] => Mux1.IN5 +op[0] => Mux2.IN5 +op[0] => Mux3.IN5 +op[0] => Mux4.IN5 +op[0] => Mux5.IN5 +op[0] => Mux6.IN5 +op[0] => Mux7.IN5 +op[0] => Mux8.IN5 +op[0] => Mux9.IN5 +op[0] => Mux10.IN5 +op[0] => Mux11.IN5 +op[0] => Mux12.IN5 +op[0] => Mux13.IN5 +op[0] => Mux14.IN5 +op[0] => Mux15.IN5 +op[0] => Mux16.IN5 +op[0] => Mux17.IN5 +op[0] => Mux18.IN5 +op[0] => Mux19.IN5 +op[0] => Mux20.IN5 +op[0] => Mux21.IN5 +op[0] => Mux22.IN5 +op[0] => Mux23.IN5 +op[0] => Mux24.IN5 +op[0] => Mux25.IN5 +op[0] => Mux26.IN5 +op[0] => Mux27.IN5 +op[0] => Mux28.IN5 +op[0] => Mux29.IN5 +op[0] => Mux30.IN5 +op[0] => Mux31.IN5 +op[1] => Mux0.IN4 +op[1] => Mux1.IN4 +op[1] => Mux2.IN4 +op[1] => Mux3.IN4 +op[1] => Mux4.IN4 +op[1] => Mux5.IN4 +op[1] => Mux6.IN4 +op[1] => Mux7.IN4 +op[1] => Mux8.IN4 +op[1] => Mux9.IN4 +op[1] => Mux10.IN4 +op[1] => Mux11.IN4 +op[1] => Mux12.IN4 +op[1] => Mux13.IN4 +op[1] => Mux14.IN4 +op[1] => Mux15.IN4 +op[1] => Mux16.IN4 +op[1] => Mux17.IN4 +op[1] => Mux18.IN4 +op[1] => Mux19.IN4 +op[1] => Mux20.IN4 +op[1] => Mux21.IN4 +op[1] => Mux22.IN4 +op[1] => Mux23.IN4 +op[1] => Mux24.IN4 +op[1] => Mux25.IN4 +op[1] => Mux26.IN4 +op[1] => Mux27.IN4 +op[1] => Mux28.IN4 +op[1] => Mux29.IN4 +op[1] => Mux30.IN4 +op[1] => Mux31.IN4 +A[0] => Y.IN0 +A[0] => Y.IN0 +A[0] => Y.IN0 +A[1] => Y.IN0 +A[1] => Y.IN0 +A[1] => Y.IN0 +A[2] => Y.IN0 +A[2] => Y.IN0 +A[2] => Y.IN0 +A[3] => Y.IN0 +A[3] => Y.IN0 +A[3] => Y.IN0 +A[4] => Y.IN0 +A[4] => Y.IN0 +A[4] => Y.IN0 +A[5] => Y.IN0 +A[5] => Y.IN0 +A[5] => Y.IN0 +A[6] => Y.IN0 +A[6] => Y.IN0 +A[6] => Y.IN0 +A[7] => Y.IN0 +A[7] => Y.IN0 +A[7] => Y.IN0 +A[8] => Y.IN0 +A[8] => Y.IN0 +A[8] => Y.IN0 +A[9] => Y.IN0 +A[9] => Y.IN0 +A[9] => Y.IN0 +A[10] => Y.IN0 +A[10] => Y.IN0 +A[10] => Y.IN0 +A[11] => Y.IN0 +A[11] => Y.IN0 +A[11] => Y.IN0 +A[12] => Y.IN0 +A[12] => Y.IN0 +A[12] => Y.IN0 +A[13] => Y.IN0 +A[13] => Y.IN0 +A[13] => Y.IN0 +A[14] => Y.IN0 +A[14] => Y.IN0 +A[14] => Y.IN0 +A[15] => Y.IN0 +A[15] => Y.IN0 +A[15] => Y.IN0 +A[16] => Y.IN0 +A[16] => Y.IN0 +A[16] => Y.IN0 +A[17] => Y.IN0 +A[17] => Y.IN0 +A[17] => Y.IN0 +A[18] => Y.IN0 +A[18] => Y.IN0 +A[18] => Y.IN0 +A[19] => Y.IN0 +A[19] => Y.IN0 +A[19] => Y.IN0 +A[20] => Y.IN0 +A[20] => Y.IN0 +A[20] => Y.IN0 +A[21] => Y.IN0 +A[21] => Y.IN0 +A[21] => Y.IN0 +A[22] => Y.IN0 +A[22] => Y.IN0 +A[22] => Y.IN0 +A[23] => Y.IN0 +A[23] => Y.IN0 +A[23] => Y.IN0 +A[24] => Y.IN0 +A[24] => Y.IN0 +A[24] => Y.IN0 +A[25] => Y.IN0 +A[25] => Y.IN0 +A[25] => Y.IN0 +A[26] => Y.IN0 +A[26] => Y.IN0 +A[26] => Y.IN0 +A[27] => Y.IN0 +A[27] => Y.IN0 +A[27] => Y.IN0 +A[28] => Y.IN0 +A[28] => Y.IN0 +A[28] => Y.IN0 +A[29] => Y.IN0 +A[29] => Y.IN0 +A[29] => Y.IN0 +A[30] => Y.IN0 +A[30] => Y.IN0 +A[30] => Y.IN0 +A[31] => Y.IN0 +A[31] => Y.IN0 +A[31] => Y.IN0 +B[0] => Y.IN1 +B[0] => Y.IN1 +B[0] => Y.IN1 +B[1] => Y.IN1 +B[1] => Y.IN1 +B[1] => Y.IN1 +B[2] => Y.IN1 +B[2] => Y.IN1 +B[2] => Y.IN1 +B[3] => Y.IN1 +B[3] => Y.IN1 +B[3] => Y.IN1 +B[4] => Y.IN1 +B[4] => Y.IN1 +B[4] => Y.IN1 +B[5] => Y.IN1 +B[5] => Y.IN1 +B[5] => Y.IN1 +B[6] => Y.IN1 +B[6] => Y.IN1 +B[6] => Y.IN1 +B[7] => Y.IN1 +B[7] => Y.IN1 +B[7] => Y.IN1 +B[8] => Y.IN1 +B[8] => Y.IN1 +B[8] => Y.IN1 +B[9] => Y.IN1 +B[9] => Y.IN1 +B[9] => Y.IN1 +B[10] => Y.IN1 +B[10] => Y.IN1 +B[10] => Y.IN1 +B[11] => Y.IN1 +B[11] => Y.IN1 +B[11] => Y.IN1 +B[12] => Y.IN1 +B[12] => Y.IN1 +B[12] => Y.IN1 +B[13] => Y.IN1 +B[13] => Y.IN1 +B[13] => Y.IN1 +B[14] => Y.IN1 +B[14] => Y.IN1 +B[14] => Y.IN1 +B[15] => Y.IN1 +B[15] => Y.IN1 +B[15] => Y.IN1 +B[16] => Y.IN1 +B[16] => Y.IN1 +B[16] => Y.IN1 +B[17] => Y.IN1 +B[17] => Y.IN1 +B[17] => Y.IN1 +B[18] => Y.IN1 +B[18] => Y.IN1 +B[18] => Y.IN1 +B[19] => Y.IN1 +B[19] => Y.IN1 +B[19] => Y.IN1 +B[20] => Y.IN1 +B[20] => Y.IN1 +B[20] => Y.IN1 +B[21] => Y.IN1 +B[21] => Y.IN1 +B[21] => Y.IN1 +B[22] => Y.IN1 +B[22] => Y.IN1 +B[22] => Y.IN1 +B[23] => Y.IN1 +B[23] => Y.IN1 +B[23] => Y.IN1 +B[24] => Y.IN1 +B[24] => Y.IN1 +B[24] => Y.IN1 +B[25] => Y.IN1 +B[25] => Y.IN1 +B[25] => Y.IN1 +B[26] => Y.IN1 +B[26] => Y.IN1 +B[26] => Y.IN1 +B[27] => Y.IN1 +B[27] => Y.IN1 +B[27] => Y.IN1 +B[28] => Y.IN1 +B[28] => Y.IN1 +B[28] => Y.IN1 +B[29] => Y.IN1 +B[29] => Y.IN1 +B[29] => Y.IN1 +B[30] => Y.IN1 +B[30] => Y.IN1 +B[30] => Y.IN1 +B[31] => Y.IN1 +B[31] => Y.IN1 +B[31] => Y.IN1 +Y[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +Y[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +Y[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +Y[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +Y[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +Y[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +Y[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +Y[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +Y[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +Y[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +Y[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +Y[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +Y[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +Y[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +Y[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +Y[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +Y[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +Y[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +Y[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +Y[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +Y[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +Y[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +Y[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE +Y[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE +Y[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +Y[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +Y[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +Y[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +Y[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +Y[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +Y[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +Y[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + +|assignment2|shifter:SHIFTER +op[0] => Mux0.IN8 +op[0] => Mux1.IN8 +op[0] => Mux2.IN8 +op[0] => Mux3.IN8 +op[0] => Mux4.IN8 +op[0] => Mux5.IN8 +op[0] => Mux6.IN8 +op[0] => Mux7.IN8 +op[0] => Mux8.IN8 +op[0] => Mux9.IN8 +op[0] => Mux10.IN8 +op[0] => Mux11.IN8 +op[0] => Mux12.IN8 +op[0] => Mux13.IN8 +op[0] => Mux14.IN8 +op[0] => Mux15.IN8 +op[0] => Mux16.IN8 +op[0] => Mux17.IN8 +op[0] => Mux18.IN8 +op[0] => Mux19.IN8 +op[0] => Mux20.IN8 +op[0] => Mux21.IN8 +op[0] => Mux22.IN8 +op[0] => Mux23.IN8 +op[0] => Mux24.IN8 +op[0] => Mux25.IN8 +op[0] => Mux26.IN8 +op[0] => Mux27.IN8 +op[0] => Mux28.IN8 +op[0] => Mux29.IN8 +op[0] => Mux30.IN8 +op[0] => Mux31.IN8 +op[1] => Mux0.IN7 +op[1] => Mux1.IN7 +op[1] => Mux2.IN7 +op[1] => Mux3.IN7 +op[1] => Mux4.IN7 +op[1] => Mux5.IN7 +op[1] => Mux6.IN7 +op[1] => Mux7.IN7 +op[1] => Mux8.IN7 +op[1] => Mux9.IN7 +op[1] => Mux10.IN7 +op[1] => Mux11.IN7 +op[1] => Mux12.IN7 +op[1] => Mux13.IN7 +op[1] => Mux14.IN7 +op[1] => Mux15.IN7 +op[1] => Mux16.IN7 +op[1] => Mux17.IN7 +op[1] => Mux18.IN7 +op[1] => Mux19.IN7 +op[1] => Mux20.IN7 +op[1] => Mux21.IN7 +op[1] => Mux22.IN7 +op[1] => Mux23.IN7 +op[1] => Mux24.IN7 +op[1] => Mux25.IN7 +op[1] => Mux26.IN7 +op[1] => Mux27.IN7 +op[1] => Mux28.IN7 +op[1] => Mux29.IN7 +op[1] => Mux30.IN7 +op[1] => Mux31.IN7 +op[2] => Mux0.IN6 +op[2] => Mux1.IN6 +op[2] => Mux2.IN6 +op[2] => Mux3.IN6 +op[2] => Mux4.IN6 +op[2] => Mux5.IN6 +op[2] => Mux6.IN6 +op[2] => Mux7.IN6 +op[2] => Mux8.IN6 +op[2] => Mux9.IN6 +op[2] => Mux10.IN6 +op[2] => Mux11.IN6 +op[2] => Mux12.IN6 +op[2] => Mux13.IN6 +op[2] => Mux14.IN6 +op[2] => Mux15.IN6 +op[2] => Mux16.IN6 +op[2] => Mux17.IN6 +op[2] => Mux18.IN6 +op[2] => Mux19.IN6 +op[2] => Mux20.IN6 +op[2] => Mux21.IN6 +op[2] => Mux22.IN6 +op[2] => Mux23.IN6 +op[2] => Mux24.IN6 +op[2] => Mux25.IN6 +op[2] => Mux26.IN6 +op[2] => Mux27.IN6 +op[2] => Mux28.IN6 +op[2] => Mux29.IN6 +op[2] => Mux30.IN6 +op[2] => Mux31.IN6 +A[0] => ShiftLeft0.IN32 +A[0] => ShiftRight0.IN32 +A[0] => ShiftRight1.IN32 +A[0] => ShiftLeft1.IN32 +A[0] => ShiftRight2.IN32 +A[0] => ShiftRight3.IN32 +A[0] => Mux31.IN9 +A[0] => Mux31.IN10 +A[1] => ShiftLeft0.IN31 +A[1] => ShiftRight0.IN31 +A[1] => ShiftRight1.IN31 +A[1] => ShiftLeft1.IN31 +A[1] => ShiftRight2.IN31 +A[1] => ShiftRight3.IN31 +A[1] => Mux30.IN9 +A[1] => Mux30.IN10 +A[2] => ShiftLeft0.IN30 +A[2] => ShiftRight0.IN30 +A[2] => ShiftRight1.IN30 +A[2] => ShiftLeft1.IN30 +A[2] => ShiftRight2.IN30 +A[2] => ShiftRight3.IN30 +A[2] => Mux29.IN9 +A[2] => Mux29.IN10 +A[3] => ShiftLeft0.IN29 +A[3] => ShiftRight0.IN29 +A[3] => ShiftRight1.IN29 +A[3] => ShiftLeft1.IN29 +A[3] => ShiftRight2.IN29 +A[3] => ShiftRight3.IN29 +A[3] => Mux28.IN9 +A[3] => Mux28.IN10 +A[4] => ShiftLeft0.IN28 +A[4] => ShiftRight0.IN28 +A[4] => ShiftRight1.IN28 +A[4] => ShiftLeft1.IN28 +A[4] => ShiftRight2.IN28 +A[4] => ShiftRight3.IN28 +A[4] => Mux27.IN9 +A[4] => Mux27.IN10 +A[5] => ShiftLeft0.IN27 +A[5] => ShiftRight0.IN27 +A[5] => ShiftRight1.IN27 +A[5] => ShiftLeft1.IN27 +A[5] => ShiftRight2.IN27 +A[5] => ShiftRight3.IN27 +A[5] => Mux26.IN9 +A[5] => Mux26.IN10 +A[6] => ShiftLeft0.IN26 +A[6] => ShiftRight0.IN26 +A[6] => ShiftRight1.IN26 +A[6] => ShiftLeft1.IN26 +A[6] => ShiftRight2.IN26 +A[6] => ShiftRight3.IN26 +A[6] => Mux25.IN9 +A[6] => Mux25.IN10 +A[7] => ShiftLeft0.IN25 +A[7] => ShiftRight0.IN25 +A[7] => ShiftRight1.IN25 +A[7] => ShiftLeft1.IN25 +A[7] => ShiftRight2.IN25 +A[7] => ShiftRight3.IN25 +A[7] => Mux24.IN9 +A[7] => Mux24.IN10 +A[8] => ShiftLeft0.IN24 +A[8] => ShiftRight0.IN24 +A[8] => ShiftRight1.IN24 +A[8] => ShiftLeft1.IN24 +A[8] => ShiftRight2.IN24 +A[8] => ShiftRight3.IN24 +A[8] => Mux23.IN9 +A[8] => Mux23.IN10 +A[9] => ShiftLeft0.IN23 +A[9] => ShiftRight0.IN23 +A[9] => ShiftRight1.IN23 +A[9] => ShiftLeft1.IN23 +A[9] => ShiftRight2.IN23 +A[9] => ShiftRight3.IN23 +A[9] => Mux22.IN9 +A[9] => Mux22.IN10 +A[10] => ShiftLeft0.IN22 +A[10] => ShiftRight0.IN22 +A[10] => ShiftRight1.IN22 +A[10] => ShiftLeft1.IN22 +A[10] => ShiftRight2.IN22 +A[10] => ShiftRight3.IN22 +A[10] => Mux21.IN9 +A[10] => Mux21.IN10 +A[11] => ShiftLeft0.IN21 +A[11] => ShiftRight0.IN21 +A[11] => ShiftRight1.IN21 +A[11] => ShiftLeft1.IN21 +A[11] => ShiftRight2.IN21 +A[11] => ShiftRight3.IN21 +A[11] => Mux20.IN9 +A[11] => Mux20.IN10 +A[12] => ShiftLeft0.IN20 +A[12] => ShiftRight0.IN20 +A[12] => ShiftRight1.IN20 +A[12] => ShiftLeft1.IN20 +A[12] => ShiftRight2.IN20 +A[12] => ShiftRight3.IN20 +A[12] => Mux19.IN9 +A[12] => Mux19.IN10 +A[13] => ShiftLeft0.IN19 +A[13] => ShiftRight0.IN19 +A[13] => ShiftRight1.IN19 +A[13] => ShiftLeft1.IN19 +A[13] => ShiftRight2.IN19 +A[13] => ShiftRight3.IN19 +A[13] => Mux18.IN9 +A[13] => Mux18.IN10 +A[14] => ShiftLeft0.IN18 +A[14] => ShiftRight0.IN18 +A[14] => ShiftRight1.IN18 +A[14] => ShiftLeft1.IN18 +A[14] => ShiftRight2.IN18 +A[14] => ShiftRight3.IN18 +A[14] => Mux17.IN9 +A[14] => Mux17.IN10 +A[15] => ShiftLeft0.IN17 +A[15] => ShiftRight0.IN17 +A[15] => ShiftRight1.IN17 +A[15] => ShiftLeft1.IN17 +A[15] => ShiftRight2.IN17 +A[15] => ShiftRight3.IN17 +A[15] => Mux16.IN9 +A[15] => Mux16.IN10 +A[16] => ShiftLeft0.IN16 +A[16] => ShiftRight0.IN16 +A[16] => ShiftRight1.IN16 +A[16] => ShiftLeft1.IN16 +A[16] => ShiftRight2.IN16 +A[16] => ShiftRight3.IN16 +A[16] => Mux15.IN9 +A[16] => Mux15.IN10 +A[17] => ShiftLeft0.IN15 +A[17] => ShiftRight0.IN15 +A[17] => ShiftRight1.IN15 +A[17] => ShiftLeft1.IN15 +A[17] => ShiftRight2.IN15 +A[17] => ShiftRight3.IN15 +A[17] => Mux14.IN9 +A[17] => Mux14.IN10 +A[18] => ShiftLeft0.IN14 +A[18] => ShiftRight0.IN14 +A[18] => ShiftRight1.IN14 +A[18] => ShiftLeft1.IN14 +A[18] => ShiftRight2.IN14 +A[18] => ShiftRight3.IN14 +A[18] => Mux13.IN9 +A[18] => Mux13.IN10 +A[19] => ShiftLeft0.IN13 +A[19] => ShiftRight0.IN13 +A[19] => ShiftRight1.IN13 +A[19] => ShiftLeft1.IN13 +A[19] => ShiftRight2.IN13 +A[19] => ShiftRight3.IN13 +A[19] => Mux12.IN9 +A[19] => Mux12.IN10 +A[20] => ShiftLeft0.IN12 +A[20] => ShiftRight0.IN12 +A[20] => ShiftRight1.IN12 +A[20] => ShiftLeft1.IN12 +A[20] => ShiftRight2.IN12 +A[20] => ShiftRight3.IN12 +A[20] => Mux11.IN9 +A[20] => Mux11.IN10 +A[21] => ShiftLeft0.IN11 +A[21] => ShiftRight0.IN11 +A[21] => ShiftRight1.IN11 +A[21] => ShiftLeft1.IN11 +A[21] => ShiftRight2.IN11 +A[21] => ShiftRight3.IN11 +A[21] => Mux10.IN9 +A[21] => Mux10.IN10 +A[22] => ShiftLeft0.IN10 +A[22] => ShiftRight0.IN10 +A[22] => ShiftRight1.IN10 +A[22] => ShiftLeft1.IN10 +A[22] => ShiftRight2.IN10 +A[22] => ShiftRight3.IN10 +A[22] => Mux9.IN9 +A[22] => Mux9.IN10 +A[23] => ShiftLeft0.IN9 +A[23] => ShiftRight0.IN9 +A[23] => ShiftRight1.IN9 +A[23] => ShiftLeft1.IN9 +A[23] => ShiftRight2.IN9 +A[23] => ShiftRight3.IN9 +A[23] => Mux8.IN9 +A[23] => Mux8.IN10 +A[24] => ShiftLeft0.IN8 +A[24] => ShiftRight0.IN8 +A[24] => ShiftRight1.IN8 +A[24] => ShiftLeft1.IN8 +A[24] => ShiftRight2.IN8 +A[24] => ShiftRight3.IN8 +A[24] => Mux7.IN9 +A[24] => Mux7.IN10 +A[25] => ShiftLeft0.IN7 +A[25] => ShiftRight0.IN7 +A[25] => ShiftRight1.IN7 +A[25] => ShiftLeft1.IN7 +A[25] => ShiftRight2.IN7 +A[25] => ShiftRight3.IN7 +A[25] => Mux6.IN9 +A[25] => Mux6.IN10 +A[26] => ShiftLeft0.IN6 +A[26] => ShiftRight0.IN6 +A[26] => ShiftRight1.IN6 +A[26] => ShiftLeft1.IN6 +A[26] => ShiftRight2.IN6 +A[26] => ShiftRight3.IN6 +A[26] => Mux5.IN9 +A[26] => Mux5.IN10 +A[27] => ShiftLeft0.IN5 +A[27] => ShiftRight0.IN5 +A[27] => ShiftRight1.IN5 +A[27] => ShiftLeft1.IN5 +A[27] => ShiftRight2.IN5 +A[27] => ShiftRight3.IN5 +A[27] => Mux4.IN9 +A[27] => Mux4.IN10 +A[28] => ShiftLeft0.IN4 +A[28] => ShiftRight0.IN4 +A[28] => ShiftRight1.IN4 +A[28] => ShiftLeft1.IN4 +A[28] => ShiftRight2.IN4 +A[28] => ShiftRight3.IN4 +A[28] => Mux3.IN9 +A[28] => Mux3.IN10 +A[29] => ShiftLeft0.IN3 +A[29] => ShiftRight0.IN3 +A[29] => ShiftRight1.IN3 +A[29] => ShiftLeft1.IN3 +A[29] => ShiftRight2.IN3 +A[29] => ShiftRight3.IN3 +A[29] => Mux2.IN9 +A[29] => Mux2.IN10 +A[30] => ShiftLeft0.IN2 +A[30] => ShiftRight0.IN2 +A[30] => ShiftRight1.IN2 +A[30] => ShiftLeft1.IN2 +A[30] => ShiftRight2.IN2 +A[30] => ShiftRight3.IN2 +A[30] => Mux1.IN9 +A[30] => Mux1.IN10 +A[31] => ShiftLeft0.IN1 +A[31] => ShiftRight0.IN1 +A[31] => ShiftRight1.IN0 +A[31] => ShiftRight1.IN1 +A[31] => ShiftLeft1.IN1 +A[31] => ShiftRight2.IN1 +A[31] => ShiftRight3.IN0 +A[31] => ShiftRight3.IN1 +A[31] => Mux0.IN9 +A[31] => Mux0.IN10 +B[0] => ShiftLeft1.IN64 +B[0] => ShiftRight2.IN64 +B[0] => ShiftRight3.IN64 +B[1] => ShiftLeft1.IN63 +B[1] => ShiftRight2.IN63 +B[1] => ShiftRight3.IN63 +B[2] => ShiftLeft1.IN62 +B[2] => ShiftRight2.IN62 +B[2] => ShiftRight3.IN62 +B[3] => ShiftLeft1.IN61 +B[3] => ShiftRight2.IN61 +B[3] => ShiftRight3.IN61 +B[4] => ShiftLeft1.IN60 +B[4] => ShiftRight2.IN60 +B[4] => ShiftRight3.IN60 +B[5] => ShiftLeft1.IN59 +B[5] => ShiftRight2.IN59 +B[5] => ShiftRight3.IN59 +B[6] => ShiftLeft1.IN58 +B[6] => ShiftRight2.IN58 +B[6] => ShiftRight3.IN58 +B[7] => ShiftLeft1.IN57 +B[7] => ShiftRight2.IN57 +B[7] => ShiftRight3.IN57 +B[8] => ShiftLeft1.IN56 +B[8] => ShiftRight2.IN56 +B[8] => ShiftRight3.IN56 +B[9] => ShiftLeft1.IN55 +B[9] => ShiftRight2.IN55 +B[9] => ShiftRight3.IN55 +B[10] => ShiftLeft1.IN54 +B[10] => ShiftRight2.IN54 +B[10] => ShiftRight3.IN54 +B[11] => ShiftLeft1.IN53 +B[11] => ShiftRight2.IN53 +B[11] => ShiftRight3.IN53 +B[12] => ShiftLeft1.IN52 +B[12] => ShiftRight2.IN52 +B[12] => ShiftRight3.IN52 +B[13] => ShiftLeft1.IN51 +B[13] => ShiftRight2.IN51 +B[13] => ShiftRight3.IN51 +B[14] => ShiftLeft1.IN50 +B[14] => ShiftRight2.IN50 +B[14] => ShiftRight3.IN50 +B[15] => ShiftLeft1.IN49 +B[15] => ShiftRight2.IN49 +B[15] => ShiftRight3.IN49 +B[16] => ShiftLeft1.IN48 +B[16] => ShiftRight2.IN48 +B[16] => ShiftRight3.IN48 +B[17] => ShiftLeft1.IN47 +B[17] => ShiftRight2.IN47 +B[17] => ShiftRight3.IN47 +B[18] => ShiftLeft1.IN46 +B[18] => ShiftRight2.IN46 +B[18] => ShiftRight3.IN46 +B[19] => ShiftLeft1.IN45 +B[19] => ShiftRight2.IN45 +B[19] => ShiftRight3.IN45 +B[20] => ShiftLeft1.IN44 +B[20] => ShiftRight2.IN44 +B[20] => ShiftRight3.IN44 +B[21] => ShiftLeft1.IN43 +B[21] => ShiftRight2.IN43 +B[21] => ShiftRight3.IN43 +B[22] => ShiftLeft1.IN42 +B[22] => ShiftRight2.IN42 +B[22] => ShiftRight3.IN42 +B[23] => ShiftLeft1.IN41 +B[23] => ShiftRight2.IN41 +B[23] => ShiftRight3.IN41 +B[24] => ShiftLeft1.IN40 +B[24] => ShiftRight2.IN40 +B[24] => ShiftRight3.IN40 +B[25] => ShiftLeft1.IN39 +B[25] => ShiftRight2.IN39 +B[25] => ShiftRight3.IN39 +B[26] => ShiftLeft1.IN38 +B[26] => ShiftRight2.IN38 +B[26] => ShiftRight3.IN38 +B[27] => ShiftLeft1.IN37 +B[27] => ShiftRight2.IN37 +B[27] => ShiftRight3.IN37 +B[28] => ShiftLeft1.IN36 +B[28] => ShiftRight2.IN36 +B[28] => ShiftRight3.IN36 +B[29] => ShiftLeft1.IN35 +B[29] => ShiftRight2.IN35 +B[29] => ShiftRight3.IN35 +B[30] => ShiftLeft1.IN34 +B[30] => ShiftRight2.IN34 +B[30] => ShiftRight3.IN34 +B[31] => ShiftLeft1.IN33 +B[31] => ShiftRight2.IN33 +B[31] => ShiftRight3.IN33 +C[0] => ShiftLeft0.IN37 +C[0] => ShiftRight0.IN37 +C[0] => ShiftRight1.IN37 +C[1] => ShiftLeft0.IN36 +C[1] => ShiftRight0.IN36 +C[1] => ShiftRight1.IN36 +C[2] => ShiftLeft0.IN35 +C[2] => ShiftRight0.IN35 +C[2] => ShiftRight1.IN35 +C[3] => ShiftLeft0.IN34 +C[3] => ShiftRight0.IN34 +C[3] => ShiftRight1.IN34 +C[4] => ShiftLeft0.IN33 +C[4] => ShiftRight0.IN33 +C[4] => ShiftRight1.IN33 +OUT_1[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/Quartus/A2/db/assignment2.hif b/Quartus/A2/db/assignment2.hif new file mode 100644 index 0000000..76e3eea Binary files /dev/null and b/Quartus/A2/db/assignment2.hif differ diff --git a/Quartus/A2/db/assignment2.lpc.html b/Quartus/A2/db/assignment2.lpc.html new file mode 100644 index 0000000..ebcf221 --- /dev/null +++ b/Quartus/A2/db/assignment2.lpc.html @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
SHIFTER72270273227272700000
ALU|logic_unit660003200000000
ALU|adder_unit650003400000000
ALU680003400000000
REGS490003200000000
INSTRUCTION_MODULE_CLASSIFIER3000400000000
INSTRUCTION_CLASSIFIER6000700000000
ROM100003200000000
PC34440443244444400000
diff --git a/Quartus/A2/db/assignment2.lpc.rdb b/Quartus/A2/db/assignment2.lpc.rdb new file mode 100644 index 0000000..bf873f2 Binary files /dev/null and b/Quartus/A2/db/assignment2.lpc.rdb differ diff --git a/Quartus/A2/db/assignment2.lpc.txt b/Quartus/A2/db/assignment2.lpc.txt new file mode 100644 index 0000000..0f52d19 --- /dev/null +++ b/Quartus/A2/db/assignment2.lpc.txt @@ -0,0 +1,15 @@ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; SHIFTER ; 72 ; 27 ; 0 ; 27 ; 32 ; 27 ; 27 ; 27 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU|logic_unit ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU|adder_unit ; 65 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ALU ; 68 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; REGS ; 49 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; INSTRUCTION_MODULE_CLASSIFIER ; 3 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; INSTRUCTION_CLASSIFIER ; 6 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; ROM ; 10 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; PC ; 34 ; 44 ; 0 ; 44 ; 32 ; 44 ; 44 ; 44 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A2/db/assignment2.map.ammdb b/Quartus/A2/db/assignment2.map.ammdb new file mode 100644 index 0000000..25b1b34 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.ammdb differ diff --git a/Quartus/A2/db/assignment2.map.bpm b/Quartus/A2/db/assignment2.map.bpm new file mode 100644 index 0000000..c3dc931 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.bpm differ diff --git a/Quartus/A2/db/assignment2.map.cdb b/Quartus/A2/db/assignment2.map.cdb new file mode 100644 index 0000000..d04dd37 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.cdb differ diff --git a/Quartus/A2/db/assignment2.map.hdb b/Quartus/A2/db/assignment2.map.hdb new file mode 100644 index 0000000..63220a8 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.hdb differ diff --git a/Quartus/A2/db/assignment2.map.kpt b/Quartus/A2/db/assignment2.map.kpt new file mode 100644 index 0000000..59be3a1 Binary files /dev/null and b/Quartus/A2/db/assignment2.map.kpt differ diff --git a/Quartus/A2/db/assignment2.map.logdb b/Quartus/A2/db/assignment2.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A2/db/assignment2.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A2/db/assignment2.map.qmsg b/Quartus/A2/db/assignment2.map.qmsg index b754c22..45d32cf 100644 --- a/Quartus/A2/db/assignment2.map.qmsg +++ b/Quartus/A2/db/assignment2.map.qmsg @@ -1,15 +1,32 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854502822 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:21:42 2026 " "Processing started: Tue Oct 13 12:21:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512634 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:21:52 2026 " "Processing ended: Tue Oct 13 12:21:52 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512678 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858197350 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:23:17 2026 " "Processing started: Tue Oct 13 13:23:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 11 11 " "Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "11 assignment2 " "Found entity 11: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858206828 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791858206971 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(48) " "Verilog HDL or VHDL warning at assignment2.sv(48): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 48 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791858206973 "|assignment2"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206990 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206997 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791858207006 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207036 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207039 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207041 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207048 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207054 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207060 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207066 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207119 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207120 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207121 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207122 ""} +{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[17\] " "Net \"rs\[17\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[17\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[16\] " "Net \"rs\[16\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[16\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[15\] " "Net \"rs\[15\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[15\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[14\] " "Net \"rs\[14\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[14\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[13\] " "Net \"rs\[13\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[13\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[12\] " "Net \"rs\[12\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[12\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[11\] " "Net \"rs\[11\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[11\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[10\] " "Net \"rs\[10\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[10\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[9\] " "Net \"rs\[9\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[9\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[8\] " "Net \"rs\[8\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[8\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[7\] " "Net \"rs\[7\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[7\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[6\] " "Net \"rs\[6\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[6\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[5\] " "Net \"rs\[5\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[5\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[4\] " "Net \"rs\[4\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[4\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[3\] " "Net \"rs\[3\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[3\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[2\] " "Net \"rs\[2\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[2\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[1\] " "Net \"rs\[1\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[1\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[0\] " "Net \"rs\[0\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[0\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1791858207124 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791858207654 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791858207721 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791858207864 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207864 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791858207996 "|assignment2|clk[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "1 " "Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791858207996 ""} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Implemented 0 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791858207996 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 174 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:23:28 2026 " "Processing ended: Tue Oct 13 13:23:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858208006 ""} diff --git a/Quartus/A2/db/assignment2.map.rdb b/Quartus/A2/db/assignment2.map.rdb index 676973d..aae289d 100644 Binary files a/Quartus/A2/db/assignment2.map.rdb and b/Quartus/A2/db/assignment2.map.rdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.cdb b/Quartus/A2/db/assignment2.map_bb.cdb new file mode 100644 index 0000000..5e91b80 Binary files /dev/null and b/Quartus/A2/db/assignment2.map_bb.cdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.hdb b/Quartus/A2/db/assignment2.map_bb.hdb index 24f33df..df5ce4e 100644 Binary files a/Quartus/A2/db/assignment2.map_bb.hdb and b/Quartus/A2/db/assignment2.map_bb.hdb differ diff --git a/Quartus/A2/db/assignment2.map_bb.logdb b/Quartus/A2/db/assignment2.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A2/db/assignment2.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A2/db/assignment2.pre_map.hdb b/Quartus/A2/db/assignment2.pre_map.hdb new file mode 100644 index 0000000..b460eae Binary files /dev/null and b/Quartus/A2/db/assignment2.pre_map.hdb differ diff --git a/Quartus/A2/db/assignment2.quiproj.2400.rdr.flock b/Quartus/A2/db/assignment2.quiproj.5775.rdr.flock similarity index 100% rename from Quartus/A2/db/assignment2.quiproj.2400.rdr.flock rename to Quartus/A2/db/assignment2.quiproj.5775.rdr.flock diff --git a/Quartus/A2/db/assignment2.ram0_register_file_16097a2d.hdl.mif b/Quartus/A2/db/assignment2.ram0_register_file_16097a2d.hdl.mif new file mode 100644 index 0000000..6eefa95 --- /dev/null +++ b/Quartus/A2/db/assignment2.ram0_register_file_16097a2d.hdl.mif @@ -0,0 +1,46 @@ +-- begin_signature +-- register_file(width +-- 5 +-- nregs +-- 5) +-- end_signature +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=UNS; +DATA_RADIX=BIN; + +CONTENT BEGIN + 31 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 30 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 29 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 28 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 27 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 26 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 25 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 24 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 23 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 22 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 21 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 20 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 19 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 18 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 17 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 16 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 15 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 14 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 13 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 12 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 11 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 10 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; + 9 : XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX; 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+ 5 : 00000001001010110110000000100010; + 4 : 00000001001010100101100000100001; + 3 : 10001101000010100000000000000000; + 2 : 10101101000010010000000000000000; + 1 : 00100101000010010000000000000111; + 0 : 00000001000010000100000000100011; +END; diff --git a/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..e3cdaae Binary files /dev/null and b/Quartus/A2/db/assignment2.root_partition.map.reg_db.cdb differ diff --git a/Quartus/A2/db/assignment2.routing.rdb b/Quartus/A2/db/assignment2.routing.rdb new file mode 100644 index 0000000..faae01f Binary files /dev/null and b/Quartus/A2/db/assignment2.routing.rdb differ diff --git a/Quartus/A2/db/assignment2.rtlv.hdb b/Quartus/A2/db/assignment2.rtlv.hdb new file mode 100644 index 0000000..cee2f72 Binary files /dev/null and b/Quartus/A2/db/assignment2.rtlv.hdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg.cdb b/Quartus/A2/db/assignment2.rtlv_sg.cdb new file mode 100644 index 0000000..34dfbc5 Binary files /dev/null and b/Quartus/A2/db/assignment2.rtlv_sg.cdb differ diff --git a/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb new file mode 100644 index 0000000..5640608 Binary files /dev/null and b/Quartus/A2/db/assignment2.rtlv_sg_swap.cdb differ diff --git a/Quartus/A2/db/assignment2.sld_design_entry_dsc.sci b/Quartus/A2/db/assignment2.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A2/db/assignment2.sld_design_entry_dsc.sci differ diff --git a/Quartus/A2/db/assignment2.smart_action.txt b/Quartus/A2/db/assignment2.smart_action.txt index 11b531f..c8e8a13 100644 --- a/Quartus/A2/db/assignment2.smart_action.txt +++ b/Quartus/A2/db/assignment2.smart_action.txt @@ -1 +1 @@ -SOURCE +DONE diff --git a/Quartus/A2/db/assignment2.sta.qmsg b/Quartus/A2/db/assignment2.sta.qmsg new file mode 100644 index 0000000..6da6962 --- /dev/null +++ b/Quartus/A2/db/assignment2.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858244479 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858244480 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:24:04 2026 " "Processing started: Tue Oct 13 13:24:04 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858244480 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858244480 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta assignment2 -c assignment2 " "Command: quartus_sta assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858244480 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1791858244539 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1791858245026 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1791858245026 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245104 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245104 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "assignment2.sdc " "Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1791858245714 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858245714 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1791858245715 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858245715 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1791858245716 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1791858245721 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791858245721 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245723 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245734 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245735 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245736 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245736 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858245737 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791858245739 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791858245784 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791858246730 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858246816 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858246817 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246818 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246820 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246821 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246822 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246823 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858246823 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1791858246825 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1791858247086 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1791858247632 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858247668 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858247668 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858247669 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858247669 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247670 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247671 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247672 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247673 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247673 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1791858247675 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1791858247823 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1791858247823 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247824 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247825 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247826 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247827 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1791858247827 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791858248367 ""} +{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1791858248367 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "718 " "Peak virtual memory: 718 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:24:08 2026 " "Processing ended: Tue Oct 13 13:24:08 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858248389 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1791858248389 ""} diff --git a/Quartus/A2/db/assignment2.sta.rdb b/Quartus/A2/db/assignment2.sta.rdb new file mode 100644 index 0000000..5ecbfed Binary files /dev/null and b/Quartus/A2/db/assignment2.sta.rdb differ diff --git a/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb new file mode 100644 index 0000000..f3ae18d Binary files /dev/null and b/Quartus/A2/db/assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A2/db/assignment2.tis_db_list.ddb b/Quartus/A2/db/assignment2.tis_db_list.ddb index 781db1e..06ddd4e 100644 Binary files a/Quartus/A2/db/assignment2.tis_db_list.ddb and b/Quartus/A2/db/assignment2.tis_db_list.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb new file mode 100644 index 0000000..aba38c0 Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb new file mode 100644 index 0000000..d8030c2 Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb new file mode 100644 index 0000000..479718e Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb new file mode 100644 index 0000000..7d048ee Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb new file mode 100644 index 0000000..2d98789 Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb new file mode 100644 index 0000000..7c127f4 Binary files /dev/null and b/Quartus/A2/db/assignment2.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A2/db/assignment2.tmw_info b/Quartus/A2/db/assignment2.tmw_info new file mode 100644 index 0000000..be32990 --- /dev/null +++ b/Quartus/A2/db/assignment2.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:00:55 +start_analysis_synthesis:s:00:00:12-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:28-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation +start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A2/db/assignment2.vpr.ammdb b/Quartus/A2/db/assignment2.vpr.ammdb new file mode 100644 index 0000000..5a53bbf Binary files /dev/null and b/Quartus/A2/db/assignment2.vpr.ammdb differ diff --git a/Quartus/A2/db/assignment2_partition_pins.json b/Quartus/A2/db/assignment2_partition_pins.json new file mode 100644 index 0000000..aeab6ee --- /dev/null +++ b/Quartus/A2/db/assignment2_partition_pins.json @@ -0,0 +1,8 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [] + } + ] +} \ No newline at end of file diff --git a/Quartus/A2/db/prev_cmp_assignment2.qmsg b/Quartus/A2/db/prev_cmp_assignment2.qmsg index ffbf67b..cd49738 100644 --- a/Quartus/A2/db/prev_cmp_assignment2.qmsg +++ b/Quartus/A2/db/prev_cmp_assignment2.qmsg @@ -1,22 +1,15 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854431570 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854431571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:20:31 2026 " "Processing started: Tue Oct 13 12:20:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854431571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854431571 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854431571 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854431890 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854431890 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"end\"; \"end\" without \"begin\" instruction_counter.sv(18) " "Verilog HDL syntax error at instruction_counter.sv(18) near text: \"end\"; \"end\" without \"begin\" . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 18 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440693 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_counter instruction_counter.sv(4) " "Ignored design unit \"instruction_counter\" at instruction_counter.sv(4) due to previous errors" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440694 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_classifier instruction_classifier.sv(3) " "Ignored design unit \"instruction_classifier\" at instruction_classifier.sv(3) due to previous errors" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440694 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "asu asu.sv(4) " "Ignored design unit \"asu\" at asu.sv(4) due to previous errors" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lu lu.sv(3) " "Ignored design unit \"lu\" at lu.sv(3) due to previous errors" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(9) " "Ignored design unit \"alu\" at alu.sv(9) due to previous errors" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440695 ""} -{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854440696 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854440697 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 14 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 14 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:20:40 2026 " "Processing ended: Tue Oct 13 12:20:40 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854440753 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854440753 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 16 s 1 " "Quartus Prime Full Compilation was unsuccessful. 16 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854441416 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858134196 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:22:14 2026 " "Processing started: Tue Oct 13 13:22:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858134196 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134196 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858134197 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858134513 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting a direction instruction_module_classifier.sv(10) " "Verilog HDL syntax error at instruction_module_classifier.sv(10) near text: \")\"; expecting a direction. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 10 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791858143825 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "instruction_module_classifier instruction_module_classifier.sv(4) " "Ignored design unit \"instruction_module_classifier\" at instruction_module_classifier.sv(4) due to previous errors" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "asu asu.sv(4) " "Ignored design unit \"asu\" at asu.sv(4) due to previous errors" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "lu lu.sv(3) " "Ignored design unit \"lu\" at lu.sv(3) due to previous errors" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143826 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "alu alu.sv(9) " "Ignored design unit \"alu\" at alu.sv(9) due to previous errors" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "shifter shifter.sv(3) " "Ignored design unit \"shifter\" at shifter.sv(3) due to previous errors" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791858143827 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143828 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 7 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 7 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 13:22:23 2026 " "Processing ended: Tue Oct 13 13:22:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858143869 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858143869 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 9 s 1 " "Quartus Prime Full Compilation was unsuccessful. 9 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858144586 ""} diff --git a/Quartus/A2/incremental_db/README b/Quartus/A2/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/Quartus/A2/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.db_info b/Quartus/A2/incremental_db/compiled_partitions/assignment2.db_info new file mode 100644 index 0000000..bf742ca --- /dev/null +++ b/Quartus/A2/incremental_db/compiled_partitions/assignment2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Tue Oct 13 13:23:27 2026 diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb new file mode 100644 index 0000000..01edc23 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.ammdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb new file mode 100644 index 0000000..ada6728 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.dfp b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.dfp differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb new file mode 100644 index 0000000..e4f1a6b Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb new file mode 100644 index 0000000..c61efd4 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.sig b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb new file mode 100644 index 0000000..4cd9f99 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.logdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb new file mode 100644 index 0000000..027d974 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.cmp.rcfdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb new file mode 100644 index 0000000..dadfbd7 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi new file mode 100644 index 0000000..54d9a73 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.dpi differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..6cd087e Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hb_info b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hb_info differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..8a1fee0 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.sig b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb new file mode 100644 index 0000000..4f4e33c Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt new file mode 100644 index 0000000..cbdd95c Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.root_partition.map.kpt differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb new file mode 100644 index 0000000..b156727 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrp.hdb differ diff --git a/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrs.cdb b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrs.cdb new file mode 100644 index 0000000..7793495 Binary files /dev/null and b/Quartus/A2/incremental_db/compiled_partitions/assignment2.rrs.cdb differ diff --git a/Quartus/A2/output_files/assignment2.asm.rpt b/Quartus/A2/output_files/assignment2.asm.rpt new file mode 100644 index 0000000..6da6ab8 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for assignment2 +Tue Oct 13 13:24:02 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: assignment2.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Oct 13 13:24:02 2026 ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------------------------------------------+ +; File Name ; ++----------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/output_files/assignment2.sof ; ++----------------------------------------------------------------------------------+ + + ++-------------------------------------------+ +; Assembler Device Options: assignment2.sof ; ++----------------+--------------------------+ +; Option ; Setting ; ++----------------+--------------------------+ +; JTAG usercode ; 0x0077D665 ; +; Checksum ; 0x0077D665 ; ++----------------+--------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Oct 13 13:23:57 2026 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 521 megabytes + Info: Processing ended: Tue Oct 13 13:24:02 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/Quartus/A2/output_files/assignment2.done b/Quartus/A2/output_files/assignment2.done new file mode 100644 index 0000000..cab42d9 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.done @@ -0,0 +1 @@ +Tue Oct 13 13:24:11 2026 diff --git a/Quartus/A2/output_files/assignment2.eda.rpt b/Quartus/A2/output_files/assignment2.eda.rpt new file mode 100644 index 0000000..725337e --- /dev/null +++ b/Quartus/A2/output_files/assignment2.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for assignment2 +Tue Oct 13 13:24:10 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Oct 13 13:24:10 2026 ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Tool Name ; Questa Altera FPGA (SystemVerilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/assignment2.svo ; ++---------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Oct 13 13:24:09 2026 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 666 megabytes + Info: Processing ended: Tue Oct 13 13:24:10 2026 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Quartus/A2/output_files/assignment2.fit.rpt b/Quartus/A2/output_files/assignment2.fit.rpt new file mode 100644 index 0000000..552506b --- /dev/null +++ b/Quartus/A2/output_files/assignment2.fit.rpt @@ -0,0 +1,1294 @@ +Fitter report for assignment2 +Tue Oct 13 13:23:55 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. I/O Assignment Warnings + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Routing Usage Summary + 19. I/O Rules Summary + 20. I/O Rules Details + 21. I/O Rules Matrix + 22. Fitter Device Options + 23. Operating Settings and Conditions + 24. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Tue Oct 13 13:23:55 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 1 / 364 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total RAM Blocks ; 0 / 446 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; +; -- Achieved ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; 0.00 % ( 0 / 3 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 3 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/output_files/assignment2.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 1 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29,080 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 0 ; ; +; [b] ALMs used for LUT logic ; 1 ; ; +; [c] ALMs used for registers ; 0 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 2,908 ; < 1 % ; +; -- Logic LABs ; 1 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 1 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 0 ; ; +; -- 5 input functions ; 0 ; ; +; -- 4 input functions ; 0 ; ; +; -- <=3 input functions ; 1 ; ; +; Combinational ALUT usage for route-throughs ; 0 ; ; +; ; ; ; +; Dedicated logic registers ; 0 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58,160 ; 0 % ; +; -- Secondary logic registers ; 0 / 58,160 ; 0 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; ; +; -- Routing optimization registers ; 0 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 1 / 364 ; < 1 % ; +; -- Clock pins ; 1 / 14 ; 7 % ; +; -- Dedicated input pins ; 0 / 23 ; 0 % ; +; ; ; ; +; M10K blocks ; 0 / 446 ; 0 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 0 / 4,567,040 ; 0 % ; +; Total block memory implementation bits ; 0 / 4,567,040 ; 0 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 150 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 0 ; ; +; -- Global clocks ; 0 / 16 ; 0 % ; +; -- Quadrant clocks ; 0 / 88 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ; +; SERDES Transmitters ; 0 / 88 ; 0 % ; +; SERDES Receivers ; 0 / 88 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Hard IPs ; 0 / 2 ; 0 % ; +; Standard RX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA RX Deserializers ; 0 / 6 ; 0 % ; +; Standard TX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA TX Serializers ; 0 / 6 ; 0 % ; +; Channel PLLs ; 0 / 6 ; 0 % ; +; Impedance control blocks ; 0 / 3 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; +; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; +; Maximum fan-out ; 1 ; ; +; Highest non-global fan-out ; 1 ; ; +; Total fan-out ; 1 ; ; +; Average fan-out ; 0.33 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+---------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 1 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; +; [b] ALMs used for LUT logic ; 1 ; 0 ; +; [c] ALMs used for registers ; 0 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; +; -- Logic LABs ; 1 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 1 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 0 ; 0 ; +; -- 5 input functions ; 0 ; 0 ; +; -- 4 input functions ; 0 ; 0 ; +; -- <=3 input functions ; 1 ; 0 ; +; Combinational ALUT usage for route-throughs ; 0 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; 0 ; +; -- Routing optimization registers ; 0 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 1 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 0 ; 0 ; +; Total block memory implementation bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 1 ; 0 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 1 ; 0 ; +; -- Output Ports ; 0 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+---------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; clk[0] ; M21 ; 6A ; 68 ; 32 ; 60 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; ++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++--------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+----------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+----------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 1 / 48 ( 2 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+----------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; 396 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; A3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A5 ; 344 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 392 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A11 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 332 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 330 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A21 ; 274 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; 270 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A23 ; 268 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 269 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA14 ; 87 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA26 ; 201 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; 21 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB2 ; 20 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB24 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB25 ; 189 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 199 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; 18 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC4 ; 19 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC23 ; 168 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC25 ; 193 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD1 ; 25 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD2 ; 24 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF11 ; 101 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B5 ; 394 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; B6 ; 346 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 350 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B9 ; 314 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 334 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 328 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B14 ; 302 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 304 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; ; 7A ; VREFB7AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B17 ; 298 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 282 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C7 ; 358 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; C9 ; 312 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 318 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; 338 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 336 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 307 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 306 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 280 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 266 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 264 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; C25 ; 253 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C26 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 395 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; D6 ; 352 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 356 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 372 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 340 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 342 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 341 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D15 ; 309 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 293 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 291 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D19 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D20 ; 277 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 275 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D23 ; 262 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D25 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D26 ; 227 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 354 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 315 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 299 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 285 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; 283 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E21 ; 259 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E23 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E24 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E25 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E26 ; 229 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F16 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F18 ; 301 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F21 ; 260 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 261 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F23 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F24 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F25 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F26 ; 219 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 329 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 331 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 279 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 281 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G19 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G22 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G24 ; 237 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G25 ; 223 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 221 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H5 ; 400 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 263 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H17 ; 273 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 271 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H23 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H24 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 225 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 399 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 287 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J16 ; 265 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J20 ; 254 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 256 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J25 ; 215 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 217 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K5 ; 397 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 373 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 363 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 361 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 367 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 305 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K21 ; 248 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K23 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K25 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K26 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L6 ; 393 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L7 ; 371 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 359 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 353 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; 337 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 303 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; 246 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L23 ; 238 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 240 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L26 ; ; 6A ; VREFB6AN0 ; power ; ; ; -- ; ; -- ; -- ; +; M1 ; 5 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M2 ; 4 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M7 ; 391 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; 351 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 345 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 335 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 321 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M21 ; 216 ; 6A ; clk[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M25 ; 226 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 228 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; 1 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; N8 ; 36 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; N9 ; 343 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; 76 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; 319 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N20 ; 214 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N22 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 222 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 218 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 210 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P1 ; 6 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P2 ; 7 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 200 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 206 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 208 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; 192 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; P26 ; 212 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R20 ; 198 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R22 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R23 ; 190 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R24 ; 194 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; 196 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R26 ; 204 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 9 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T2 ; 8 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T4 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T19 ; 179 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 182 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 184 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T23 ; 186 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 188 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T26 ; 202 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; 108 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U25 ; 211 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 213 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 13 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V2 ; 12 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; 26 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; 10 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W4 ; 11 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W25 ; 207 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 209 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; 203 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y26 ; 205 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; clk[0] ; Incomplete set of assignments ; +; clk[0] ; Missing location assignment ; ++----------+-------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +; |assignment2 ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ +; clk[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++--------+----------+----+------+------+----+----+-------+--------+------------------------+--------------------------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; clk[0] ; ; ; ++---------------------+-------------------+---------+ + + ++----------------------------------------------------+ +; Routing Usage Summary ; ++------------------------------+---------------------+ +; Routing Resource Type ; Usage ; ++------------------------------+---------------------+ +; Block interconnects ; 0 / 217,884 ( 0 % ) ; +; C12 interconnects ; 0 / 10,080 ( 0 % ) ; +; C2 interconnects ; 0 / 87,208 ( 0 % ) ; +; C4 interconnects ; 0 / 41,360 ( 0 % ) ; +; DQS bus muxes ; 0 / 21 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; +; Direct links ; 0 / 217,884 ( 0 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; +; Local interconnects ; 0 / 58,160 ( 0 % ) ; +; Quadrant clocks ; 0 / 88 ( 0 % ) ; +; R14 interconnects ; 0 / 9,228 ( 0 % ) ; +; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ; +; R3 interconnects ; 0 / 94,896 ( 0 % ) ; +; R6 interconnects ; 0 / 194,640 ( 0 % ) ; +; Spine clocks ; 0 / 180 ( 0 % ) ; +; Wire stub REs ; 0 / 11,606 ( 0 % ) ; ++------------------------------+---------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 3 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 25 ; ++----------------------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Outputs with single-ended I/O Standard or Differential I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+-------------------------------------------------------------------------------------------+------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 1 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; clk[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CGXFC5C6F27C7 for design "assignment2" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 1 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Info (184020): Starting Fitter periphery placement operations +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 +Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02 +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1336 megabytes + Info: Processing ended: Tue Oct 13 13:23:55 2026 + Info: Elapsed time: 00:00:26 + Info: Total CPU time (on all processors): 00:00:37 + + diff --git a/Quartus/A2/output_files/assignment2.fit.summary b/Quartus/A2/output_files/assignment2.fit.summary new file mode 100644 index 0000000..a8c3248 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Oct 13 13:23:55 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : assignment2 +Top-level Entity Name : assignment2 +Family : Cyclone V +Device : 5CGXFC5C6F27C7 +Timing Models : Final +Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % ) +Total registers : 0 +Total pins : 1 / 364 ( < 1 % ) +Total virtual pins : 0 +Total block memory bits : 0 / 4,567,040 ( 0 % ) +Total RAM Blocks : 0 / 446 ( 0 % ) +Total DSP Blocks : 0 / 150 ( 0 % ) +Total HSSI RX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) +Total HSSI TX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) +Total PLLs : 0 / 12 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) diff --git a/Quartus/A2/output_files/assignment2.flow.rpt b/Quartus/A2/output_files/assignment2.flow.rpt index f8a77d2..502e15c 100644 --- a/Quartus/A2/output_files/assignment2.flow.rpt +++ b/Quartus/A2/output_files/assignment2.flow.rpt @@ -1,5 +1,5 @@ Flow report for assignment2 -Tue Oct 13 12:21:52 2026 +Tue Oct 13 13:24:10 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,24 +38,29 @@ on the Quartus Prime software download page. -+-------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------------+-------------------------------------------------+ -; Flow Status ; Flow Failed - Tue Oct 13 12:21:52 2026 ; -; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; -; Revision Name ; assignment2 ; -; Top-level Entity Name ; assignment2 ; -; Family ; Cyclone V ; -; Device ; 5CGXFC5C6F27C7 ; -; Timing Models ; Final ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -; Total DLLs ; N/A until Partition Merge ; -+-----------------------------+-------------------------------------------------+ ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Tue Oct 13 13:24:10 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 1 / 364 ( < 1 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ +-----------------------------------------+ @@ -63,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 10/13/2026 12:21:43 ; +; Start date & time ; 10/13/2026 13:23:17 ; ; Main task ; Compilation ; ; Revision Name ; assignment2 ; +-------------------+---------------------+ @@ -74,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 268883478169649.179185450204071 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 152226744081900.179185819706755 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -88,6 +93,7 @@ on the Quartus Prime software download page. ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; VERILOG_MACRO ; QUARTUS_SYNTH ; -- ; -- ; -- ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ @@ -96,8 +102,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 400 MB ; 00:00:25 ; -; Total ; 00:00:10 ; -- ; -- ; 00:00:25 ; +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 410 MB ; 00:00:24 ; +; Fitter ; 00:00:26 ; 1.0 ; 1336 MB ; 00:00:36 ; +; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:04 ; 1.0 ; 718 MB ; 00:00:04 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 666 MB ; 00:00:01 ; +; Total ; 00:00:46 ; -- ; -- ; 00:01:10 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -107,6 +117,10 @@ on the Quartus Prime software download page. ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+---------------------+------------+------------+----------------+ ; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +----------------------+---------------------+------------+------------+----------------+ @@ -114,6 +128,10 @@ on the Quartus Prime software download page. ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 +quartus_fit --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +quartus_asm --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 +quartus_sta assignment2 -c assignment2 +quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2 diff --git a/Quartus/A2/output_files/assignment2.jdi b/Quartus/A2/output_files/assignment2.jdi new file mode 100644 index 0000000..a83eaac --- /dev/null +++ b/Quartus/A2/output_files/assignment2.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Quartus/A2/output_files/assignment2.map.rpt b/Quartus/A2/output_files/assignment2.map.rpt index 180c01b..38d26ee 100644 --- a/Quartus/A2/output_files/assignment2.map.rpt +++ b/Quartus/A2/output_files/assignment2.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for assignment2 -Tue Oct 13 12:21:52 2026 +Tue Oct 13 13:23:28 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -10,7 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation - 5. Analysis & Synthesis Messages + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Parameter Settings for User Entity Instance: Top-level Entity: |assignment2 + 11. Parameter Settings for User Entity Instance: instruction_counter:PC + 12. Parameter Settings for User Entity Instance: rom:ROM + 13. Parameter Settings for User Entity Instance: register_file:REGS + 14. Parameter Settings for User Entity Instance: alu:ALU + 15. Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit + 16. Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit + 17. Parameter Settings for User Entity Instance: shifter:SHIFTER + 18. Port Connectivity Checks: "shifter:SHIFTER" + 19. Port Connectivity Checks: "alu:ALU" + 20. Port Connectivity Checks: "register_file:REGS" + 21. Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" + 22. Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER" + 23. Port Connectivity Checks: "instruction_counter:PC" + 24. Post-Synthesis Netlist Statistics for Top Partition + 25. Elapsed Time Per Partition + 26. Analysis & Synthesis Messages @@ -34,22 +55,27 @@ on the Quartus Prime software download page. -+-------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Failed - Tue Oct 13 12:21:52 2026 ; -; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; -; Revision Name ; assignment2 ; -; Top-level Entity Name ; assignment2 ; -; Family ; Cyclone V ; -; Logic utilization (in ALMs) ; N/A until Partition Merge ; -; Total registers ; N/A until Partition Merge ; -; Total pins ; N/A until Partition Merge ; -; Total virtual pins ; N/A until Partition Merge ; -; Total block memory bits ; N/A until Partition Merge ; -; Total PLLs ; N/A until Partition Merge ; -; Total DLLs ; N/A until Partition Merge ; -+-----------------------------+-------------------------------------------------+ ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Oct 13 13:23:27 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; assignment2 ; +; Top-level Entity Name ; assignment2 ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 0 ; +; Total pins ; 1 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+-------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ @@ -155,29 +181,474 @@ on the Quartus Prime software download page. +----------------------------+-------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+ +; ../../modules/assignment2.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv ; ; +; ../../modules/rom.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv ; ; +; ../../modules/ram.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv ; ; +; ../../modules/register_file.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv ; ; +; ../../modules/instruction_counter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv ; ; +; ../../modules/instruction_classifier.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv ; ; +; ../../modules/instruction_module_classifier.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv ; ; +; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ; +; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ; +; ../../modules/alu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ; +; ../../modules/shifter.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ; +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; yes ; Auto-Found File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt ; ; ++----------------------------------------------------------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+--------+ +; Resource ; Usage ; ++---------------------------------------------+--------+ +; Estimate of Logic utilization (ALMs needed) ; 0 ; +; ; ; +; Combinational ALUT usage for logic ; 0 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 0 ; +; -- 5 input functions ; 0 ; +; -- 4 input functions ; 0 ; +; -- <=3 input functions ; 0 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 1 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; clk[0] ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 1 ; +; Average fan-out ; 0.50 ; ++---------------------------------------------+--------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; |assignment2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; |assignment2 ; assignment2 ; work ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------+--------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------+--------------------+ +; instruction_counter:PC|pc[0..31] ; Lost fanout ; +; Total Number of Removed Registers = 32 ; ; ++----------------------------------------+--------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |assignment2 ; ++----------------+-------+----------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------+ +; width ; 5 ; Signed Integer ; +; ramsz ; 9 ; Signed Integer ; +; romsz ; 10 ; Signed Integer ; ++----------------+-------+----------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: instruction_counter:PC ; ++----------------+-------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------+ +; Parameter Settings for User Entity Instance: rom:ROM ; ++----------------+-------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------+ +; m ; 10 ; Signed Integer ; +; p ; 32 ; Signed Integer ; ++----------------+-------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: register_file:REGS ; ++----------------+-------+----------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------+ +; width ; 5 ; Signed Integer ; +; nregs ; 5 ; Signed Integer ; ++----------------+-------+----------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU ; ++----------------+-------+-----------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+-----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU|asu:adder_unit ; ++----------------+-------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: alu:ALU|lu:logic_unit ; ++----------------+-------+-------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+-------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: shifter:SHIFTER ; ++----------------+-------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------+ +; width ; 5 ; Signed Integer ; ++----------------+-------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "shifter:SHIFTER" ; ++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; B ; Input ; Warning ; Input port expression (5 bits) is smaller than the input port (32 bits) it drives. Extra input bit(s) "B[31..5]" will be connected to GND. ; +; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "alu:ALU" ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ +; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; flags ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "register_file:REGS" ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; RD2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ +; en_shifter ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; en_jmp ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; en_mul ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; en_alu ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "instruction_classifier:INSTRUCTION_CLASSIFIER" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; R ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; B1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; J ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; B2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; I ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; F ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; M ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "instruction_counter:PC" ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; W ; Input ; Warning ; Input port expression (10 bits) is smaller than the input port (32 bits) it drives. Extra input bit(s) "W[31..10]" will be connected to GND. ; +; addr ; Output ; Warning ; Output or bidir port (32 bits) is wider than the port expression (10 bits) it drives; bit(s) "addr[31..10]" have no fanouts ; ++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-------------------+---------------------------------+ +; Type ; Count ; ++-------------------+---------------------------------+ +; boundary_port ; 1 ; +; ; ; +; Max LUT depth ; 0.00 ; +; Average LUT depth ; 0.00 ; ++-------------------+---------------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Tue Oct 13 12:21:42 2026 + Info: Processing started: Tue Oct 13 13:23:17 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected -Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 -Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_we" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 -Error (10149): Verilog HDL Declaration error at assignment2.sv(26): identifier "pc_addr" is already declared in the present scope File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 -Error (10170): Verilog HDL syntax error at assignment2.sv(26) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 -Error (10170): Verilog HDL syntax error at assignment2.sv(27) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 27 -Error (10170): Verilog HDL syntax error at assignment2.sv(28) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 28 -Error (10170): Verilog HDL syntax error at assignment2.sv(29) near text: "#"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 29 -Error (10112): Ignored design unit "assignment2" at assignment2.sv(20) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 20 -Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv -Error: Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning - Error: Peak virtual memory: 400 megabytes - Error: Processing ended: Tue Oct 13 12:21:52 2026 - Error: Elapsed time: 00:00:10 - Error: Total CPU time (on all processors): 00:00:25 +Info (12021): Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv + Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4 + Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4 + Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4 + Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4 + Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3 + Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4 + Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 + Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3 + Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 + Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3 + Info (12023): Found entity 11: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Info (12127): Elaborating entity "assignment2" for the top level hierarchy +Warning (10036): Verilog HDL or VHDL warning at assignment2.sv(48): object "rd" assigned a value but never read File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 48 +Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 51 +Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 52 +Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16 +Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 +Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 +Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9 +Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 53 +Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 54 +Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 60 +Info (12128): Elaborating entity "alu" for hierarchy "alu:ALU" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 63 +Info (12128): Elaborating entity "asu" for hierarchy "alu:ALU|asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 18 +Info (12128): Elaborating entity "lu" for hierarchy "alu:ALU|lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 21 +Info (12128): Elaborating entity "shifter" for hierarchy "shifter:SHIFTER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 66 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 +Warning (12011): Net is missing source, defaulting to GND + Warning (12110): Net "rs[31]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[30]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[29]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[28]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[27]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[26]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[25]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[24]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[23]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[22]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[21]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[20]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[19]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[18]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[17]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[16]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[15]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[14]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[13]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[12]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[11]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[10]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[9]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[8]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[7]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[6]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[5]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[4]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[3]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[2]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[1]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 + Warning (12110): Net "rs[0]" is missing source, defaulting to GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 46 +Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Info (17049): 32 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 1 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "clk[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 26 +Info (21057): Implemented 1 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 1 input pins + Info (21059): Implemented 0 output pins +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings + Info: Peak virtual memory: 423 megabytes + Info: Processing ended: Tue Oct 13 13:23:28 2026 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:25 diff --git a/Quartus/A2/output_files/assignment2.map.summary b/Quartus/A2/output_files/assignment2.map.summary index 473bad4..1ee9b31 100644 --- a/Quartus/A2/output_files/assignment2.map.summary +++ b/Quartus/A2/output_files/assignment2.map.summary @@ -1,12 +1,17 @@ -Analysis & Synthesis Status : Failed - Tue Oct 13 12:21:52 2026 +Analysis & Synthesis Status : Successful - Tue Oct 13 13:23:27 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : assignment2 Top-level Entity Name : assignment2 Family : Cyclone V -Logic utilization (in ALMs) : N/A until Partition Merge -Total registers : N/A until Partition Merge -Total pins : N/A until Partition Merge -Total virtual pins : N/A until Partition Merge -Total block memory bits : N/A until Partition Merge -Total PLLs : N/A until Partition Merge -Total DLLs : N/A until Partition Merge +Logic utilization (in ALMs) : N/A +Total registers : 0 +Total pins : 1 +Total virtual pins : 0 +Total block memory bits : 0 +Total DSP Blocks : 0 +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/Quartus/A2/output_files/assignment2.pin b/Quartus/A2/output_files/assignment2.pin new file mode 100644 index 0000000..55e64f0 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.pin @@ -0,0 +1,750 @@ + -- Copyright (C) 2025 Altera Corporation. All rights reserved. + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, the Altera Quartus Prime License Agreement, + -- the Altera IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Altera and sold by Altera or its authorized distributors. Please + -- refer to the Altera Software License Subscription Agreements + -- on the Quartus Prime software download page. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 3A: 2.5V + -- Bank 3B: 2.5V + -- Bank 4A: 2.5V + -- Bank 5A: 2.5V + -- Bank 5B: 2.5V + -- Bank 6A: 2.5V + -- Bank 7A: 2.5V + -- Bank 8A: 2.5V + -- Bank 9A: Dedicated configuration pins only, no VCCIO required. + -- RREF : External reference resistor for the quad, MUST be connected to + -- GND via a 2k Ohm resistor. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin + -- must not be connected. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +CHIP "assignment2" ASSIGNED TO AN: 5CGXFC5C6F27C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +MSEL2 : A2 : : : : 9A : +DNU : A3 : : : : : +DNU : A4 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A : +CONF_DONE : A6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A : +VCCIO7A : A10 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A : +GND : A15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : +VCCIO7A : A20 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A : +GND : A25 : gnd : : : : +GND : AA1 : gnd : : : : +GND : AA2 : gnd : : : : +GXB_NC : AA3 : : : : B0L : +GXB_NC : AA4 : : : : B0L : +GND : AA5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : +VCC_AUX : AA8 : power : : 2.5V : : +VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : +NC : AA12 : : : : : +VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4A : +GND : AA15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : +VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : +VCCIO4A : AA20 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B : +GND : AA25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : +GND : AB1 : : : : B0L : +GND : AB2 : : : : B0L : +GND : AB3 : gnd : : : : +GND : AB4 : gnd : : : : +AS_DATA2, DATA2 : AB5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A : +NC : AB7 : : : : : +GND : AB8 : gnd : : : : +VCCPD3A : AB9 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : +VCCIO4A : AB13 : power : : 2.5V : 4A : +VCC_AUX : AB14 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : +GND : AB18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A : +VCC_AUX : AB20 : power : : 2.5V : : +VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A : +VCCIO5A : AB23 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B : +GND : AC1 : gnd : : : : +GND : AC2 : gnd : : : : +GXB_NC : AC3 : : : : B0L : +GXB_NC : AC4 : : : : B0L : +GND : AC5 : gnd : : : : +VCCIO3A : AC6 : power : : 2.5V : 3A : +VREFB3AN0 : AC7 : power : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B : +GND : AC11 : gnd : : : : +VREFB3BN0 : AC12 : power : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : +VCCIO4A : AC16 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A : +GND : AC21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B : +GND : AC26 : gnd : : : : +GND : AD1 : : : : B0L : +GND : AD2 : : : : B0L : +GND : AD3 : gnd : : : : +GND : AD4 : gnd : : : : +AS_DATA1, DATA1 : AD5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : +VCCIO3B : AD9 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A : +GND : AD14 : gnd : : : : +VREFB4AN0 : AD15 : power : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : +VCCIO4A : AD19 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : +GND : AD24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A : +GND : AE1 : gnd : : : : +GND : AE2 : gnd : : : : +GXB_NC : AE3 : : : : B0L : +GXB_NC : AE4 : : : : B0L : +GND : AE5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B : +GND : AE7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : +VCCIO4A : AE12 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : +GND : AE17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : +VCCIO4A : AE22 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A : +GND : AF2 : gnd : : : : +GND : AF3 : gnd : : : : +GND : AF4 : gnd : : : : +AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : +GND : AF10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : +VCCIO4A : AF15 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A : +GND : AF20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : +GND : AF25 : gnd : : : : +RREF : B1 : : : : : +GND : B2 : gnd : : : : +GND : B3 : gnd : : : : +GND : B4 : gnd : : : : +nSTATUS : B5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A : +GND : B8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A : +VCCIO7A : B13 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A : +VREFB7AN0 : B16 : power : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A : +VCCIO7A : B23 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : +GND : C1 : gnd : : : : +GND : C2 : gnd : : : : +NC : C3 : : : : : +NC : C4 : : : : : +GND : C5 : gnd : : : : +VCCIO8A : C6 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A : +VREFB8AN0 : C8 : power : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7A : +GND : C11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A : +VCCIO7A : C16 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A : +GND : C21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A : +DNU : C24 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 6A : +VCCIO6A : C26 : power : : 2.5V : 6A : +NC : D1 : : : : : +NC : D2 : : : : : +GND : D3 : gnd : : : : +GND : D4 : gnd : : : : +nCE : D5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A : +VCCIO8A : D9 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A : +GND : D14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A : +VCCIO7A : D19 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A : +GND : D23 : : : : 7A : +GND : D24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A : +GND : E1 : gnd : : : : +GND : E2 : gnd : : : : +NC : E3 : : : : : +NC : E4 : : : : : +GND : E5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A : +GND : E7 : gnd : : : : +VCCBAT : E8 : power : : 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: : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : +VCCIO3B : U8 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A : +GND : U13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : +VCCIO4A : U18 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : +VCCPD5A : U21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : +GND : U23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B : +GND : V1 : : : : B1L : +GND : V2 : : : : B1L : +GND : V3 : gnd : : : : +GND : V4 : gnd : : : : +GND : V5 : gnd : : : : +GND : V6 : : : : B0L : +TDO : V7 : output : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : +VCCIO3B : V11 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A : +GND : V16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A : +VCCIO5A : V21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : +GND : V26 : gnd : : : : +GND : W1 : gnd : : : : +GND : W2 : gnd : : : : +GXB_NC : W3 : : : : B1L : +GXB_NC : W4 : : : : B1L : +GND : W5 : gnd : : : : +GND : W6 : : : : B0L : +VCCA_FPLL : W7 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : +GND : W9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : +VCCIO4A : W14 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A : +GND : W19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A : +VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : +VREFB5AN0 : W23 : power : : : 5A : +VCCIO5B : W24 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B : +GND : Y1 : : : : B0L : +GND : Y2 : : : : B0L : +GND : Y3 : gnd : : : : +GND : Y4 : gnd : : : : +TCK : Y5 : input : : : 3A : +nCSO, DATA4 : Y6 : : : : 3A : +VCCIO3A : Y7 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : +VCCIO4A : Y17 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : +VCCA_FPLL : Y21 : power : : 2.5V : : +GND : Y22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B : diff --git a/Quartus/A2/output_files/assignment2.sld b/Quartus/A2/output_files/assignment2.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.sld @@ -0,0 +1 @@ + diff --git a/Quartus/A2/output_files/assignment2.sof b/Quartus/A2/output_files/assignment2.sof new file mode 100644 index 0000000..bf0a165 Binary files /dev/null and b/Quartus/A2/output_files/assignment2.sof differ diff --git a/Quartus/A2/output_files/assignment2.sta.rpt b/Quartus/A2/output_files/assignment2.sta.rpt new file mode 100644 index 0000000..f421b44 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.sta.rpt @@ -0,0 +1,431 @@ +Timing Analyzer report for assignment2 +Tue Oct 13 13:24:08 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1100mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1100mV 85C Model Setup Summary + 8. Slow 1100mV 85C Model Hold Summary + 9. Slow 1100mV 85C Model Recovery Summary + 10. Slow 1100mV 85C Model Removal Summary + 11. Slow 1100mV 85C Model Minimum Pulse Width Summary + 12. Slow 1100mV 85C Model Metastability Summary + 13. Slow 1100mV 0C Model Fmax Summary + 14. Slow 1100mV 0C Model Setup Summary + 15. Slow 1100mV 0C Model Hold Summary + 16. Slow 1100mV 0C Model Recovery Summary + 17. Slow 1100mV 0C Model Removal Summary + 18. Slow 1100mV 0C Model Minimum Pulse Width Summary + 19. Slow 1100mV 0C Model Metastability Summary + 20. Fast 1100mV 85C Model Setup Summary + 21. Fast 1100mV 85C Model Hold Summary + 22. Fast 1100mV 85C Model Recovery Summary + 23. Fast 1100mV 85C Model Removal Summary + 24. Fast 1100mV 85C Model Minimum Pulse Width Summary + 25. Fast 1100mV 85C Model Metastability Summary + 26. Fast 1100mV 0C Model Setup Summary + 27. Fast 1100mV 0C Model Hold Summary + 28. Fast 1100mV 0C Model Recovery Summary + 29. Fast 1100mV 0C Model Removal Summary + 30. Fast 1100mV 0C Model Minimum Pulse Width Summary + 31. Fast 1100mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1100mv 0c Model) + 36. Signal Integrity Metrics (Slow 1100mv 85c Model) + 37. Signal Integrity Metrics (Fast 1100mv 0c Model) + 38. Signal Integrity Metrics (Fast 1100mv 85c Model) + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; assignment2 ; +; Device Family ; Cyclone V ; +; Device Name ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.1% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1100mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +--------------------------------------- +; Fast 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Fast 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++-----+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-----------------------------------------------------------+ +; Input Transition Times ; ++--------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++--------+--------------+-----------------+-----------------+ +; clk[0] ; 2.5 V ; 2000 ps ; 2000 ps ; ++--------+--------------+-----------------+-----------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-----+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 0 ; 0 ; +; Unconstrained Input Port Paths ; 0 ; 0 ; +; Unconstrained Output Ports ; 0 ; 0 ; +; Unconstrained Output Port Paths ; 0 ; 0 ; ++---------------------------------+-------+------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Oct 13 13:24:04 2026 +Info: Command: quartus_sta assignment2 -c assignment2 +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'assignment2.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1100mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332101): Design is fully constrained for setup requirements +Info (332101): Design is fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 718 megabytes + Info: Processing ended: Tue Oct 13 13:24:08 2026 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + diff --git a/Quartus/A2/output_files/assignment2.sta.summary b/Quartus/A2/output_files/assignment2.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/Quartus/A2/output_files/assignment2.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/Quartus/A2/simulation/questa/assignment2.sft b/Quartus/A2/simulation/questa/assignment2.sft new file mode 100644 index 0000000..dfcc4cf --- /dev/null +++ b/Quartus/A2/simulation/questa/assignment2.sft @@ -0,0 +1 @@ +set tool_name "Questa Altera FPGA (SystemVerilog)" diff --git a/Quartus/A2/simulation/questa/assignment2.svo b/Quartus/A2/simulation/questa/assignment2.svo new file mode 100644 index 0000000..79eee10 --- /dev/null +++ b/Quartus/A2/simulation/questa/assignment2.svo @@ -0,0 +1,89 @@ +// Copyright (C) 2025 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, the Altera Quartus Prime License Agreement, +// the Altera IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Altera and sold by Altera or its authorized distributors. Please +// refer to the Altera Software License Subscription Agreements +// on the Quartus Prime software download page. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" + +// DATE "10/13/2026 13:24:10" + +// +// Device: Altera 5CGXFC5C6F27C7 Package FBGA672 +// + +// +// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only +// + +`timescale 1 ps/ 1 ps + +module assignment2 ( + clk); +input logic [0:0] clk ; + +// Design Ports Information +// clk[0] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \clk[0]~input_o ; +wire \~QUARTUS_CREATED_GND~I_combout ; + + +// Location: IOIBUF_X68_Y32_N61 +cyclonev_io_ibuf \clk[0]~input ( + .i(clk[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\clk[0]~input_o )); +// synopsys translate_off +defparam \clk[0]~input .bus_hold = "false"; +defparam \clk[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X9_Y53_N0 +cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off"; +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000; +defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off"; +// synopsys translate_on + +endmodule diff --git a/modules/assignment2.sv b/modules/assignment2.sv index c6e6762..fff260b 100644 --- a/modules/assignment2.sv +++ b/modules/assignment2.sv @@ -65,6 +65,9 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); logic [2**width-1:0] rd_shifter; shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter); - rd = en_alu ? rd_alu : (en_shifter ? : rd_shifter : ({(2**width){1'b0}})); + assign rd = en_alu + ? rd_alu + : (en_shifter ? rd_shifter : {2**width{1'b0}}); + endmodule `endif diff --git a/modules/instruction_module_classifier.sv b/modules/instruction_module_classifier.sv index a880c87..f51244a 100644 --- a/modules/instruction_module_classifier.sv +++ b/modules/instruction_module_classifier.sv @@ -1,12 +1,12 @@ -`ifndef INSTRUCTION_CLASSIFIER_H_SV -`define INSTRUCTION_CLASSIFIER_H_SV +`ifndef INSTRUCTION_MODULE_CLASSIFIER_H_SV +`define INSTRUCTION_MODULE_CLASSIFIER_H_SV module instruction_module_classifier( input logic [2:0] op, output logic en_shifter, output logic en_jmp, output logic en_mul, - output logic en_alu, + output logic en_alu ); always_comb begin en_shifter = (op & 3'b111) == 3'b000; @@ -15,4 +15,4 @@ module instruction_module_classifier( en_alu = (op & 3'b100) == 3'b100; end endmodule -`endif \ No newline at end of file +`endif diff --git a/modules/rom.sv b/modules/rom.sv index 80e6a4b..a07103d 100644 --- a/modules/rom.sv +++ b/modules/rom.sv @@ -12,7 +12,7 @@ module rom #(parameter m=7,p=4) ( //Load the program in memory // The machine code stored in text file program.dat written in Hex format initial begin - `ifdef QUARTUS_BUILD + `ifdef QUARTUS_SYNTH $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary `else $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary