Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
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143 files changed
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-109
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@@ -1,15 +1,32 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791854502822 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 12:21:42 2026 " "Processing started: Tue Oct 13 12:21:42 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791854502823 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854502823 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791854503126 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_we assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_we\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_IDENTIFIER_ALREADY_DECLARED" "pc_addr assignment2.sv(26) " "Verilog HDL Declaration error at assignment2.sv(26): identifier \"pc_addr\" is already declared in the present scope" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10149 "Verilog HDL Declaration error at %2!s!: identifier \"%1!s!\" is already declared in the present scope" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting \";\" assignment2.sv(26) " "Verilog HDL syntax error at assignment2.sv(26) near text: \")\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(27) " "Verilog HDL syntax error at assignment2.sv(27) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 27 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(28) " "Verilog HDL syntax error at assignment2.sv(28) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 28 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"#\"; expecting \";\" assignment2.sv(29) " "Verilog HDL syntax error at assignment2.sv(29) near text: \"#\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 29 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(20) " "Ignored design unit \"assignment2\" at assignment2.sv(20) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 20 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791854512633 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512634 ""}
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{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 8 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 12:21:52 2026 " "Processing ended: Tue Oct 13 12:21:52 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791854512678 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791854512678 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791858197350 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 13:23:17 2026 " "Processing started: Tue Oct 13 13:23:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791858197351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858197351 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791858197661 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 11 11 " "Found 11 design units, including 11 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "2 ram " "Found entity 2: ram" { } { { "../../modules/ram.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "3 register_file " "Found entity 3: register_file" { } { { "../../modules/register_file.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "4 instruction_counter " "Found entity 4: instruction_counter" { } { { "../../modules/instruction_counter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "5 instruction_classifier " "Found entity 5: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "6 instruction_module_classifier " "Found entity 6: instruction_module_classifier" { } { { "../../modules/instruction_module_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "7 asu " "Found entity 7: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "8 lu " "Found entity 8: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "9 alu " "Found entity 9: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "10 shifter " "Found entity 10: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} { "Info" "ISGN_ENTITY_NAME" "11 assignment2 " "Found entity 11: assignment2" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1791858206828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858206828 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "assignment2 " "Elaborating entity \"assignment2\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1791858206971 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rd assignment2.sv(48) " "Verilog HDL or VHDL warning at assignment2.sv(48): object \"rd\" assigned a value but never read" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 48 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1791858206973 "|assignment2"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_counter instruction_counter:PC " "Elaborating entity \"instruction_counter\" for hierarchy \"instruction_counter:PC\"" { } { { "../../modules/assignment2.sv" "PC" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206990 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:ROM " "Elaborating entity \"rom\" for hierarchy \"rom:ROM\"" { } { { "../../modules/assignment2.sv" "ROM" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858206997 ""}
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{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "18 0 1023 rom.sv(16) " "Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range \[0:1023\]" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 16 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1791858207006 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.data_a 0 rom.sv(9) " "Net \"mem.data_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.waddr_a 0 rom.sv(9) " "Net \"mem.waddr_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
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{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "mem.we_a 0 rom.sv(9) " "Net \"mem.we_a\" at rom.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "../../modules/rom.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1791858207032 "|assignment2|rom:ROM"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_classifier instruction_classifier:INSTRUCTION_CLASSIFIER " "Elaborating entity \"instruction_classifier\" for hierarchy \"instruction_classifier:INSTRUCTION_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207036 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instruction_module_classifier instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER " "Elaborating entity \"instruction_module_classifier\" for hierarchy \"instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER\"" { } { { "../../modules/assignment2.sv" "INSTRUCTION_MODULE_CLASSIFIER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 54 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207039 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "register_file register_file:REGS " "Elaborating entity \"register_file\" for hierarchy \"register_file:REGS\"" { } { { "../../modules/assignment2.sv" "REGS" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207041 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:ALU " "Elaborating entity \"alu\" for hierarchy \"alu:ALU\"" { } { { "../../modules/assignment2.sv" "ALU" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207048 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu alu:ALU\|asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"alu:ALU\|asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 18 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207054 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu alu:ALU\|lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"alu:ALU\|lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207060 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter shifter:SHIFTER " "Elaborating entity \"shifter\" for hierarchy \"shifter:SHIFTER\"" { } { { "../../modules/assignment2.sv" "SHIFTER" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207066 ""}
|
||||
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207119 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" Line truncated
|
||||
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207120 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" Line truncated
|
||||
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207121 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" Line truncated
|
||||
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207122 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" Line truncated
|
||||
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[31\] " "Net \"rs\[31\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[31\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[30\] " "Net \"rs\[30\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[30\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[29\] " "Net \"rs\[29\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[29\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[28\] " "Net \"rs\[28\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[28\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[27\] " "Net \"rs\[27\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[27\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[26\] " "Net \"rs\[26\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[26\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[25\] " "Net \"rs\[25\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[25\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[24\] " "Net \"rs\[24\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[24\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[23\] " "Net \"rs\[23\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[23\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[22\] " "Net \"rs\[22\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[22\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[21\] " "Net \"rs\[21\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[21\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[20\] " "Net \"rs\[20\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[20\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[19\] " "Net \"rs\[19\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[19\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 46 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1791858207124 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rs\[18\] " "Net \"rs\[18\]\" is missing source, defaulting to GND" { } { { "../../modules/assignment2.sv" "rs\[18\]" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" Line truncated
|
||||
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1791858207654 ""}
|
||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1791858207721 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1791858207864 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791858207864 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk\[0\] " "No output dependent on input pin \"clk\[0\]\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1791858207996 "|assignment2|clk[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "1 " "Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1791858207996 ""} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Implemented 0 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1791858207996 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1791858207996 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 174 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 174 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 13 13:23:28 2026 " "Processing ended: Tue Oct 13 13:23:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791858208006 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791858208006 ""}
|
||||
Reference in new issue
Block a user