Added Q4 sumbission and comments
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`ifndef ALU_H_SV
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`define ALU_H_SV
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`ifndef LU_H_SV
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`define LU_H_SV
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module lu #(parameter width = 2) (
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input logic [1:0] op, // 2 bit operand
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input logic [2**width-1:0] A, // width defined as 2^n
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input logic [2**width-1:0] B,
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output logic [2**width-1:0] Y);
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always_comb begin
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case (op) // different operations of A and B based on operand
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2'b00: Y = A & B;
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2'b01: Y = A | B;
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2'b10: Y = A ^ B;
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2'b11: Y = ~(A | B);
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default:Y = '0;
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endcase
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end
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endmodule
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`endif
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`ifndef SEVEN_SEG_H_SV
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`define SEVEN_SEG_H_SV
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module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
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always_comb begin
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case (num)
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4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
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4'b0001: segments = ~(8'b00001101);
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4'b0010: segments = ~(8'b10110111);
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4'b0011: segments = ~(8'b10011111);
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4'b0100: segments = ~(8'b11001101);
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4'b0101: segments = ~(8'b11011011);
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4'b0110: segments = ~(8'b11111011);
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4'b0111: segments = ~(8'b00001111);
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4'b1000: segments = ~(8'b11111111);
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4'b1001: segments = ~(8'b11001111);
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4'b1010: segments = ~(8'b11101111);
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4'b1011: segments = ~(8'b11111001);
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4'b1100: segments = ~(8'b01110011);
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4'b1101: segments = ~(8'b10111101);
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4'b1110: segments = ~(8'b11110011);
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4'b1111: segments = ~(8'b11100011);
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default: segments = ~(8'bxxxxxxxx);
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endcase
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end
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endmodule
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`endif
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`ifndef ASU_H_SV
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`define ASU_H_SV
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module asu #(parameter width = 2)(
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input logic [0:0] op,
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input logic[2**width-1:0] A, input logic[2**width-1:0] B,
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output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
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// Used to switch between demo mode and testbench mode
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// TODO: Strip for assignment 2
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`ifdef SYNTHESIS
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, output logic[7:0] out_seg_1);
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`else
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);
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`endif
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logic [2**width-1:0] operand;
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always_comb begin
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// A + (sub) ? B : -B
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// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
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//operand = (B ^ {(2**width){op}});
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operand = op == 1'b0 ? B : ~B;
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{COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
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end
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// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
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// Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
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assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
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// Include seven segment visual output for hardware builds only
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// TODO: Strip this for assignment 2 outright
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`ifdef SYNTHESIS
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seven_seg dut(OUT_1, 1'b1, out_seg_1);
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`endif
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endmodule
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`endif
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// flags[0:0] = Cout
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// flags[1:1] = Overflow
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module alu #(parameter width=2)(input logic [3:0] op,
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input logic [2**width-1:0] A, input logic [2**width-1:0] B,
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output logic [2**width-1:0] OUT_1, output logic[1:0] flags
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`ifdef SYNTHESIS
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, output logic [7:0] out_seg1);
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`else
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);
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`endif
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// intermediate logic for handling asu output
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logic [0:0] asu_op;
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logic [2**width-1:0] asu_out;
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logic [1:0] asu_flags;
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logic [7:0] asu_seven_seg_out;
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// NOTE: For demo only
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// TODO: Strip this for assignment 2
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`ifdef SYNTHESIS
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asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
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`else
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asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
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`endif
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logic [2**width-1:0] lu_out;
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lu #(width) logic_unit(op[1:0], A, B, lu_out);
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always_comb begin
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case (op)
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4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
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4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
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4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end
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4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
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4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
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4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
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default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
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endcase
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end
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// NOTE: For demo only
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// TODO: Strip this for assignment 2
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`ifdef SYNTHESIS
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seven_seg dut(OUT_1, 1'b1, out_seg1);
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`endif
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endmodule
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`endif
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// Testbench
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module alu_tb #(width=2)();
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localparam bitwidth = 2**width;
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// Guard against future me by testing the tests
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generate
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if (bitwidth < 4) begin : param_asserts
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initial begin
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$fatal(1, "Can not instantiate an ALU testbench with less than 4 bits (n=2)");
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end
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end
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endgenerate
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logic [3:0] op_in;
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logic [2**width-1:0] A_in;
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logic [2**width-1:0] B_in;
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logic [2**width-1:0] Y_out;
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logic [1:0] flags_out;
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localparam int NUM_TESTS = 28;
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logic [3:0] ops[NUM_TESTS];
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logic [2**width-1:0] A_cases[NUM_TESTS];
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logic [2**width-1:0] B_cases[NUM_TESTS];
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logic [2**width-1:0] Y_exp[NUM_TESTS];
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logic [1:0] flags_exp[NUM_TESTS];
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alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out);
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integer error_count;
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initial begin
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ops[0] = 4'b0000; // sadd
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A_in[0] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[0] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[0] = {{(bitwidth-2){1'b0}}, 2'b10}; // 0
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flags_exp[0] = {2'b00}; // ~Cout, ~Overflow
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ops[1] = 4'b0000; // sadd
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A_in[1] = {bitwidth{1'b1}}; // UINTMAX
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B_in[1] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[1] = {bitwidth{1'b0}}; // 0
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flags_exp[1] = {2'b01}; // Cout, ~Overflow
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ops[2] = 4'b0000; // sadd
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A_in[2] = {{1'b0}, {(bitwidth-1){1'b1}}}; // INTMAX
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B_in[2] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
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Y_exp[2] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
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flags_exp[2] = {2'b10}; // ~Cout, Overflow
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ops[3] = 4'b0000; // sadd
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A_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX
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B_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX
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Y_exp[3] = {bitwidth{1'b0}}; // 0
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flags_exp[3] = {2'b11}; // Cout, Overflow
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ops[4] = 4'b0001; // uadd
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A_in[4] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[4] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[4] = {{(bitwidth-2){1'b0}}, 2'b10}; // 0
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flags_exp[4] = {2'b00}; // ~Cout, ~Overflow
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ops[5] = 4'b0001; // uadd
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A_in[5] = {bitwidth{1'b1}}; // UINTMAX
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B_in[5] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[5] = {bitwidth{1'b0}}; // 0
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flags_exp[5] = {2'b01}; // Cout, ~Overflow
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ops[6] = 4'b0001; // uadd
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A_in[6] = {{1'b0}, {(bitwidth-1){1'b1}}}; // INTMAX
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B_in[6] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
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Y_exp[6] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
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flags_exp[6] = {2'b10}; // ~Cout, Overflow
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ops[7] = 4'b0001; // uadd
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A_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX
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B_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX
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Y_exp[7] = {bitwidth{1'b0}}; // 0
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flags_exp[7] = {2'b11}; // Cout, Overflow
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ops[8] = 4'b0010; // ssub
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A_in[8] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[8] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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Y_exp[8] = {bitwidth{1'b1}}; // -1
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flags_exp[8] = {2'b00}; // ~Cout, ~Overflow
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ops[9] = 4'b0010; // ssub
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A_in[9] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX
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B_in[9] = {{(bitwidth-1){1'b0}}, 1'b1}; // -1
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Y_exp[9] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX
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flags_exp[9] = {2'b10}; // ~Cout, Overflow
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ops[10] = 4'b0010; // ssub
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A_in[10] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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B_in[10] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[10] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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flags_exp[10] = {2'b01}; // Cout, ~Overflow
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ops[11] = 4'b0010; // ssub
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A_in[11] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX
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B_in[11] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[11] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX
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flags_exp[11] = {2'b11}; // Cout, Overflow
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ops[12] = 4'b0011; // ssub
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A_in[12] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[12] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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Y_exp[12] = {bitwidth{1'b1}}; // -1
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flags_exp[12] = {2'b00}; // ~Cout, ~Overflow
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ops[13] = 4'b0011; // ssub
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A_in[13] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX
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B_in[13] = {{(bitwidth-1){1'b0}}, 1'b1}; // -1
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Y_exp[13] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX
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flags_exp[13] = {2'b10}; // ~Cout, Overflow
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ops[14] = 4'b0011; // ssub
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A_in[14] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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B_in[14] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[14] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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flags_exp[14] = {2'b01}; // Cout, ~Overflow
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ops[15] = 4'b0011; // ssub
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A_in[15] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX
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B_in[15] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[15] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX
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flags_exp[15] = {2'b11}; // Cout, Overflow
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ops[16] = 4'b0100; // and
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A_in[16] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c
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B_in[16] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a
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Y_exp[16] = {{(bitwidth-4){1'b0}}, 4'b1000}; // 8
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flags_exp[16] = {2'bxx}; // Don't care
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ops[17] = 4'b0101; // or
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A_in[17] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c
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B_in[17] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a
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Y_exp[17] = {{(bitwidth-4){1'b0}}, 4'b1110}; // e
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flags_exp[17] = {2'bxx}; // Don't care
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ops[18] = 4'b0110; // xor
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A_in[18] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c
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B_in[18] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a
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Y_exp[18] = {{(bitwidth-4){1'b0}}, 4'b0110}; // 6
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flags_exp[18] = {2'bxx}; // Don't care
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ops[19] = 4'b0111; // nor
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A_in[19] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c
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B_in[19] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a
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Y_exp[19] = {{(bitwidth-4){1'b0}}, 4'b0001}; // 1
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flags_exp[19] = {2'bxx}; // Don't care
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ops[20] = 4'b1010; // sslt: 1 < 2 (No overflow)
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A_in[20] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[20] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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Y_exp[20] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True)
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flags_exp[20] = {2'b00}; // ~Cout, ~Overflow
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ops[21] = 4'b1010; // sslt: 2 < 1 (No overflow)
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A_in[21] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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B_in[21] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[21] = {bitwidth{1'b0}}; // 0 (False)
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flags_exp[21] = {2'b10}; // Cout, ~Overflow
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ops[22] = 4'b1010; // sslt: -INTMAX < 1 (Overflow test)
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A_in[22] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX
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B_in[22] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[22] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True)
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flags_exp[22] = {2'b11}; // Cout, Overflow
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ops[23] = 4'b1010; // sslt: INTMAX < -1 (Overflow test)
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A_in[23] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX
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B_in[23] = {bitwidth{1'b1}}; // -1
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Y_exp[23] = {bitwidth{1'b0}}; // 0 (False)
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flags_exp[23] = {2'b01}; // ~Cout, Overflow
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ops[24] = 4'b1011; // uslt: 1 < 2
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A_in[24] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[24] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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Y_exp[24] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True)
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flags_exp[24] = {2'b00}; // ~Cout, ~Overflow
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ops[25] = 4'b1011; // uslt: 2 < 1
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A_in[25] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2
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B_in[25] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[25] = {bitwidth{1'b0}}; // 0 (False)
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flags_exp[25] = {2'b10}; // Cout, ~Overflow
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ops[26] = 4'b1011; // uslt: 1 < UINTMAX
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A_in[26] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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B_in[26] = {bitwidth{1'b1}}; // UINTMAX
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Y_exp[26] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True)
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flags_exp[26] = {2'b00}; // ~Cout, ~Overflow
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ops[27] = 4'b1011; // uslt: UINTMAX < 1
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A_in[27] = {bitwidth{1'b1}}; // UINTMAX
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B_in[27] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1
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Y_exp[27] = {bitwidth{1'b0}}; // 0 (False)
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flags_exp[27] = {2'b10}; // Cout, ~Overflow
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error_count = 0;
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$display("Beginning ALU tests");
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for (integer N = 0; N < $size(ops); ++N) begin
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op_in = ops[N];
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A_in = A_cases[N];
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B_in = B_cases[N];
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#1;
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if (Y_out != Y_exp[N]) begin
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$display("\t\x1b[38;5;9m[%0d] ALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", N, op_in, flags_out, Y_out, flags_exp[N], Y_exp[N]);
|
||||
error_count = error_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m");
|
||||
else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count);
|
||||
end
|
||||
endmodule
|
||||
+2
-2
@@ -15,7 +15,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
|
||||
`else
|
||||
);
|
||||
`endif
|
||||
|
||||
// intermediate logic for handling asu output
|
||||
logic [0:0] asu_op;
|
||||
logic [2**width-1:0] asu_out;
|
||||
logic [1:0] asu_flags;
|
||||
@@ -54,4 +54,4 @@ module alu #(parameter width=2)(input logic [3:0] op,
|
||||
seven_seg dut(OUT_1, 1'b1, out_seg1);
|
||||
`endif
|
||||
endmodule
|
||||
`endif
|
||||
`endif
|
||||
Reference in new issue
Block a user