68 lines
2.3 KiB
Verilog
68 lines
2.3 KiB
Verilog
`include "seven_seg.v"
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module seven_seg_tb();
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logic [3:0] in_num;
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logic [0:0] in_rbi_inv;
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logic [7:0] out_segments;
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logic [7:0] true_segments[17];
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seven_seg dut(in_num, in_rbi_inv, out_segments);
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integer N;
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integer i;
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integer error_count;
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initial begin
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// Initialise truth table
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true_segments[0 ] = 8'b11111101;
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true_segments[1 ] = 8'b01100001;
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true_segments[2 ] = 8'b11011011;
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true_segments[3 ] = 8'b11110011;
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true_segments[4 ] = 8'b01100111;
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true_segments[5 ] = 8'b10110111;
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true_segments[6 ] = 8'b10111111;
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true_segments[7 ] = 8'b11100001;
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true_segments[8 ] = 8'b11111111;
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true_segments[9 ] = 8'b11100111;
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true_segments[10] = 8'b11101111;
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true_segments[11] = 8'b00111111;
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true_segments[12] = 8'b10011101;
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true_segments[13] = 8'b01111011;
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true_segments[14] = 8'b10011111;
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true_segments[15] = 8'b10001111;
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true_segments[16] = 8'b00000000;
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$display("Beginning seven-segment tests");
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in_num = 4'd0;
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in_rbi_inv = 1'b0;
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error_count = 0;
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#1;
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if (out_segments !== true_segments[16]) begin
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$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[16], out_segments);
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error_count = error_count + 1;
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end
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for (N=1; N < 15; ++N) begin
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in_num = in_num + 1;
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#1;
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if (out_segments !== true_segments[N]) begin
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$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
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error_count = error_count + 1;
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end
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end
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in_num = 4'd0;
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in_rbi_inv = 1'b1;
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for (N=0; N < 15; ++N) begin
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#1;
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if (out_segments !== true_segments[N]) begin
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$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
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error_count = error_count + 1;
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end
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in_num = in_num + 1;
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll seven-segment tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d seven-segment test(s) failing\x1b[m", error_count);
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end
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endmodule |