13 lines
345 B
Verilog
13 lines
345 B
Verilog
module shifter #(width=8)(input logic op[1:0],
|
|
input logic[width-1:0] A, input logic[width-1:0] B,
|
|
output logic[width-1:0] OUT_1);
|
|
|
|
always_comb begin
|
|
case (op)
|
|
00: OUT_1 = A << B;
|
|
01: OUT_1 = A >> B;
|
|
10: OUT_1 = $signed(A) >>> B;
|
|
default:;
|
|
endcase
|
|
end
|
|
endmodule |