Added all Testbenches to Modelsim and confirmed working operation
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@@ -0,0 +1 @@
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set tool_name "Questa Altera FPGA (SystemVerilog)"
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@@ -0,0 +1,437 @@
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// Copyright (C) 2025 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, the Altera Quartus Prime License Agreement,
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// the Altera IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Altera and sold by Altera or its authorized distributors. Please
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// refer to the Altera Software License Subscription Agreements
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// on the Quartus Prime software download page.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
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// DATE "09/15/2026 10:20:23"
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//
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// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
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//
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//
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// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
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//
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`timescale 1 ps/ 1 ps
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module instruction_classifier (
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op,
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R,
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B1,
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J,
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B2,
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I,
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F,
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M);
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input logic [5:0] op ;
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output logic [0:0] R ;
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output logic [0:0] B1 ;
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output logic [0:0] J ;
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output logic [0:0] B2 ;
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output logic [0:0] I ;
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output logic [0:0] F ;
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output logic [0:0] M ;
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// Design Ports Information
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// R[0] => Location: PIN_W10, I/O Standard: 2.5 V, Current Strength: Default
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// B1[0] => Location: PIN_AC10, I/O Standard: 2.5 V, Current Strength: Default
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// J[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default
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// B2[0] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
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// I[0] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default
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// F[0] => Location: PIN_Y10, I/O Standard: 2.5 V, Current Strength: Default
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// M[0] => Location: PIN_T11, I/O Standard: 2.5 V, Current Strength: Default
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// op[0] => Location: PIN_AB12, I/O Standard: 2.5 V, Current Strength: Default
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// op[1] => Location: PIN_AB11, I/O Standard: 2.5 V, Current Strength: Default
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// op[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default
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// op[3] => Location: PIN_AC8, I/O Standard: 2.5 V, Current Strength: Default
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// op[4] => Location: PIN_AC9, I/O Standard: 2.5 V, Current Strength: Default
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// op[5] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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wire \op[5]~input_o ;
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wire \op[0]~input_o ;
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wire \op[2]~input_o ;
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wire \op[1]~input_o ;
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wire \op[4]~input_o ;
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wire \op[3]~input_o ;
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wire \Equal0~0_combout ;
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wire \Equal1~0_combout ;
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wire \Equal2~0_combout ;
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wire \Equal3~0_combout ;
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wire \Equal4~0_combout ;
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wire \Equal5~0_combout ;
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// Location: IOOBUF_X15_Y0_N36
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cyclonev_io_obuf \R[0]~output (
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.i(\Equal0~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(R[0]),
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.obar());
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// synopsys translate_off
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defparam \R[0]~output .bus_hold = "false";
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defparam \R[0]~output .open_drain_output = "false";
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defparam \R[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X12_Y0_N53
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cyclonev_io_obuf \B1[0]~output (
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.i(\Equal1~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(B1[0]),
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.obar());
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// synopsys translate_off
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defparam \B1[0]~output .bus_hold = "false";
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defparam \B1[0]~output .open_drain_output = "false";
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defparam \B1[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X15_Y0_N19
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cyclonev_io_obuf \J[0]~output (
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.i(\Equal2~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(J[0]),
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.obar());
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// synopsys translate_off
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defparam \J[0]~output .bus_hold = "false";
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defparam \J[0]~output .open_drain_output = "false";
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defparam \J[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X15_Y0_N2
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cyclonev_io_obuf \B2[0]~output (
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.i(\Equal3~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(B2[0]),
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.obar());
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// synopsys translate_off
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defparam \B2[0]~output .bus_hold = "false";
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defparam \B2[0]~output .open_drain_output = "false";
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defparam \B2[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X12_Y0_N2
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cyclonev_io_obuf \I[0]~output (
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.i(\Equal4~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(I[0]),
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.obar());
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// synopsys translate_off
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defparam \I[0]~output .bus_hold = "false";
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defparam \I[0]~output .open_drain_output = "false";
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defparam \I[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X15_Y0_N53
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cyclonev_io_obuf \F[0]~output (
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.i(\Equal5~0_combout ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(F[0]),
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.obar());
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// synopsys translate_off
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defparam \F[0]~output .bus_hold = "false";
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defparam \F[0]~output .open_drain_output = "false";
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defparam \F[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X12_Y0_N19
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cyclonev_io_obuf \M[0]~output (
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.i(\op[5]~input_o ),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(M[0]),
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.obar());
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// synopsys translate_off
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defparam \M[0]~output .bus_hold = "false";
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defparam \M[0]~output .open_drain_output = "false";
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defparam \M[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOIBUF_X12_Y0_N35
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cyclonev_io_ibuf \op[5]~input (
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.i(op[5]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[5]~input_o ));
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// synopsys translate_off
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defparam \op[5]~input .bus_hold = "false";
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defparam \op[5]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N1
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cyclonev_io_ibuf \op[0]~input (
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.i(op[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[0]~input_o ));
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// synopsys translate_off
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defparam \op[0]~input .bus_hold = "false";
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defparam \op[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X10_Y0_N75
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cyclonev_io_ibuf \op[2]~input (
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.i(op[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[2]~input_o ));
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// synopsys translate_off
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defparam \op[2]~input .bus_hold = "false";
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defparam \op[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N18
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cyclonev_io_ibuf \op[1]~input (
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.i(op[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[1]~input_o ));
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// synopsys translate_off
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defparam \op[1]~input .bus_hold = "false";
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defparam \op[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N35
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cyclonev_io_ibuf \op[4]~input (
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.i(op[4]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[4]~input_o ));
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// synopsys translate_off
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defparam \op[4]~input .bus_hold = "false";
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defparam \op[4]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X14_Y0_N52
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cyclonev_io_ibuf \op[3]~input (
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.i(op[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[3]~input_o ));
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// synopsys translate_off
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defparam \op[3]~input .bus_hold = "false";
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defparam \op[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: MLABCELL_X14_Y1_N30
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cyclonev_lcell_comb \Equal0~0 (
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// Equation(s):
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// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (!\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) )
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.dataa(!\op[5]~input_o ),
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.datab(!\op[0]~input_o ),
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.datac(!\op[2]~input_o ),
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.datad(!\op[1]~input_o ),
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.datae(!\op[4]~input_o ),
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.dataf(!\op[3]~input_o ),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\Equal0~0_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \Equal0~0 .extended_lut = "off";
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defparam \Equal0~0 .lut_mask = 64'h8000000000000000;
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defparam \Equal0~0 .shared_arith = "off";
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// synopsys translate_on
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// Location: MLABCELL_X14_Y1_N6
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cyclonev_lcell_comb \Equal1~0 (
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// Equation(s):
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// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) )
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.dataa(!\op[5]~input_o ),
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.datab(!\op[0]~input_o ),
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.datac(!\op[2]~input_o ),
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.datad(!\op[1]~input_o ),
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.datae(!\op[4]~input_o ),
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.dataf(!\op[3]~input_o ),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\Equal1~0_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \Equal1~0 .extended_lut = "off";
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defparam \Equal1~0 .lut_mask = 64'h2000000000000000;
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defparam \Equal1~0 .shared_arith = "off";
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// synopsys translate_on
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// Location: MLABCELL_X14_Y1_N42
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cyclonev_lcell_comb \Equal2~0 (
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// Equation(s):
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// \Equal2~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[1]~input_o & !\op[2]~input_o )) ) ) )
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||||
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.dataa(!\op[5]~input_o ),
|
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.datab(!\op[1]~input_o ),
|
||||
.datac(!\op[2]~input_o ),
|
||||
.datad(gnd),
|
||||
.datae(!\op[4]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
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.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Equal2~0_combout ),
|
||||
.sumout(),
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||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Equal2~0 .extended_lut = "off";
|
||||
defparam \Equal2~0 .lut_mask = 64'h2020000000000000;
|
||||
defparam \Equal2~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X14_Y1_N51
|
||||
cyclonev_lcell_comb \Equal3~0 (
|
||||
// Equation(s):
|
||||
// \Equal3~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (\op[2]~input_o & !\op[5]~input_o ) ) ) )
|
||||
|
||||
.dataa(!\op[2]~input_o ),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(!\op[5]~input_o ),
|
||||
.datae(!\op[4]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Equal3~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Equal3~0 .extended_lut = "off";
|
||||
defparam \Equal3~0 .lut_mask = 64'h5500000000000000;
|
||||
defparam \Equal3~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X14_Y1_N24
|
||||
cyclonev_lcell_comb \Equal4~0 (
|
||||
// Equation(s):
|
||||
// \Equal4~0_combout = ( !\op[4]~input_o & ( \op[3]~input_o & ( !\op[5]~input_o ) ) )
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(!\op[5]~input_o ),
|
||||
.datad(gnd),
|
||||
.datae(!\op[4]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Equal4~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Equal4~0 .extended_lut = "off";
|
||||
defparam \Equal4~0 .lut_mask = 64'h00000000F0F00000;
|
||||
defparam \Equal4~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X14_Y1_N3
|
||||
cyclonev_lcell_comb \Equal5~0 (
|
||||
// Equation(s):
|
||||
// \Equal5~0_combout = ( \op[4]~input_o & ( !\op[5]~input_o ) )
|
||||
|
||||
.dataa(!\op[5]~input_o ),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.datae(!\op[4]~input_o ),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Equal5~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Equal5~0 .extended_lut = "off";
|
||||
defparam \Equal5~0 .lut_mask = 64'h0000AAAA0000AAAA;
|
||||
defparam \Equal5~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X55_Y25_N3
|
||||
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
|
||||
// Equation(s):
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
|
||||
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
|
||||
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
endmodule
|
||||
Reference in new issue
Block a user