diff --git a/ModelSim/Assignment_1_Q1.cr.mti b/ModelSim/Assignment_1_Q1.cr.mti new file mode 100644 index 0000000..3205b28 --- /dev/null +++ b/ModelSim/Assignment_1_Q1.cr.mti @@ -0,0 +1,16 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module seven_seg + +Top level modules: + seven_seg + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module seven_seg +-- Compiling module seven_seg_tb + +Top level modules: + seven_seg_tb + +} {} {}} diff --git a/ModelSim/Assignment_1_Q1.mpf b/ModelSim/Assignment_1_Q1.mpf new file mode 100644 index 0000000..5413229 --- /dev/null +++ b/ModelSim/Assignment_1_Q1.mpf @@ -0,0 +1,466 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 ps + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/Assignment_1_Q2.mpf b/ModelSim/Assignment_1_Q2.mpf index ff2872f..5fed1bb 100644 --- a/ModelSim/Assignment_1_Q2.mpf +++ b/ModelSim/Assignment_1_Q2.mpf @@ -412,9 +412,9 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv -Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv -Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ModelSim/Assignment_1_Q3.mpf b/ModelSim/Assignment_1_Q3.mpf index f9d4fc6..a579913 100644 --- a/ModelSim/Assignment_1_Q3.mpf +++ b/ModelSim/Assignment_1_Q3.mpf @@ -412,9 +412,9 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv -Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv -Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1789017573 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ModelSim/Assignment_1_Q4.cr.mti b/ModelSim/Assignment_1_Q4.cr.mti new file mode 100644 index 0000000..f1b7dc1 --- /dev/null +++ b/ModelSim/Assignment_1_Q4.cr.mti @@ -0,0 +1,20 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu + +Top level modules: + alu + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +-- Compiling module alu_tb + +Top level modules: + alu_tb + +} {} {}} diff --git a/ModelSim/Assignment_1_Q4.mpf b/ModelSim/Assignment_1_Q4.mpf new file mode 100644 index 0000000..2b3fa93 --- /dev/null +++ b/ModelSim/Assignment_1_Q4.mpf @@ -0,0 +1,466 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 ps + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/Assignment_1_Q5.cr.mti b/ModelSim/Assignment_1_Q5.cr.mti new file mode 100644 index 0000000..8ec1c90 --- /dev/null +++ b/ModelSim/Assignment_1_Q5.cr.mti @@ -0,0 +1,16 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module shifter + +Top level modules: + shifter + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module shifter +-- Compiling module shifter_tb + +Top level modules: + shifter_tb + +} {} {}} diff --git a/ModelSim/Assignment_1_Q5.mpf b/ModelSim/Assignment_1_Q5.mpf new file mode 100644 index 0000000..13ee7a1 --- /dev/null +++ b/ModelSim/Assignment_1_Q5.mpf @@ -0,0 +1,466 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 ps + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/Assignment_1_Q6.cr.mti b/ModelSim/Assignment_1_Q6.cr.mti new file mode 100644 index 0000000..5eda931 --- /dev/null +++ b/ModelSim/Assignment_1_Q6.cr.mti @@ -0,0 +1,16 @@ +/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_classifier + +Top level modules: + instruction_classifier + +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module instruction_classifier +-- Compiling module instruction_classifier_tb + +Top level modules: + instruction_classifier_tb + +} {} {}} diff --git a/ModelSim/Assignment_1_Q6.mpf b/ModelSim/Assignment_1_Q6.mpf new file mode 100644 index 0000000..fcf4244 --- /dev/null +++ b/ModelSim/Assignment_1_Q6.mpf @@ -0,0 +1,466 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm +sgate = $MODEL_TECH/../altera/vhdl/sgate +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip +cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 ps + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +** Warning: ; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 2 +Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +TDB_DoubleClick = Edit +TDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 2020 +Project_Minor_Version = 1 diff --git a/ModelSim/alu.sv b/ModelSim/alu.sv new file mode 100644 index 0000000..2687745 --- /dev/null +++ b/ModelSim/alu.sv @@ -0,0 +1,37 @@ +`ifndef ALU_H_SV +`define ALU_H_SV + +`include "asu.sv" +`include "lu.sv" + +// flags[0:0] = Cout +// flags[1:1] = Overflow +module alu #(parameter width=2)(input logic [3:0] op, + input logic [2**width-1:0] A, input logic [2**width-1:0] B, + output logic [2**width-1:0] OUT_1, output logic[1:0] flags); + + logic [0:0] asu_op; + logic [2**width-1:0] asu_out; + logic [1:0] asu_flags; + asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]); + + logic [2**width-1:0] lu_out; + lu #(width) logic_unit(op[1:0], A, B, lu_out); + + always_comb begin + case (op) + 4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end + 4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end + 4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end + 4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end + 4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0110: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end + 4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end + 4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end + default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/alu_tb.sv b/ModelSim/alu_tb.sv new file mode 100644 index 0000000..4c4ef15 --- /dev/null +++ b/ModelSim/alu_tb.sv @@ -0,0 +1,216 @@ +`include "alu.sv" + +module alu_tb #(width=2)(); + localparam bitwidth = 2**width; + + // Guard against future me by testing the tests + generate + if (bitwidth < 4) begin : param_asserts + initial begin + $fatal(1, "Can not instantiate an ALU testbench with less than 4 bits (n=2)"); + end + end + endgenerate + + logic [3:0] op_in; + logic [2**width-1:0] A_in; + logic [2**width-1:0] B_in; + logic [2**width-1:0] Y_out; + logic [1:0] flags_out; + + localparam int NUM_TESTS = 28; + logic [3:0] ops[NUM_TESTS]; + logic [2**width-1:0] A_cases[NUM_TESTS]; + logic [2**width-1:0] B_cases[NUM_TESTS]; + logic [2**width-1:0] Y_exp[NUM_TESTS]; + logic [1:0] flags_exp[NUM_TESTS]; + + alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out); + + integer error_count; + initial begin + ops[0] = 4'b0000; // sadd + A_in[0] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[0] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[0] = {{(bitwidth-2){1'b0}}, 2'b10}; // 0 + flags_exp[0] = {2'b00}; // ~Cout, ~Overflow + + ops[1] = 4'b0000; // sadd + A_in[1] = {bitwidth{1'b1}}; // UINTMAX + B_in[1] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[1] = {bitwidth{1'b0}}; // 0 + flags_exp[1] = {2'b01}; // Cout, ~Overflow + + ops[2] = 4'b0000; // sadd + A_in[2] = {{1'b0}, {(bitwidth-1){1'b1}}}; // INTMAX + B_in[2] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1 + Y_exp[2] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX + flags_exp[2] = {2'b10}; // ~Cout, Overflow + + ops[3] = 4'b0000; // sadd + A_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX + B_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX + Y_exp[3] = {bitwidth{1'b0}}; // 0 + flags_exp[3] = {2'b11}; // Cout, Overflow + + ops[4] = 4'b0001; // uadd + A_in[4] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[4] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[4] = {{(bitwidth-2){1'b0}}, 2'b10}; // 0 + flags_exp[4] = {2'b00}; // ~Cout, ~Overflow + + ops[5] = 4'b0001; // uadd + A_in[5] = {bitwidth{1'b1}}; // UINTMAX + B_in[5] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[5] = {bitwidth{1'b0}}; // 0 + flags_exp[5] = {2'b01}; // Cout, ~Overflow + + ops[6] = 4'b0001; // uadd + A_in[6] = {{1'b0}, {(bitwidth-1){1'b1}}}; // INTMAX + B_in[6] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1 + Y_exp[6] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX + flags_exp[6] = {2'b10}; // ~Cout, Overflow + + ops[7] = 4'b0001; // uadd + A_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX + B_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}}; // -INTMAX + Y_exp[7] = {bitwidth{1'b0}}; // 0 + flags_exp[7] = {2'b11}; // Cout, Overflow + + ops[8] = 4'b0010; // ssub + A_in[8] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[8] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + Y_exp[8] = {bitwidth{1'b1}}; // -1 + flags_exp[8] = {2'b00}; // ~Cout, ~Overflow + + ops[9] = 4'b0010; // ssub + A_in[9] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX + B_in[9] = {{(bitwidth-1){1'b0}}, 1'b1}; // -1 + Y_exp[9] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX + flags_exp[9] = {2'b10}; // ~Cout, Overflow + + ops[10] = 4'b0010; // ssub + A_in[10] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + B_in[10] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[10] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + flags_exp[10] = {2'b01}; // Cout, ~Overflow + + ops[11] = 4'b0010; // ssub + A_in[11] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX + B_in[11] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[11] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX + flags_exp[11] = {2'b11}; // Cout, Overflow + + ops[12] = 4'b0011; // ssub + A_in[12] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[12] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + Y_exp[12] = {bitwidth{1'b1}}; // -1 + flags_exp[12] = {2'b00}; // ~Cout, ~Overflow + + ops[13] = 4'b0011; // ssub + A_in[13] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX + B_in[13] = {{(bitwidth-1){1'b0}}, 1'b1}; // -1 + Y_exp[13] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX + flags_exp[13] = {2'b10}; // ~Cout, Overflow + + ops[14] = 4'b0011; // ssub + A_in[14] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + B_in[14] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[14] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + flags_exp[14] = {2'b01}; // Cout, ~Overflow + + ops[15] = 4'b0011; // ssub + A_in[15] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX + B_in[15] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[15] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX + flags_exp[15] = {2'b11}; // Cout, Overflow + + ops[16] = 4'b0100; // and + A_in[16] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c + B_in[16] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a + Y_exp[16] = {{(bitwidth-4){1'b0}}, 4'b1000}; // 8 + flags_exp[16] = {2'bxx}; // Don't care + + ops[17] = 4'b0101; // or + A_in[17] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c + B_in[17] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a + Y_exp[17] = {{(bitwidth-4){1'b0}}, 4'b1110}; // e + flags_exp[17] = {2'bxx}; // Don't care + + ops[18] = 4'b0110; // xor + A_in[18] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c + B_in[18] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a + Y_exp[18] = {{(bitwidth-4){1'b0}}, 4'b0110}; // 6 + flags_exp[18] = {2'bxx}; // Don't care + + ops[19] = 4'b0111; // nor + A_in[19] = {{(bitwidth-4){1'b0}}, 4'b1100}; // c + B_in[19] = {{(bitwidth-4){1'b0}}, 4'b1010}; // a + Y_exp[19] = {{(bitwidth-4){1'b0}}, 4'b0001}; // 1 + flags_exp[19] = {2'bxx}; // Don't care + + ops[20] = 4'b1010; // sslt: 1 < 2 (No overflow) + A_in[20] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[20] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + Y_exp[20] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True) + flags_exp[20] = {2'b00}; // ~Cout, ~Overflow + + ops[21] = 4'b1010; // sslt: 2 < 1 (No overflow) + A_in[21] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + B_in[21] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[21] = {bitwidth{1'b0}}; // 0 (False) + flags_exp[21] = {2'b10}; // Cout, ~Overflow + + ops[22] = 4'b1010; // sslt: -INTMAX < 1 (Overflow test) + A_in[22] = {1'b1, {(bitwidth-1){1'b0}}}; // -INTMAX + B_in[22] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[22] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True) + flags_exp[22] = {2'b11}; // Cout, Overflow + + ops[23] = 4'b1010; // sslt: INTMAX < -1 (Overflow test) + A_in[23] = {1'b0, {(bitwidth-1){1'b1}}}; // INTMAX + B_in[23] = {bitwidth{1'b1}}; // -1 + Y_exp[23] = {bitwidth{1'b0}}; // 0 (False) + flags_exp[23] = {2'b01}; // ~Cout, Overflow + + ops[24] = 4'b1011; // uslt: 1 < 2 + A_in[24] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[24] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + Y_exp[24] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True) + flags_exp[24] = {2'b00}; // ~Cout, ~Overflow + + ops[25] = 4'b1011; // uslt: 2 < 1 + A_in[25] = {{(bitwidth-2){1'b0}}, 2'b10}; // 2 + B_in[25] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[25] = {bitwidth{1'b0}}; // 0 (False) + flags_exp[25] = {2'b10}; // Cout, ~Overflow + + ops[26] = 4'b1011; // uslt: 1 < UINTMAX + A_in[26] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + B_in[26] = {bitwidth{1'b1}}; // UINTMAX + Y_exp[26] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 (True) + flags_exp[26] = {2'b00}; // ~Cout, ~Overflow + + ops[27] = 4'b1011; // uslt: UINTMAX < 1 + A_in[27] = {bitwidth{1'b1}}; // UINTMAX + B_in[27] = {{(bitwidth-1){1'b0}}, 1'b1}; // 1 + Y_exp[27] = {bitwidth{1'b0}}; // 0 (False) + flags_exp[27] = {2'b10}; // Cout, ~Overflow + + error_count = 0; + $display("Beginning ALU tests"); + for (integer N = 0; N < $size(ops); ++N) begin + op_in = ops[N]; + A_in = A_cases[N]; + B_in = B_cases[N]; + #1; + if (Y_out != Y_exp[N]) begin + $display("\t\x1b[38;5;9m[%0d] ALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", N, op_in, flags_out, Y_out, flags_exp[N], Y_exp[N]); + error_count = error_count + 1; + end + end + + if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count); + end +endmodule \ No newline at end of file diff --git a/ModelSim/asu.sv b/ModelSim/asu.sv index 498faad..5b0440e 100644 --- a/ModelSim/asu.sv +++ b/ModelSim/asu.sv @@ -1,3 +1,6 @@ +`ifndef ASU_H_SV +`define ASU_H_SV + module asu #(parameter width = 2)( input logic [0:0] op, input logic[2**width-1:0] A, input logic[2**width-1:0] B, @@ -7,7 +10,8 @@ module asu #(parameter width = 2)( always_comb begin // A + (sub) ? B : -B // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis - operand = (B ^ {(2**width){op}}); + //operand = (B ^ {(2**width){op}}); + operand = op == 1'b0 ? B : ~B; {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op}; end @@ -15,3 +19,4 @@ module asu #(parameter width = 2)( // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1]; endmodule +`endif \ No newline at end of file diff --git a/ModelSim/asu_tb.sv b/ModelSim/asu_tb.sv index 63069d5..e0285fb 100644 --- a/ModelSim/asu_tb.sv +++ b/ModelSim/asu_tb.sv @@ -1,6 +1,6 @@ `include "asu.sv" -module asu_tb #(width=4)(); +module asu_tb #(width=8)(); logic [0:0] op; logic [width-1:0] A; logic [width-1:0] B; diff --git a/ModelSim/instruction_classifier.sv b/ModelSim/instruction_classifier.sv new file mode 100644 index 0000000..71454f1 --- /dev/null +++ b/ModelSim/instruction_classifier.sv @@ -0,0 +1,21 @@ +`ifndef INSTRUCTION_CLASSIFIER_H_SV +`define INSTRUCTION_CLASSIFIER_H_SV +module instruction_classifier(input logic[5:0] op, + output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J, + output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F, + output logic[0:0] M); + + always_comb begin + // Performs a rolling equals check + // Uses an AND mask to mask off bits we don't care about + // And a equals operator to perform a bitwise XNOR followed by a horizontal AND + R = ( (op & 6'b111111) == 6'b000000); + B1= ( (op & 6'b111111) == 6'b000001); + J = ( (op & 6'b111110) == 6'b000010); + B2= ( (op & 6'b111100) == 6'b000100); + I = ( (op & 6'b111000) == 6'b001000); + F = ( (op & 6'b110000) == 6'b010000); + M = ( (op & 6'b100000) == 6'b100000); + end +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/instruction_classifier_tb.sv b/ModelSim/instruction_classifier_tb.sv new file mode 100644 index 0000000..2ac93c3 --- /dev/null +++ b/ModelSim/instruction_classifier_tb.sv @@ -0,0 +1,52 @@ +`include "instruction_classifier.sv" +module instruction_classifier_tb(); + logic [5:0] op; + logic [6:0] C; + logic [5:0] ops[12]; + logic [6:0] C_exp[12]; + + instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]); + + integer error_count; + initial begin + ops[0] = 6'b000000; + C_exp[0] = 7'b0000001; + ops[1] = 6'b000001; + C_exp[1] = 7'b0000010; + ops[2] = 6'b000010; + C_exp[2] = 7'b0000100; + ops[3] = 6'b000100; + C_exp[3] = 7'b0001000; + ops[4] = 6'b001000; + C_exp[4] = 7'b0010000; + ops[5] = 6'b010000; + C_exp[5] = 7'b0100000; + ops[6] = 6'b100000; + C_exp[6] = 7'b1000000; + + ops[7] = 6'b000011; + C_exp[7] = 7'b0000100; + ops[8] = 6'b000101; + C_exp[8] = 7'b0001000; + ops[9] = 6'b001001; + C_exp[9] = 7'b0010000; + ops[10] = 6'b010001; + C_exp[10] = 7'b0100000; + ops[11] = 6'b100001; + C_exp[11] = 7'b1000000; + + error_count = 0; + $display("Beginning Instruction Classifier tests"); + for (integer N = 0; N < $size(ops); ++N) begin + op = ops[N]; + #1; + if (C != C_exp[N]) begin + $display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]); + error_count = error_count + 1; + end + end + if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count); + end + +endmodule \ No newline at end of file diff --git a/ModelSim/lu.sv b/ModelSim/lu.sv index cd2c34b..ce372a3 100644 --- a/ModelSim/lu.sv +++ b/ModelSim/lu.sv @@ -1,3 +1,5 @@ +`ifndef LU_H_SV +`define LU_H_SV module lu #(parameter width = 2) ( input logic [1:0] op, input logic [2**width-1:0] A, @@ -10,7 +12,8 @@ module lu #(parameter width = 2) ( 2'b01: Y = A | B; 2'b10: Y = A ^ B; 2'b11: Y = ~(A | B); - default: Y = '0; + default:Y = '0; endcase end -endmodule \ No newline at end of file +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/seven_seg.sv b/ModelSim/seven_seg.sv new file mode 100644 index 0000000..675f354 --- /dev/null +++ b/ModelSim/seven_seg.sv @@ -0,0 +1,26 @@ +`ifndef SEVEN_SEG_H_SV +`define SEVEN_SEG_H_SV +module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments); + always_comb begin + case (num) + 4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); + 4'b0001: segments = ~(8'b00001101); + 4'b0010: segments = ~(8'b10110111); + 4'b0011: segments = ~(8'b10011111); + 4'b0100: segments = ~(8'b11001101); + 4'b0101: segments = ~(8'b11011011); + 4'b0110: segments = ~(8'b11111011); + 4'b0111: segments = ~(8'b00001111); + 4'b1000: segments = ~(8'b11111111); + 4'b1001: segments = ~(8'b11001111); + 4'b1010: segments = ~(8'b11101111); + 4'b1011: segments = ~(8'b11111001); + 4'b1100: segments = ~(8'b01110011); + 4'b1101: segments = ~(8'b10111101); + 4'b1110: segments = ~(8'b11110011); + 4'b1111: segments = ~(8'b11100011); + default: segments = ~(8'bxxxxxxxx); + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/seven_seg_tb.sv b/ModelSim/seven_seg_tb.sv new file mode 100644 index 0000000..38e8dd0 --- /dev/null +++ b/ModelSim/seven_seg_tb.sv @@ -0,0 +1,68 @@ +`include "seven_seg.sv" + +module seven_seg_tb(); + logic [3:0] in_num; + logic [0:0] in_rbi_inv; + logic [7:0] out_segments; + logic [7:0] true_segments[17]; + + seven_seg dut(in_num, in_rbi_inv, out_segments); + + integer N; + integer i; + integer error_count; + initial begin + + // Initialise truth table + true_segments[0 ] = ~(8'b01111111); + true_segments[1 ] = ~(8'b00001101); + true_segments[2 ] = ~(8'b10110111); + true_segments[3 ] = ~(8'b10011111); + true_segments[4 ] = ~(8'b11001101); + true_segments[5 ] = ~(8'b11011011); + true_segments[6 ] = ~(8'b11111011); + true_segments[7 ] = ~(8'b00001111); + true_segments[8 ] = ~(8'b11111111); + true_segments[9 ] = ~(8'b11001111); + true_segments[10] = ~(8'b11101111); + true_segments[11] = ~(8'b11111001); + true_segments[12] = ~(8'b01110011); + true_segments[13] = ~(8'b10111101); + true_segments[14] = ~(8'b11110011); + true_segments[15] = ~(8'b11100011); + true_segments[16] = ~(8'b00000000); // Special case for RBI + + $display("Beginning seven-segment tests"); + + in_num = 4'd0; + in_rbi_inv = 1'b0; + error_count = 0; + #1; + if (out_segments !== true_segments[16]) begin + $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[16], out_segments); + error_count = error_count + 1; + end + for (N=1; N < 15; ++N) begin + in_num = in_num + 1; + #1; + if (out_segments !== true_segments[N]) begin + $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments); + error_count = error_count + 1; + end + end + + in_num = 4'd0; + in_rbi_inv = 1'b1; + for (N=0; N < 15; ++N) begin + #1; + if (out_segments !== true_segments[N]) begin + $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments); + error_count = error_count + 1; + end + in_num = in_num + 1; + end + + if (error_count == 0) $display("\x1b[38;5;10mAll seven-segment tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d seven-segment test(s) failing\x1b[m", error_count); + end +endmodule \ No newline at end of file diff --git a/ModelSim/shifter.sv b/ModelSim/shifter.sv new file mode 100644 index 0000000..7b84b49 --- /dev/null +++ b/ModelSim/shifter.sv @@ -0,0 +1,19 @@ +`ifndef SHIFTER_H_SV +`define SHIFTER_H_SV +module shifter #(width=8)(input logic [2:0] op, + input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B, + output logic[width-1:0] OUT_1); + + always_comb begin + case (op) + 3'b000: OUT_1 = A << C; + 3'b001: OUT_1 = A >> C; + 3'b011: OUT_1 = $signed(A) >>> C; + 3'b100: OUT_1 = A << B; + 3'b101: OUT_1 = A >> B; + 3'b111: OUT_1 = $signed(A) >>> B; + default:OUT_1 = A; + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/shifter_tb.sv b/ModelSim/shifter_tb.sv new file mode 100644 index 0000000..2a43af6 --- /dev/null +++ b/ModelSim/shifter_tb.sv @@ -0,0 +1,77 @@ +`include "shifter.sv" +module shifter_tb #(width=8)(); + logic [2:0] op; + logic [width-1:0] Y; + logic [width-1:0] A_in; + logic [$clog2(width)-1:0] B_in; + logic [width-1:0] C_in; + + logic [2:0] ops[6]; + logic [width-1:0] A[6]; + logic [$clog2(width)-1:0] B[6]; + logic [width-1:0] C[6]; + logic [width-1:0] Y_exp[6]; + + shifter #(width) dut(op, A_in,C_in,B_in,Y); + + integer error_count; + initial begin + // Test left shift by C + ops[0] = 3'b000; + A[0] = {{(width-1){1'b0}}, {1'b1}}; + C[0] = {{(width-1){1'b0}}, {1'b1}}; + B[0] = {width{1'b0}}; + Y_exp[0] = {{(width-2){1'b0}}, {2'b10}}; + + // Test left shift by B + ops[1] = 3'b100; + A[1] = {{(width-1){1'b0}}, {1'b1}}; + C[1] = {{(width-1){1'b0}}, {1'b1}}; + B[1] = {{($clog2(width)-2){1'b0}}, 2'b10}; + Y_exp[1] = {{(width-3){1'b0}}, {3'b100}}; + + // Test Logical right shift by C + ops[2] = 3'b001; + A[2] = {{(width-2){1'b0}}, {2'b10}}; + C[2] = {{(width-1){1'b0}}, {1'b1}}; + B[2] = {width{1'b0}}; + Y_exp[2] = {{(width-1){1'b0}}, {1'b1}}; + + // Test Logical right shift by B + ops[3] = 3'b101; + A[3] = {{(width-1){1'b0}}, {2'b10}}; + C[3] = {{(width-1){1'b0}}, {1'b1}}; + B[3] = {{($clog2(width)-2){1'b0}}, 2'b10}; + Y_exp[3] = {{(width-1){1'b0}}, {1'b0}}; + + // Test arithmetic shift right by C + ops[4] = 3'b011; + A[4] = {{(width-1){1'b1}}, 1'b0}; // -2 + C[4] = {{(width-1){1'b0}}, 1'b1}; // 1 + B[4] = {{(width-2){1'b0}}, 2'b10}; // 2 + Y_exp[4] = {width{1'b1}}; // -1 + + // Test arithmetic shift right by B + ops[5] = 3'b111; + A[5] = {{(width-2){1'b1}}, 2'b00}; // -4 + C[5] = {{(width-1){1'b0}}, 1'b1}; // 1 + B[5] = {{(width-2){1'b0}}, 2'b10}; // 2 + Y_exp[5] = {width{1'b1}}; // -1 + + error_count = 0; + $display("Beginning Shifter tests"); + for (integer N = 0; N < $size(ops); ++N) begin + op = ops[N]; + A_in = A[N]; + B_in = B[N]; + C_in = C[N]; + #1; + if (Y != Y_exp[N]) begin + $display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]); + error_count = error_count + 1; + end + end + if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m"); + else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count); + end +endmodule \ No newline at end of file diff --git a/ModelSim/tests.sv b/ModelSim/tests.sv new file mode 100644 index 0000000..88cba1d --- /dev/null +++ b/ModelSim/tests.sv @@ -0,0 +1,6 @@ +`include "tests/seven_seg_tb.sv" +`include "tests/lu_tb.sv" +`include "tests/asu_tb.sv" +`include "tests/instruction_classifier_tb.sv" +`include "tests/shifter_tb.sv" +`include "tests/alu_tb.sv" \ No newline at end of file diff --git a/ModelSim/transcript b/ModelSim/transcript index f93b766..815c8aa 100644 --- a/ModelSim/transcript +++ b/ModelSim/transcript @@ -1,15 +1,14 @@ -# Loading project Assignment_1_Q2 -# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini # Loading project Assignment_1_Q3 # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. # 2 compiles, 0 failed with no errors. vsim work.asu_tb # vsim work.asu_tb -# Start time: 15:16:49 on Sep 10,2026 +# Start time: 15:01:26 on Sep 15,2026 # Loading sv_std.std # Loading work.asu_tb # Loading work.asu +add wave -position end sim:/asu_tb/op add wave -position end sim:/asu_tb/A add wave -position end sim:/asu_tb/B add wave -position end sim:/asu_tb/C @@ -18,28 +17,125 @@ add wave -position end sim:/asu_tb/Cin run # Beginning ASU tests # All ASU tests passing -add wave -position end sim:/asu_tb/op +quit -sim +# End time: 15:03:03 on Sep 15,2026, Elapsed time: 0:01:37 +# Errors: 0, Warnings: 2 +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q4 +# Compile of alu.sv was successful. +# Compile of alu_tb.sv was successful. +# 2 compiles, 0 failed with no errors. +vsim work.alu_tb +# vsim work.alu_tb +# Start time: 15:04:11 on Sep 15,2026 +# Loading sv_std.std +# Loading work.alu_tb +# Loading work.alu +# Loading work.asu +# Loading work.lu +add wave -position end sim:/alu_tb/op_in +add wave -position end sim:/alu_tb/A_in +add wave -position end sim:/alu_tb/B_in +add wave -position end sim:/alu_tb/Y_out +add wave -position end sim:/alu_tb/flags_out +add wave -position end sim:/alu_tb/ops +run +# Beginning ALU tests +# All ALU tests passing +add wave -position end sim:/alu_tb/error_count run quit -sim -# End time: 15:19:15 on Sep 10,2026, Elapsed time: 0:02:26 +# End time: 15:05:53 on Sep 15,2026, Elapsed time: 0:01:42 # Errors: 0, Warnings: 5 -# Compile of asu.sv was successful. -# Compile of asu_tb.sv was successful. +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q5 +# Compile of shifter.sv was successful. +# Compile of shifter_tb.sv was successful. # 2 compiles, 0 failed with no errors. -vsim work.asu_tb -# vsim work.asu_tb -# Start time: 15:20:10 on Sep 10,2026 +vsim work.shifter_tb +# vsim work.shifter_tb +# Start time: 15:06:46 on Sep 15,2026 # Loading sv_std.std -# Loading work.asu_tb -# Loading work.asu -add wave -position end sim:/asu_tb/A -add wave -position end sim:/asu_tb/B -add wave -position end sim:/asu_tb/C -add wave -position end sim:/asu_tb/Cout -add wave -position end sim:/asu_tb/Cin -add wave -position end sim:/asu_tb/op +# Loading work.shifter_tb +# Loading work.shifter +add wave -position end sim:/shifter_tb/op +add wave -position end sim:/shifter_tb/Y +add wave -position end sim:/shifter_tb/A_in +add wave -position end sim:/shifter_tb/B_in +add wave -position end sim:/shifter_tb/C_in +add wave -position end sim:/shifter_tb/A +add wave -position end sim:/shifter_tb/B +add wave -position end sim:/shifter_tb/C +add wave -position end sim:/shifter_tb/Y +add wave -position end sim:/shifter_tb/op run -# Beginning ASU tests -# All ASU tests passing -# End time: 15:24:25 on Sep 10,2026, Elapsed time: 0:04:15 -# Errors: 0, Warnings: 2 +# Beginning Shifter tests +# All Shifter tests passing +quit -sim +# End time: 15:07:54 on Sep 15,2026, Elapsed time: 0:01:08 +# Errors: 0, Warnings: 5 +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q6 +# Compile of instruction_classifier.sv was successful. +# Compile of instruction_classifier_tb.sv was successful. +# 2 compiles, 0 failed with no errors. +vsim work.instruction_classifier_tb +# vsim work.instruction_classifier_tb +# Start time: 15:08:34 on Sep 15,2026 +# Loading sv_std.std +# Loading work.instruction_classifier_tb +# Loading work.instruction_classifier +add wave -position end sim:/instruction_classifier_tb/op +add wave -position end sim:/instruction_classifier_tb/C +add wave -position end sim:/instruction_classifier_tb/ops +run +# Beginning Instruction Classifier tests +# All Instruction Classifier tests passing +quit -sim +# End time: 15:09:45 on Sep 15,2026, Elapsed time: 0:01:11 +# Errors: 0, Warnings: 5 +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q1 +# Compile of seven_seg.sv was successful. +# Compile of seven_seg_tb.sv was successful. +# 2 compiles, 0 failed with no errors. +vsim work.seven_seg_tb +# vsim work.seven_seg_tb +# Start time: 15:10:28 on Sep 15,2026 +# Loading sv_std.std +# Loading work.seven_seg_tb +# Loading work.seven_seg +add wave -position end sim:/seven_seg_tb/in_rbi_inv +add wave -position end sim:/seven_seg_tb/out_segments +add wave -position end sim:/seven_seg_tb/true_segments +add wave -position end sim:/seven_seg_tb/N +add wave -position end sim:/seven_seg_tb/i +add wave -position 1 sim:/seven_seg_tb/in_num +run +# Beginning seven-segment tests +# All seven-segment tests passing +quit -sim +# End time: 15:12:28 on Sep 15,2026, Elapsed time: 0:02:00 +# Errors: 0, Warnings: 5 +project open /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/Assignment_1_Q2 +# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini +# Loading project Assignment_1_Q2 +# Compile of lu.sv was successful. +# Compile of lu_tb.sv was successful. +# 2 compiles, 0 failed with no errors. +vsim work.lu_tb +# vsim work.lu_tb +# Start time: 15:13:40 on Sep 15,2026 +# Loading sv_std.std +# Loading work.lu_tb +# Loading work.lu +add wave -position end sim:/lu_tb/op +add wave -position end sim:/lu_tb/A +add wave -position end sim:/lu_tb/B +add wave -position end sim:/lu_tb/C +run +# Beginning LU tests +# All LU tests passing +quit -sim +# End time: 15:14:33 on Sep 15,2026, Elapsed time: 0:00:53 +# Errors: 0, Warnings: 3 diff --git a/ModelSim/vsim.wlf b/ModelSim/vsim.wlf index aa35809..2ca9e22 100644 Binary files a/ModelSim/vsim.wlf and b/ModelSim/vsim.wlf differ diff --git a/ModelSim/work/_info b/ModelSim/work/_info index d252026..e031d68 100644 --- a/ModelSim/work/_info +++ b/ModelSim/work/_info @@ -9,84 +9,184 @@ z2 !i10f 100 cModel Technology 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-reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv| +!i113 1 +R10 +R11 vlu_tb R0 -R12 +R17 !i10b 1 !s100 AE_liX6DCD[3>b;K6Wgf72 R2 @@ -94,18 +194,118 @@ IC?h=m;SY77_D:GA0FRi`]oD>7BNB:Rd?3 +R2 +IedFU7?nB5ZOibY?bC8=L41 +R3 +S1 +R4 +R5 +8seven_seg.sv +Fseven_seg.sv +!i122 24 +L0 3 23 +R6 +r1 +!s85 0 +31 +Z23 !s108 1789449021.000000 +Z24 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv| +Z25 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv| +!i113 1 +R10 +R11 +vseven_seg_tb +R0 +R22 +!i10b 1 +!s100 jPijM2]zTRBV8TFdD?Q`I1 +R2 +I_mSF@Md^k^GhHm5;W4U_=0 +R3 +S1 +R4 +w1788418794 +8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv +!i122 24 +L0 3 66 +R6 +r1 +!s85 0 +31 +R23 +R24 +R25 +!i113 1 +R10 +R11 +vshifter +R0 +Z26 !s110 1789448794 +!i10b 1 +!s100 operand[0].IN0 -op[0] => operand[1].IN0 -op[0] => operand[2].IN0 -op[0] => operand[3].IN0 +op[0] => operand[3].OUTPUTSELECT +op[0] => operand[2].OUTPUTSELECT +op[0] => operand[1].OUTPUTSELECT +op[0] => operand[0].OUTPUTSELECT op[0] => _.DATAB A[0] => _.DATAD A[1] => _.DATAD A[2] => _.DATAD A[3] => OUT_CIN.IN1 A[3] => _.DATAD -B[0] => operand[0].IN1 -B[1] => operand[1].IN1 -B[2] => operand[2].IN1 -B[3] => operand[3].IN1 -OUT_1[0] << _.SUM_OUT -OUT_1[1] << _.SUM_OUT -OUT_1[2] << _.SUM_OUT -OUT_1[3] << _.SUM_OUT -COUT[0] << _.SUM_OUT -OUT_CIN[0] << OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE +B[0] => operand[0].DATAB +B[0] => operand[0].DATAA +B[1] => operand[1].DATAB +B[1] => operand[1].DATAA +B[2] => operand[2].DATAB +B[2] => operand[2].DATAA +B[3] => operand[3].DATAB +B[3] => operand[3].DATAA +OUT_1[0] <= _.SUM_OUT +OUT_1[1] <= _.SUM_OUT +OUT_1[2] <= _.SUM_OUT +OUT_1[3] <= _.SUM_OUT +COUT[0] <= _.SUM_OUT +OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q3/db/asu.hif b/Quartus/A1_Q3/db/asu.hif index 71d7ecf..e50e045 100644 Binary files a/Quartus/A1_Q3/db/asu.hif and b/Quartus/A1_Q3/db/asu.hif differ diff --git a/Quartus/A1_Q3/db/asu.map.bpm b/Quartus/A1_Q3/db/asu.map.bpm index 4a6f89a..2582fb0 100644 Binary files a/Quartus/A1_Q3/db/asu.map.bpm and b/Quartus/A1_Q3/db/asu.map.bpm differ diff --git a/Quartus/A1_Q3/db/asu.map.cdb b/Quartus/A1_Q3/db/asu.map.cdb index 9ef171d..790b22d 100644 Binary files a/Quartus/A1_Q3/db/asu.map.cdb and b/Quartus/A1_Q3/db/asu.map.cdb differ diff --git a/Quartus/A1_Q3/db/asu.map.hdb b/Quartus/A1_Q3/db/asu.map.hdb index 76849c6..e8874eb 100644 Binary files a/Quartus/A1_Q3/db/asu.map.hdb and b/Quartus/A1_Q3/db/asu.map.hdb differ diff --git a/Quartus/A1_Q3/db/asu.map.qmsg b/Quartus/A1_Q3/db/asu.map.qmsg index 081f64b..709b9ed 100644 --- a/Quartus/A1_Q3/db/asu.map.qmsg +++ b/Quartus/A1_Q3/db/asu.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789012844961 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789012844962 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 10 14:00:44 2026 " "Processing started: Thu Sep 10 14:00:44 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789012844962 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789012844962 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789012844962 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789012845613 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789012845613 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789012859944 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789012859944 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789012860119 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789012861121 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789012861608 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789012861608 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789012861731 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789012861731 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789012861731 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789012861731 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789012861742 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 10 14:01:01 2026 " "Processing ended: Thu Sep 10 14:01:01 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789012861742 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789012861742 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789012861742 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789012861742 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430407159 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430407160 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:00:06 2026 " "Processing started: Tue Sep 15 10:00:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430407160 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430407160 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430407160 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430407694 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430407694 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430420346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430420346 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "asu " "Elaborating entity \"asu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430420541 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430421709 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430422213 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430422213 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430422350 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430422350 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430422350 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430422350 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:00:22 2026 " "Processing ended: Tue Sep 15 10:00:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430422361 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430422361 ""} diff --git a/Quartus/A1_Q3/db/asu.map.rdb b/Quartus/A1_Q3/db/asu.map.rdb index fc6877b..6b4c376 100644 Binary files a/Quartus/A1_Q3/db/asu.map.rdb and b/Quartus/A1_Q3/db/asu.map.rdb differ diff --git a/Quartus/A1_Q3/db/asu.map_bb.cdb b/Quartus/A1_Q3/db/asu.map_bb.cdb index c68ca3e..f2f417b 100644 Binary files a/Quartus/A1_Q3/db/asu.map_bb.cdb and b/Quartus/A1_Q3/db/asu.map_bb.cdb differ diff --git a/Quartus/A1_Q3/db/asu.map_bb.hdb b/Quartus/A1_Q3/db/asu.map_bb.hdb index 6cc28fa..7a8990c 100644 Binary files a/Quartus/A1_Q3/db/asu.map_bb.hdb and b/Quartus/A1_Q3/db/asu.map_bb.hdb differ diff --git a/Quartus/A1_Q3/db/asu.pre_map.hdb b/Quartus/A1_Q3/db/asu.pre_map.hdb index 57b4054..7c431bb 100644 Binary files a/Quartus/A1_Q3/db/asu.pre_map.hdb and b/Quartus/A1_Q3/db/asu.pre_map.hdb differ diff --git a/Quartus/A1_Q3/db/asu.rtlv.hdb b/Quartus/A1_Q3/db/asu.rtlv.hdb index e2d4aaa..03a689b 100644 Binary files a/Quartus/A1_Q3/db/asu.rtlv.hdb and b/Quartus/A1_Q3/db/asu.rtlv.hdb differ diff --git a/Quartus/A1_Q3/db/asu.rtlv_sg.cdb b/Quartus/A1_Q3/db/asu.rtlv_sg.cdb index 3af045b..e8fd017 100644 Binary files a/Quartus/A1_Q3/db/asu.rtlv_sg.cdb and b/Quartus/A1_Q3/db/asu.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q3/db/asu.sta.qmsg b/Quartus/A1_Q3/db/asu.sta.qmsg index f9c00d4..96c4db1 100644 --- a/Quartus/A1_Q3/db/asu.sta.qmsg +++ b/Quartus/A1_Q3/db/asu.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789012911907 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789012911907 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 10 14:01:51 2026 " "Processing started: Thu Sep 10 14:01:51 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789012911907 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789012911907 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789012911908 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789012912004 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789012912522 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789012912522 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012912593 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012912593 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789012913211 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012913211 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789012913212 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789012913212 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789012913212 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789012913212 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789012913213 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789012913217 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789012913218 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913219 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913223 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913224 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913225 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913226 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012913226 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789012913229 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789012913270 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789012914699 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012914844 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789012914844 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789012914844 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789012914845 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914846 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914848 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914850 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914853 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914855 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012914856 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789012914859 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789012915233 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789012916069 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012916121 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789012916121 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789012916121 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789012916121 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916123 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916123 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916124 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916125 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916126 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789012916128 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789012916287 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789012916288 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789012916288 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789012916288 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916289 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916290 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916291 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916291 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789012916292 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789012918968 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789012918968 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "780 " "Peak virtual memory: 780 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789012919021 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 10 14:01:59 2026 " "Processing ended: Thu Sep 10 14:01:59 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789012919021 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789012919021 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789012919021 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789012919021 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430476722 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430476723 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:01:16 2026 " "Processing started: Tue Sep 15 10:01:16 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430476723 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430476723 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q3 -c asu " "Command: quartus_sta A1_Q3 -c asu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430476723 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430476825 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430477740 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430477740 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430477834 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430477834 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "asu.sdc " "Synopsys Design Constraints File file not found: 'asu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430478816 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430478817 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430478818 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430478818 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430478819 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430478819 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430478821 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430478830 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430478831 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478832 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478842 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478843 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478846 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430478847 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430478852 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430478922 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430481155 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430481259 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430481259 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430481260 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430481260 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481262 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481265 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481267 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481268 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481269 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430481270 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430481272 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430481594 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430482658 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430482705 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430482705 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430482706 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430482706 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482707 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482708 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482709 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482710 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482710 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430482712 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430482932 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430482933 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482934 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482936 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482937 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482938 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430482939 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430484833 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430484833 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "785 " "Peak virtual memory: 785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:01:24 2026 " "Processing ended: Tue Sep 15 10:01:24 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430484859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430484859 ""} diff --git a/Quartus/A1_Q3/db/asu.sta.rdb b/Quartus/A1_Q3/db/asu.sta.rdb index 64d4edd..8f83a98 100644 Binary files a/Quartus/A1_Q3/db/asu.sta.rdb and b/Quartus/A1_Q3/db/asu.sta.rdb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb index 5acedca..9f981ce 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb index a2613d0..f4bb6cb 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb index 8bce0b9..67154de 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb index 9250331..d969c88 100644 Binary files a/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q3/db/asu.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q3/db/asu.tmw_info b/Quartus/A1_Q3/db/asu.tmw_info index 8ca163e..6784514 100644 --- a/Quartus/A1_Q3/db/asu.tmw_info +++ b/Quartus/A1_Q3/db/asu.tmw_info @@ -1,7 +1,7 @@ -start_full_compilation:s:00:01:20 -start_analysis_synthesis:s:00:00:19-start_full_compilation +start_full_compilation:s:00:01:24 +start_analysis_synthesis:s:00:00:18-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:39-start_full_compilation -start_assembler:s:00:00:09-start_full_compilation -start_timing_analyzer:s:00:00:09-start_full_compilation +start_fitter:s:00:00:41-start_full_compilation +start_assembler:s:00:00:11-start_full_compilation +start_timing_analyzer:s:00:00:10-start_full_compilation start_eda_netlist_writer:s:00:00:04-start_full_compilation diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb index 54fb481..eabbe59 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb index 226ebdb..dc33447 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb index cbf535e..ec27649 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb index 5c97450..c24af12 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb index e35ae7d..89ef368 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi index 16bb15d..68c02fa 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.dpi differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb index 9e00fb6..f98b030 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb index d81e3fe..79fb0c7 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb index 24daea9..e9567a2 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.root_partition.map.hdb differ diff --git a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb index d0d1412..9a60dd0 100644 Binary files a/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb and b/Quartus/A1_Q3/incremental_db/compiled_partitions/asu.rrp.hdb differ diff --git a/Quartus/A1_Q3/output_files/asu.asm.rpt b/Quartus/A1_Q3/output_files/asu.asm.rpt index c72cc49..ccbf8fe 100644 --- a/Quartus/A1_Q3/output_files/asu.asm.rpt +++ b/Quartus/A1_Q3/output_files/asu.asm.rpt @@ -1,5 +1,5 @@ Assembler report for asu -Thu Sep 10 14:01:49 2026 +Tue Sep 15 10:01:14 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Sep 10 14:01:49 2026 ; +; Assembler Status ; Successful - Tue Sep 15 10:01:14 2026 ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; @@ -78,14 +78,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 10 14:01:42 2026 + Info: Processing started: Tue Sep 15 10:01:06 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 511 megabytes - Info: Processing ended: Thu Sep 10 14:01:49 2026 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:07 + Info: Peak virtual memory: 521 megabytes + Info: Processing ended: Tue Sep 15 10:01:14 2026 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:08 diff --git a/Quartus/A1_Q3/output_files/asu.done b/Quartus/A1_Q3/output_files/asu.done index 596b059..590915f 100644 --- a/Quartus/A1_Q3/output_files/asu.done +++ b/Quartus/A1_Q3/output_files/asu.done @@ -1 +1 @@ -Thu Sep 10 14:02:03 2026 +Tue Sep 15 10:01:29 2026 diff --git a/Quartus/A1_Q3/output_files/asu.eda.rpt b/Quartus/A1_Q3/output_files/asu.eda.rpt index 357f85b..48be722 100644 --- a/Quartus/A1_Q3/output_files/asu.eda.rpt +++ b/Quartus/A1_Q3/output_files/asu.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for asu -Thu Sep 10 14:02:02 2026 +Tue Sep 15 10:01:28 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Thu Sep 10 14:02:02 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:01:28 2026 ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; ; Family ; Cyclone V ; @@ -81,14 +81,14 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 10 14:02:01 2026 + Info: Processing started: Tue Sep 15 10:01:26 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file asu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q3/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 658 megabytes - Info: Processing ended: Thu Sep 10 14:02:03 2026 + Info: Processing ended: Tue Sep 15 10:01:28 2026 Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/Quartus/A1_Q3/output_files/asu.fit.rpt b/Quartus/A1_Q3/output_files/asu.fit.rpt index 627e3be..f1c7b12 100644 --- a/Quartus/A1_Q3/output_files/asu.fit.rpt +++ b/Quartus/A1_Q3/output_files/asu.fit.rpt @@ -1,5 +1,5 @@ Fitter report for asu -Thu Sep 10 14:01:39 2026 +Tue Sep 15 10:01:03 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -58,7 +58,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Sep 10 14:01:39 2026 ; +; Fitter Status ; Successful - Tue Sep 15 10:01:03 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; @@ -1376,9 +1376,9 @@ Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1387 megabytes - Info: Processing ended: Thu Sep 10 14:01:40 2026 - Info: Elapsed time: 00:00:37 - Info: Total CPU time (on all processors): 00:00:51 + Info: Peak virtual memory: 1380 megabytes + Info: Processing ended: Tue Sep 15 10:01:04 2026 + Info: Elapsed time: 00:00:41 + Info: Total CPU time (on all processors): 00:00:52 diff --git a/Quartus/A1_Q3/output_files/asu.fit.summary b/Quartus/A1_Q3/output_files/asu.fit.summary index a0a7a3b..6475df8 100644 --- a/Quartus/A1_Q3/output_files/asu.fit.summary +++ b/Quartus/A1_Q3/output_files/asu.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Thu Sep 10 14:01:39 2026 +Fitter Status : Successful - Tue Sep 15 10:01:03 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : asu Top-level Entity Name : asu diff --git a/Quartus/A1_Q3/output_files/asu.flow.rpt b/Quartus/A1_Q3/output_files/asu.flow.rpt index d537f7c..4ff6be8 100644 --- a/Quartus/A1_Q3/output_files/asu.flow.rpt +++ b/Quartus/A1_Q3/output_files/asu.flow.rpt @@ -1,5 +1,5 @@ Flow report for asu -Thu Sep 10 14:02:02 2026 +Tue Sep 15 10:01:28 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Sep 10 14:02:02 2026 ; +; Flow Status ; Successful - Tue Sep 15 10:01:28 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/10/2026 14:00:45 ; +; Start date & time ; 09/15/2026 10:00:07 ; ; Main task ; Compilation ; ; Revision Name ; asu ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 7209694329158.178901284503666 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 253029099468756.178943040705122 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 419 MB ; 00:00:32 ; -; Fitter ; 00:00:36 ; 1.0 ; 1387 MB ; 00:00:50 ; -; Assembler ; 00:00:07 ; 1.0 ; 511 MB ; 00:00:07 ; -; Timing Analyzer ; 00:00:07 ; 1.0 ; 780 MB ; 00:00:07 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; -; Total ; 00:01:08 ; -- ; -- ; 00:01:37 ; +; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 422 MB ; 00:00:32 ; +; Fitter ; 00:00:40 ; 1.0 ; 1380 MB ; 00:00:51 ; +; Assembler ; 00:00:08 ; 1.0 ; 521 MB ; 00:00:08 ; +; Timing Analyzer ; 00:00:08 ; 1.0 ; 785 MB ; 00:00:08 ; +; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ; +; Total ; 00:01:14 ; -- ; -- ; 00:01:40 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q3/output_files/asu.map.rpt b/Quartus/A1_Q3/output_files/asu.map.rpt index 2cc9d84..05078c7 100644 --- a/Quartus/A1_Q3/output_files/asu.map.rpt +++ b/Quartus/A1_Q3/output_files/asu.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for asu -Thu Sep 10 14:01:01 2026 +Tue Sep 15 10:00:22 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -44,7 +44,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Sep 10 14:01:01 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:00:22 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; asu ; ; Top-level Entity Name ; asu ; @@ -271,12 +271,12 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 10 14:00:44 2026 + Info: Processing started: Tue Sep 15 10:00:06 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv - Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1 + Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4 Info (12127): Elaborating entity "asu" for the top level hierarchy Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" @@ -286,9 +286,9 @@ Info (21057): Implemented 21 device resources after synthesis - the final resour Info (21059): Implemented 6 output pins Info (21061): Implemented 6 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 436 megabytes - Info: Processing ended: Thu Sep 10 14:01:01 2026 - Info: Elapsed time: 00:00:17 - Info: Total CPU time (on all processors): 00:00:33 + Info: Peak virtual memory: 439 megabytes + Info: Processing ended: Tue Sep 15 10:00:22 2026 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:32 diff --git a/Quartus/A1_Q3/output_files/asu.map.summary b/Quartus/A1_Q3/output_files/asu.map.summary index 408c117..efc3915 100644 --- a/Quartus/A1_Q3/output_files/asu.map.summary +++ b/Quartus/A1_Q3/output_files/asu.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Thu Sep 10 14:01:01 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 10:00:22 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : asu Top-level Entity Name : asu diff --git a/Quartus/A1_Q3/output_files/asu.sof b/Quartus/A1_Q3/output_files/asu.sof index b380dc6..8371371 100644 Binary files a/Quartus/A1_Q3/output_files/asu.sof and b/Quartus/A1_Q3/output_files/asu.sof differ diff --git a/Quartus/A1_Q3/output_files/asu.sta.rpt b/Quartus/A1_Q3/output_files/asu.sta.rpt index 74d0b3c..f048c6e 100644 --- a/Quartus/A1_Q3/output_files/asu.sta.rpt +++ b/Quartus/A1_Q3/output_files/asu.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for asu -Thu Sep 10 14:01:59 2026 +Tue Sep 15 10:01:24 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -98,12 +98,12 @@ on the Quartus Prime software download page. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.02 ; +; Average used ; 1.04 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.9% ; +; Processor 2 ; 3.8% ; +----------------------------+-------------+ @@ -472,7 +472,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 10 14:01:51 2026 + Info: Processing started: Tue Sep 15 10:01:16 2026 Info: Command: quartus_sta A1_Q3 -c asu Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -532,9 +532,9 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 780 megabytes - Info: Processing ended: Thu Sep 10 14:01:59 2026 + Info: Peak virtual memory: 785 megabytes + Info: Processing ended: Tue Sep 15 10:01:24 2026 Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:07 + Info: Total CPU time (on all processors): 00:00:08 diff --git a/Quartus/A1_Q3/simulation/questa/asu.svo b/Quartus/A1_Q3/simulation/questa/asu.svo index 4918fa2..66cd20e 100644 --- a/Quartus/A1_Q3/simulation/questa/asu.svo +++ b/Quartus/A1_Q3/simulation/questa/asu.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/10/2026 14:02:02" +// DATE "09/15/2026 10:01:28" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -36,12 +36,12 @@ module asu ( OUT_1, COUT, OUT_CIN); -input [0:0] op; -input [3:0] A; -input [3:0] B; -output [3:0] OUT_1; -output [0:0] COUT; -output [0:0] OUT_CIN; +input logic [0:0] op ; +input logic [3:0] A ; +input logic [3:0] B ; +output logic [3:0] OUT_1 ; +output logic [0:0] COUT ; +output logic [0:0] OUT_CIN ; // Design Ports Information // OUT_1[0] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default diff --git a/Quartus/A1_Q4/asu.sv b/Quartus/A1_Q4/asu.sv new file mode 100644 index 0000000..5b0440e --- /dev/null +++ b/Quartus/A1_Q4/asu.sv @@ -0,0 +1,22 @@ +`ifndef ASU_H_SV +`define ASU_H_SV + +module asu #(parameter width = 2)( + input logic [0:0] op, + input logic[2**width-1:0] A, input logic[2**width-1:0] B, + output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN); + + logic [2**width-1:0] operand; + always_comb begin + // A + (sub) ? B : -B + // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis + //operand = (B ^ {(2**width){op}}); + operand = op == 1'b0 ? B : ~B; + {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op}; + end + + // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported? + // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture + assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1]; +endmodule +`endif \ No newline at end of file diff --git a/Quartus/A1_Q4/db/alu.(0).cnf.cdb b/Quartus/A1_Q4/db/alu.(0).cnf.cdb index 969b0d7..c3e3f20 100644 Binary files a/Quartus/A1_Q4/db/alu.(0).cnf.cdb and b/Quartus/A1_Q4/db/alu.(0).cnf.cdb differ diff --git a/Quartus/A1_Q4/db/alu.(0).cnf.hdb b/Quartus/A1_Q4/db/alu.(0).cnf.hdb index fb72d0f..82f6b47 100644 Binary files a/Quartus/A1_Q4/db/alu.(0).cnf.hdb and b/Quartus/A1_Q4/db/alu.(0).cnf.hdb differ diff --git a/Quartus/A1_Q4/db/alu.(1).cnf.cdb b/Quartus/A1_Q4/db/alu.(1).cnf.cdb index 6bfe5d9..8c5b1ff 100644 Binary files a/Quartus/A1_Q4/db/alu.(1).cnf.cdb and b/Quartus/A1_Q4/db/alu.(1).cnf.cdb differ diff --git a/Quartus/A1_Q4/db/alu.(1).cnf.hdb b/Quartus/A1_Q4/db/alu.(1).cnf.hdb index 49b534a..059dba1 100644 Binary files a/Quartus/A1_Q4/db/alu.(1).cnf.hdb and b/Quartus/A1_Q4/db/alu.(1).cnf.hdb differ diff --git a/Quartus/A1_Q4/db/alu.(2).cnf.cdb b/Quartus/A1_Q4/db/alu.(2).cnf.cdb index f9b1585..8dce792 100644 Binary files a/Quartus/A1_Q4/db/alu.(2).cnf.cdb and b/Quartus/A1_Q4/db/alu.(2).cnf.cdb differ diff --git a/Quartus/A1_Q4/db/alu.(2).cnf.hdb b/Quartus/A1_Q4/db/alu.(2).cnf.hdb index 2bf94bc..80bab6d 100644 Binary files a/Quartus/A1_Q4/db/alu.(2).cnf.hdb and b/Quartus/A1_Q4/db/alu.(2).cnf.hdb differ diff --git a/Quartus/A1_Q4/db/alu.asm.qmsg b/Quartus/A1_Q4/db/alu.asm.qmsg index d224183..f9ebb7d 100644 --- a/Quartus/A1_Q4/db/alu.asm.qmsg +++ b/Quartus/A1_Q4/db/alu.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927773356 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927773357 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:53 2026 " "Processing started: Wed Sep 9 14:22:53 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927773357 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788927773357 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788927773357 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788927774010 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788927778263 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "516 " "Peak virtual memory: 516 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:58 2026 " "Processing ended: Wed Sep 9 14:22:58 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788927778461 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430641404 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:01 2026 " "Processing started: Tue Sep 15 10:04:01 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430642068 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430646380 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:06 2026 " "Processing ended: Tue Sep 15 10:04:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430646577 ""} diff --git a/Quartus/A1_Q4/db/alu.asm.rdb b/Quartus/A1_Q4/db/alu.asm.rdb index 6efb1a4..7485375 100644 Binary files a/Quartus/A1_Q4/db/alu.asm.rdb and b/Quartus/A1_Q4/db/alu.asm.rdb differ diff --git a/Quartus/A1_Q4/db/alu.cmp.bpm b/Quartus/A1_Q4/db/alu.cmp.bpm index e796067..ab43975 100644 Binary files a/Quartus/A1_Q4/db/alu.cmp.bpm and b/Quartus/A1_Q4/db/alu.cmp.bpm differ diff --git a/Quartus/A1_Q4/db/alu.cmp.cdb b/Quartus/A1_Q4/db/alu.cmp.cdb index 6101efb..4efdde2 100644 Binary files a/Quartus/A1_Q4/db/alu.cmp.cdb and b/Quartus/A1_Q4/db/alu.cmp.cdb differ diff --git a/Quartus/A1_Q4/db/alu.cmp.hdb b/Quartus/A1_Q4/db/alu.cmp.hdb index e9bb367..2ee8e7a 100644 Binary files a/Quartus/A1_Q4/db/alu.cmp.hdb and b/Quartus/A1_Q4/db/alu.cmp.hdb differ diff --git a/Quartus/A1_Q4/db/alu.cmp.idb b/Quartus/A1_Q4/db/alu.cmp.idb index 09afed7..2b7d7a5 100644 Binary files a/Quartus/A1_Q4/db/alu.cmp.idb and b/Quartus/A1_Q4/db/alu.cmp.idb differ diff --git a/Quartus/A1_Q4/db/alu.cmp.logdb b/Quartus/A1_Q4/db/alu.cmp.logdb index d6d1ce4..90ff09e 100644 --- a/Quartus/A1_Q4/db/alu.cmp.logdb +++ b/Quartus/A1_Q4/db/alu.cmp.logdb @@ -33,24 +33,24 @@ IO_RULES_MATRIX,Total Pass,0;0;0;0;0;18;0;0;0;0;0;0;0;6;0;0;0;0;6;0;0;0;0;6;0;18 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, IO_RULES_MATRIX,Total Inapplicable,18;18;18;18;18;0;18;18;18;18;18;18;18;12;18;18;18;18;12;18;18;18;18;12;18;0;0;18, IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, -IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,flags[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_MATRIX,flags[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, IO_RULES_SUMMARY,Total I/O Rules,28, IO_RULES_SUMMARY,Number of I/O Rules Passed,6, IO_RULES_SUMMARY,Number of I/O Rules Failed,0, diff --git a/Quartus/A1_Q4/db/alu.cmp.rdb b/Quartus/A1_Q4/db/alu.cmp.rdb index af4b2d3..3fe92a2 100644 Binary files a/Quartus/A1_Q4/db/alu.cmp.rdb and b/Quartus/A1_Q4/db/alu.cmp.rdb differ diff --git a/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ff_0c_fast.hsd index b19b6d1..5b25938 100644 Binary files a/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ff_0c_fast.hsd and b/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ii_85c_slow.hsd index 118df22..0778662 100644 Binary files a/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ii_85c_slow.hsd and b/Quartus/A1_Q4/db/alu.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q4/db/alu.db_info b/Quartus/A1_Q4/db/alu.db_info index c986234..cfe4bf5 100644 --- a/Quartus/A1_Q4/db/alu.db_info +++ b/Quartus/A1_Q4/db/alu.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Thu Sep 10 14:53:57 2026 +Creation_Time = Tue Sep 15 10:02:02 2026 diff --git a/Quartus/A1_Q4/db/alu.eda.qmsg b/Quartus/A1_Q4/db/alu.eda.qmsg index cbdf7e8..26dde4c 100644 --- a/Quartus/A1_Q4/db/alu.eda.qmsg +++ b/Quartus/A1_Q4/db/alu.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927786173 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927786174 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:23:05 2026 " "Processing started: Wed Sep 9 14:23:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927786174 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786174 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786174 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788927786909 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788927786950 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:23:06 2026 " "Processing ended: Wed Sep 9 14:23:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786981 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430654884 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:14 2026 " "Processing started: Tue Sep 15 10:04:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430655640 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430655696 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:15 2026 " "Processing ended: Tue Sep 15 10:04:15 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430655731 ""} diff --git a/Quartus/A1_Q4/db/alu.fit.qmsg b/Quartus/A1_Q4/db/alu.fit.qmsg index 015cc89..96d1983 100644 --- a/Quartus/A1_Q4/db/alu.fit.qmsg +++ b/Quartus/A1_Q4/db/alu.fit.qmsg @@ -1,44 +1,44 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788927745146 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788927745146 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788927745151 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927745220 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927745220 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788927745630 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788927745657 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788927745702 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1788927745949 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788927752374 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927752460 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788927752462 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788927752463 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788927752464 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788927752464 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927752477 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788927758260 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788927758261 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788927758261 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788927758262 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788927758262 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788927758262 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788927758263 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788927758265 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788927758304 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927758698 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788927758958 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788927759227 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927759228 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788927759766 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788927765042 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788927765042 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788927765181 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788927765181 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788927765181 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927765183 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788927767056 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927767089 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927767455 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927767455 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927767964 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927771013 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1342 " "Peak virtual memory: 1342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:51 2026 " "Processing ended: Wed Sep 9 14:22:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788927771810 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430610558 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430610558 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430610563 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430611045 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430611073 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430611121 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430611389 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430617956 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618032 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430618036 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618036 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618037 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430618037 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430618038 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430618038 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430618038 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430618038 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430618038 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618057 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430623909 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430623909 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430623910 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430623910 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430623911 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430623911 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430623912 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430623914 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430623985 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430626215 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430627179 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430627539 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430627539 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430628497 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430634025 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430634025 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430634284 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430634286 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430635157 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635194 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430635550 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635550 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430636274 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430638928 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1388 " "Peak virtual memory: 1388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:59 2026 " "Processing ended: Tue Sep 15 10:03:59 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430639787 ""} diff --git a/Quartus/A1_Q4/db/alu.hier_info b/Quartus/A1_Q4/db/alu.hier_info index 6db64fc..3347177 100644 --- a/Quartus/A1_Q4/db/alu.hier_info +++ b/Quartus/A1_Q4/db/alu.hier_info @@ -1,8 +1,14 @@ |alu op[0] => op[0].IN1 op[1] => op[1].IN1 -op[2] => ~NO_FANOUT~ -op[3] => ~NO_FANOUT~ +op[2] => Mux0.IN3 +op[2] => Mux1.IN3 +op[2] => Mux2.IN3 +op[2] => Mux3.IN9 +op[3] => Mux0.IN2 +op[3] => Mux1.IN2 +op[3] => Mux2.IN2 +op[3] => Mux3.IN8 A[0] => A[0].IN2 A[1] => A[1].IN2 A[2] => A[2].IN2 @@ -11,29 +17,33 @@ B[0] => B[0].IN2 B[1] => B[1].IN2 B[2] => B[2].IN2 B[3] => B[3].IN2 -OUT_1[0] <= -OUT_1[1] <= -OUT_1[2] <= -OUT_1[3] <= -flags[0] <= -flags[1] <= +OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +flags[0] <= asu:adder_unit.port4 +flags[1] <= asu:adder_unit.port5 |alu|asu:adder_unit -op[0] => operand[0].IN0 -op[0] => operand[1].IN0 -op[0] => operand[2].IN0 -op[0] => operand[3].IN0 +op[0] => operand[3].OUTPUTSELECT +op[0] => operand[2].OUTPUTSELECT +op[0] => operand[1].OUTPUTSELECT +op[0] => operand[0].OUTPUTSELECT op[0] => _.DATAB A[0] => _.DATAD A[1] => _.DATAD A[2] => _.DATAD A[3] => OUT_CIN.IN1 A[3] => _.DATAD -B[0] => operand[0].IN1 -B[1] => operand[1].IN1 -B[2] => operand[2].IN1 -B[3] => operand[3].IN1 +B[0] => operand[0].DATAB +B[0] => operand[0].DATAA +B[1] => operand[1].DATAB +B[1] => operand[1].DATAA +B[2] => operand[2].DATAB +B[2] => operand[2].DATAA +B[3] => operand[3].DATAB +B[3] => operand[3].DATAA OUT_1[0] <= _.SUM_OUT OUT_1[1] <= _.SUM_OUT OUT_1[2] <= _.SUM_OUT diff --git a/Quartus/A1_Q4/db/alu.hif b/Quartus/A1_Q4/db/alu.hif index a136ff9..35355a7 100644 Binary files a/Quartus/A1_Q4/db/alu.hif and b/Quartus/A1_Q4/db/alu.hif differ diff --git a/Quartus/A1_Q4/db/alu.lpc.html b/Quartus/A1_Q4/db/alu.lpc.html index 9b39c78..54e44cd 100644 --- a/Quartus/A1_Q4/db/alu.lpc.html +++ b/Quartus/A1_Q4/db/alu.lpc.html @@ -18,13 +18,13 @@ logic_unit 10 -2 0 -2 +0 +0 4 -2 -2 -2 +0 +0 +0 0 0 0 diff --git a/Quartus/A1_Q4/db/alu.lpc.rdb b/Quartus/A1_Q4/db/alu.lpc.rdb index 45a8041..8be49ac 100644 Binary files a/Quartus/A1_Q4/db/alu.lpc.rdb and b/Quartus/A1_Q4/db/alu.lpc.rdb differ diff --git a/Quartus/A1_Q4/db/alu.lpc.txt b/Quartus/A1_Q4/db/alu.lpc.txt index 223e576..fc26869 100644 --- a/Quartus/A1_Q4/db/alu.lpc.txt +++ b/Quartus/A1_Q4/db/alu.lpc.txt @@ -3,6 +3,6 @@ +------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; logic_unit ; 10 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; logic_unit ; 10 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; adder_unit ; 9 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A1_Q4/db/alu.map.bpm b/Quartus/A1_Q4/db/alu.map.bpm index 9a9109c..afe79d4 100644 Binary files a/Quartus/A1_Q4/db/alu.map.bpm and b/Quartus/A1_Q4/db/alu.map.bpm differ diff --git a/Quartus/A1_Q4/db/alu.map.cdb b/Quartus/A1_Q4/db/alu.map.cdb index 704941d..0c6fd07 100644 Binary files a/Quartus/A1_Q4/db/alu.map.cdb and b/Quartus/A1_Q4/db/alu.map.cdb differ diff --git a/Quartus/A1_Q4/db/alu.map.hdb b/Quartus/A1_Q4/db/alu.map.hdb index 080735d..dabf3b0 100644 Binary files a/Quartus/A1_Q4/db/alu.map.hdb and b/Quartus/A1_Q4/db/alu.map.hdb differ diff --git a/Quartus/A1_Q4/db/alu.map.qmsg b/Quartus/A1_Q4/db/alu.map.qmsg index 24618b3..195bfba 100644 --- a/Quartus/A1_Q4/db/alu.map.qmsg +++ b/Quartus/A1_Q4/db/alu.map.qmsg @@ -1,17 +1,13 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927733469 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927733470 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:13 2026 " "Processing started: Wed Sep 9 14:22:13 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927733470 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927733470 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927733470 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788927733775 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788927733775 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 3 3 " "Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} { "Info" "ISGN_ENTITY_NAME" "3 alu " "Found entity 3: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927742589 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788927742728 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "OUT_1 alu.sv(8) " "Output port \"OUT_1\" at alu.sv(8) has no driver" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1788927742729 "|alu"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "flags alu.sv(8) " "Output port \"flags\" at alu.sv(8) has no driver" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1788927742729 "|alu"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927742734 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927742738 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1788927743236 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[0\] GND " "Pin \"OUT_1\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[1\] GND " "Pin \"OUT_1\[1\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[2\] GND " "Pin \"OUT_1\[2\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[3\] GND " "Pin \"OUT_1\[3\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "flags\[0\] GND " "Pin \"flags\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|flags[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "flags\[1\] GND " "Pin \"flags\[1\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|flags[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1788927743252 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788927743358 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927743358 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "12 " "Design contains 12 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[0\] " "No output dependent on input pin \"op\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[1\] " "No output dependent on input pin \"op\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[2\] " "No output dependent on input pin \"op\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[3\] " "No output dependent on input pin \"op\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[0\] " "No output dependent on input pin \"A\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[1\] " "No output dependent on input pin \"A\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[2\] " "No output dependent on input pin \"A\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[3\] " "No output dependent on input pin \"A\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[0\] " "No output dependent on input pin \"B\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[1\] " "No output dependent on input pin \"B\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[2\] " "No output dependent on input pin \"B\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[3\] " "No output dependent on input pin \"B\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1788927743394 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788927743395 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788927743395 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788927743395 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "425 " "Peak virtual memory: 425 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:23 2026 " "Processing ended: Wed Sep 9 14:22:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927743401 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430597214 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:03:17 2026 " "Processing started: Tue Sep 15 10:03:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 3 3 " "Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "3 alu " "Found entity 3: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430607470 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430607626 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607634 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607639 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430608371 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430608734 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430608734 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430608768 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430608768 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:28 2026 " "Processing ended: Tue Sep 15 10:03:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430608774 ""} diff --git a/Quartus/A1_Q4/db/alu.map.rdb b/Quartus/A1_Q4/db/alu.map.rdb index 0b54309..c52b0d6 100644 Binary files a/Quartus/A1_Q4/db/alu.map.rdb and b/Quartus/A1_Q4/db/alu.map.rdb differ diff --git a/Quartus/A1_Q4/db/alu.map_bb.cdb b/Quartus/A1_Q4/db/alu.map_bb.cdb index da002a5..2f0bb40 100644 Binary files a/Quartus/A1_Q4/db/alu.map_bb.cdb and b/Quartus/A1_Q4/db/alu.map_bb.cdb differ diff --git a/Quartus/A1_Q4/db/alu.map_bb.hdb b/Quartus/A1_Q4/db/alu.map_bb.hdb index d418877..2dd3372 100644 Binary files a/Quartus/A1_Q4/db/alu.map_bb.hdb and b/Quartus/A1_Q4/db/alu.map_bb.hdb differ diff --git a/Quartus/A1_Q4/db/alu.pre_map.hdb b/Quartus/A1_Q4/db/alu.pre_map.hdb index 65184bf..432e0ae 100644 Binary files a/Quartus/A1_Q4/db/alu.pre_map.hdb and b/Quartus/A1_Q4/db/alu.pre_map.hdb differ diff --git a/Quartus/A1_Q4/db/alu.routing.rdb b/Quartus/A1_Q4/db/alu.routing.rdb index faae01f..8563023 100644 Binary files a/Quartus/A1_Q4/db/alu.routing.rdb and b/Quartus/A1_Q4/db/alu.routing.rdb differ diff --git a/Quartus/A1_Q4/db/alu.rtlv.hdb b/Quartus/A1_Q4/db/alu.rtlv.hdb index f3e77e2..d20d1b9 100644 Binary files a/Quartus/A1_Q4/db/alu.rtlv.hdb and b/Quartus/A1_Q4/db/alu.rtlv.hdb differ diff --git a/Quartus/A1_Q4/db/alu.rtlv_sg.cdb b/Quartus/A1_Q4/db/alu.rtlv_sg.cdb index f00163f..1751db9 100644 Binary files a/Quartus/A1_Q4/db/alu.rtlv_sg.cdb and b/Quartus/A1_Q4/db/alu.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb b/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb index f9fa6f1..a00be8b 100644 Binary files a/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb and b/Quartus/A1_Q4/db/alu.rtlv_sg_swap.cdb differ diff --git a/Quartus/A1_Q4/db/alu.sta.qmsg b/Quartus/A1_Q4/db/alu.sta.qmsg index 36ace3f..f1ffb8f 100644 --- a/Quartus/A1_Q4/db/alu.sta.qmsg +++ b/Quartus/A1_Q4/db/alu.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927780035 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927780035 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:59 2026 " "Processing started: Wed Sep 9 14:22:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927780035 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927780035 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927780036 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788927780089 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788927780570 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788927780570 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927780648 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927780648 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788927781220 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927781221 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927781221 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927781222 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927781222 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927781222 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788927781223 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788927781228 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927781228 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781230 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781233 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781234 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781235 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781236 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781236 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927781239 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927781277 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927782133 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927782214 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782215 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782216 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782218 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782219 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782221 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782222 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927782226 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927782475 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927782976 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927783014 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783016 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783017 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783018 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783020 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783022 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927783025 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927783164 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927783164 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927783164 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927783165 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783166 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783167 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783167 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783168 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783169 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927784565 ""} -{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927784565 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "760 " "Peak virtual memory: 760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:23:04 2026 " "Processing ended: Wed Sep 9 14:23:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788927784588 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430648073 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:07 2026 " "Processing started: Tue Sep 15 10:04:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430648128 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430648621 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430648622 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430649270 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430649271 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430649271 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430649272 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430649273 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430649277 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430649278 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649279 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649282 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649283 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649284 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430649287 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430649326 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430650655 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430650741 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430650742 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650743 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650745 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650746 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650747 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430650750 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430651010 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430651713 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651764 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651765 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651766 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651767 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651768 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651769 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430651771 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651921 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651921 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651923 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651924 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651926 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "793 " "Peak virtual memory: 793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:13 2026 " "Processing ended: Tue Sep 15 10:04:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430653351 ""} diff --git a/Quartus/A1_Q4/db/alu.sta.rdb b/Quartus/A1_Q4/db/alu.sta.rdb index 998cded..13ba4f0 100644 Binary files a/Quartus/A1_Q4/db/alu.sta.rdb and b/Quartus/A1_Q4/db/alu.sta.rdb differ diff --git a/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb index a8de7bd..3f3ac2e 100644 Binary files a/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q4/db/alu.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb index 6f8015b..72ed6fb 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb index c264b0d..c620d14 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb index 2257862..c898c33 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb index 47c1bd3..63da1ab 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb index 237ca48..61dedea 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb index e43b321..9f80f5b 100644 Binary files a/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q4/db/alu.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q4/db/alu.tmw_info b/Quartus/A1_Q4/db/alu.tmw_info index 1bd50f7..52c26ab 100644 --- a/Quartus/A1_Q4/db/alu.tmw_info +++ b/Quartus/A1_Q4/db/alu.tmw_info @@ -1,4 +1,7 @@ -start_full_compilation:s -start_assembler:s-start_full_compilation -start_timing_analyzer:s-start_full_compilation -start_eda_netlist_writer:s-start_full_compilation +start_full_compilation:s:00:01:00 +start_analysis_synthesis:s:00:00:13-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:31-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation +start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A1_Q4/db/alu.vpr.ammdb b/Quartus/A1_Q4/db/alu.vpr.ammdb index 6c23694..01b2d8a 100644 Binary files a/Quartus/A1_Q4/db/alu.vpr.ammdb and b/Quartus/A1_Q4/db/alu.vpr.ammdb differ diff --git a/Quartus/A1_Q4/db/alu_partition_pins.json b/Quartus/A1_Q4/db/alu_partition_pins.json index aeab6ee..2ca2efe 100644 --- a/Quartus/A1_Q4/db/alu_partition_pins.json +++ b/Quartus/A1_Q4/db/alu_partition_pins.json @@ -2,7 +2,80 @@ "partitions" : [ { "name" : "Top", - "pins" : [] + "pins" : [ + { + "name" : "OUT_1[0]", + "strict" : false + }, + { + "name" : "OUT_1[1]", + "strict" : false + }, + { + "name" : "OUT_1[2]", + "strict" : false + }, + { + "name" : "OUT_1[3]", + "strict" : false + }, + { + "name" : "flags[0]", + "strict" : false + }, + { + "name" : "flags[1]", + "strict" : false + }, + { + "name" : "op[2]", + "strict" : false + }, + { + "name" : "op[3]", + "strict" : false + }, + { + "name" : "B[0]", + "strict" : false + }, + { + "name" : "A[0]", + "strict" : false + }, + { + "name" : "op[0]", + "strict" : false + }, + { + "name" : "op[1]", + "strict" : false + }, + { + "name" : "B[3]", + "strict" : false + }, + { + "name" : "A[3]", + "strict" : false + }, + { + "name" : "B[1]", + "strict" : false + }, + { + "name" : "A[1]", + "strict" : false + }, + { + "name" : "B[2]", + "strict" : false + }, + { + "name" : "A[2]", + "strict" : false + } + ] } ] } \ No newline at end of file diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb index d25c683..12efe70 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb index 9e9dde7..ed82a2b 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb index 77d21bf..9e302a7 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb index e0fada9..cf2566b 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb index b522a7f..f6b4768 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb index 099bf46..7ed45bb 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb index 376528e..27ef4ce 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.cdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi index 5775472..c2b027c 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.dpi differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb index 5546fd6..82103e9 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb index 2aac181..9135c59 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb index 2e4743e..dc7f779 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.root_partition.map.hdb differ diff --git a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb index 6460c43..a12ec8a 100644 Binary files a/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb and b/Quartus/A1_Q4/incremental_db/compiled_partitions/alu.rrp.hdb differ diff --git a/Quartus/A1_Q4/lu.sv b/Quartus/A1_Q4/lu.sv new file mode 100644 index 0000000..ce372a3 --- /dev/null +++ b/Quartus/A1_Q4/lu.sv @@ -0,0 +1,19 @@ +`ifndef LU_H_SV +`define LU_H_SV +module lu #(parameter width = 2) ( + input logic [1:0] op, + input logic [2**width-1:0] A, + input logic [2**width-1:0] B, + output logic [2**width-1:0] Y); + + always_comb begin + case (op) + 2'b00: Y = A & B; + 2'b01: Y = A | B; + 2'b10: Y = A ^ B; + 2'b11: Y = ~(A | B); + default:Y = '0; + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/Quartus/A1_Q4/output_files/alu.asm.rpt b/Quartus/A1_Q4/output_files/alu.asm.rpt index 775f9ea..8edea52 100644 --- a/Quartus/A1_Q4/output_files/alu.asm.rpt +++ b/Quartus/A1_Q4/output_files/alu.asm.rpt @@ -1,5 +1,5 @@ Assembler report for alu -Wed Sep 9 14:22:58 2026 +Tue Sep 15 10:04:06 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Sep 9 14:22:58 2026 ; +; Assembler Status ; Successful - Tue Sep 15 10:04:06 2026 ; ; Revision Name ; alu ; ; Top-level Entity Name ; alu ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+------------------+ ; Option ; Setting ; +----------------+------------------+ -; JTAG usercode ; 0x0077DC97 ; -; Checksum ; 0x0077DC97 ; +; JTAG usercode ; 0x0078346C ; +; Checksum ; 0x0078346C ; +----------------+------------------+ @@ -78,13 +78,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Wed Sep 9 14:22:53 2026 + Info: Processing started: Tue Sep 15 10:04:01 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 516 megabytes - Info: Processing ended: Wed Sep 9 14:22:58 2026 + Info: Peak virtual memory: 525 megabytes + Info: Processing ended: Tue Sep 15 10:04:06 2026 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q4/output_files/alu.done b/Quartus/A1_Q4/output_files/alu.done index 2669a43..31fd0b2 100644 --- a/Quartus/A1_Q4/output_files/alu.done +++ b/Quartus/A1_Q4/output_files/alu.done @@ -1 +1 @@ -Wed Sep 9 14:23:07 2026 +Tue Sep 15 10:04:16 2026 diff --git a/Quartus/A1_Q4/output_files/alu.eda.rpt b/Quartus/A1_Q4/output_files/alu.eda.rpt index 40ffe30..a666823 100644 --- a/Quartus/A1_Q4/output_files/alu.eda.rpt +++ b/Quartus/A1_Q4/output_files/alu.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for alu -Wed Sep 9 14:23:06 2026 +Tue Sep 15 10:04:15 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Wed Sep 9 14:23:06 2026 ; +; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:04:15 2026 ; ; Revision Name ; alu ; ; Top-level Entity Name ; alu ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Wed Sep 9 14:23:05 2026 + Info: Processing started: Tue Sep 15 10:04:14 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file alu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 670 megabytes - Info: Processing ended: Wed Sep 9 14:23:06 2026 + Info: Peak virtual memory: 658 megabytes + Info: Processing ended: Tue Sep 15 10:04:15 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q4/output_files/alu.fit.rpt b/Quartus/A1_Q4/output_files/alu.fit.rpt index 53c9c55..a20f98a 100644 --- a/Quartus/A1_Q4/output_files/alu.fit.rpt +++ b/Quartus/A1_Q4/output_files/alu.fit.rpt @@ -1,5 +1,5 @@ Fitter report for alu -Wed Sep 9 14:22:51 2026 +Tue Sep 15 10:03:59 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -57,14 +57,14 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Wed Sep 9 14:22:51 2026 ; +; Fitter Status ; Successful - Tue Sep 15 10:03:59 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; alu ; ; Top-level Entity Name ; alu ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; ; Total pins ; 18 / 364 ( 5 % ) ; ; Total virtual pins ; 0 ; @@ -152,7 +152,7 @@ on the Quartus Prime software download page. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 0.2% ; +----------------------------+-------------+ @@ -162,8 +162,8 @@ on the Quartus Prime software download page. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+-------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; -; -- Achieved ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; +; -- Requested ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; +; -- Achieved ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -186,7 +186,7 @@ on the Quartus Prime software download page. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 51 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -202,11 +202,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------------------------------------------------------------+--------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+--------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29,080 ; < 1 % ; -; ALMs needed [=A-B+C] ; 1 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29,080 ; < 1 % ; +; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 11 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29,080 ; < 1 % ; ; [a] ALMs used for LUT logic and registers ; 0 ; ; -; [b] ALMs used for LUT logic ; 1 ; ; +; [b] ALMs used for LUT logic ; 11 ; ; ; [c] ALMs used for registers ; 0 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; ; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ; @@ -218,16 +218,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Difficulty packing design ; Low ; ; ; ; ; ; -; Total LABs: partially or completely used ; 1 / 2,908 ; < 1 % ; -; -- Logic LABs ; 1 ; ; +; Total LABs: partially or completely used ; 3 / 2,908 ; < 1 % ; +; -- Logic LABs ; 3 ; ; ; -- Memory LABs (up to half of total LABs) ; 0 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 1 ; ; -; -- 7 input functions ; 0 ; ; -; -- 6 input functions ; 0 ; ; +; Combinational ALUT usage for logic ; 15 ; ; +; -- 7 input functions ; 3 ; ; +; -- 6 input functions ; 3 ; ; ; -- 5 input functions ; 0 ; ; -; -- 4 input functions ; 0 ; ; -; -- <=3 input functions ; 1 ; ; +; -- 4 input functions ; 1 ; ; +; -- <=3 input functions ; 8 ; ; ; Combinational ALUT usage for route-throughs ; 0 ; ; ; ; ; ; ; Dedicated logic registers ; 0 ; ; @@ -240,7 +240,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; ; ; ; ; Virtual pins ; 0 ; ; ; I/O pins ; 18 / 364 ; 5 % ; -; -- Clock pins ; 1 / 14 ; 7 % ; +; -- Clock pins ; 0 / 14 ; 0 % ; ; -- Dedicated input pins ; 0 / 23 ; 0 % ; ; ; ; ; ; M10K blocks ; 0 / 446 ; 0 % ; @@ -271,98 +271,98 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Impedance control blocks ; 0 / 3 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; ; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; -; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; -; Maximum fan-out ; 1 ; ; -; Highest non-global fan-out ; 1 ; ; -; Total fan-out ; 18 ; ; -; Average fan-out ; 0.49 ; ; +; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.2% ; ; +; Maximum fan-out ; 7 ; ; +; Highest non-global fan-out ; 7 ; ; +; Total fan-out ; 84 ; ; +; Average fan-out ; 1.65 ; ; +-------------------------------------------------------------+--------------------+-------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+-------------------------------------------------------------+---------------------+--------------------------------+ -; Statistic ; Top ; hard_block:auto_generated_inst ; -+-------------------------------------------------------------+---------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 1 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; -; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; -; [b] ALMs used for LUT logic ; 1 ; 0 ; -; [c] ALMs used for registers ; 0 ; 0 ; -; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; -; [a] Due to location constrained logic ; 0 ; 0 ; -; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; -; [c] Due to LAB input limits ; 0 ; 0 ; -; [d] Due to virtual I/Os ; 0 ; 0 ; -; ; ; ; -; Difficulty packing design ; Low ; Low ; -; ; ; ; -; Total LABs: partially or completely used ; 1 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; -; -- Logic LABs ; 1 ; 0 ; -; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; -; ; ; ; -; Combinational ALUT usage for logic ; 1 ; 0 ; -; -- 7 input functions ; 0 ; 0 ; -; -- 6 input functions ; 0 ; 0 ; -; -- 5 input functions ; 0 ; 0 ; -; -- 4 input functions ; 0 ; 0 ; -; -- <=3 input functions ; 1 ; 0 ; -; Combinational ALUT usage for route-throughs ; 0 ; 0 ; -; Memory ALUT usage ; 0 ; 0 ; -; -- 64-address deep ; 0 ; 0 ; -; -- 32-address deep ; 0 ; 0 ; -; ; ; ; -; Dedicated logic registers ; 0 ; 0 ; -; -- By type: ; ; ; -; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; -; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; -; -- By function: ; ; ; -; -- Design implementation registers ; 0 ; 0 ; -; -- Routing optimization registers ; 0 ; 0 ; -; ; ; ; -; ; ; ; -; Virtual pins ; 0 ; 0 ; -; I/O pins ; 18 ; 0 ; -; I/O registers ; 0 ; 0 ; -; Total block memory bits ; 0 ; 0 ; -; Total block memory implementation bits ; 0 ; 0 ; -; ; ; ; -; Connections ; ; ; -; -- Input Connections ; 0 ; 0 ; -; -- Registered Input Connections ; 0 ; 0 ; -; -- Output Connections ; 0 ; 0 ; -; -- Registered Output Connections ; 0 ; 0 ; -; ; ; ; -; Internal Connections ; ; ; -; -- Total Connections ; 18 ; 0 ; -; -- Registered Connections ; 0 ; 0 ; -; ; ; ; -; External Connections ; ; ; -; -- Top ; 0 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; -; ; ; ; -; Partition Interface ; ; ; -; -- Input Ports ; 12 ; 0 ; -; -- Output Ports ; 6 ; 0 ; -; -- Bidir Ports ; 0 ; 0 ; -; ; ; ; -; Registered Ports ; ; ; -; -- Registered Input Ports ; 0 ; 0 ; -; -- Registered Output Ports ; 0 ; 0 ; -; ; ; ; -; Port Connectivity ; ; ; -; -- Input Ports driven by GND ; 0 ; 0 ; -; -- Output Ports driven by GND ; 0 ; 0 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 0 ; -; -- Output Ports with no Source ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 0 ; -; -- Output Ports with no Fanout ; 0 ; 0 ; -+-------------------------------------------------------------+---------------------+--------------------------------+ ++---------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 11 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; +; [b] ALMs used for LUT logic ; 11 ; 0 ; +; [c] ALMs used for registers ; 0 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 3 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; +; -- Logic LABs ; 3 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 15 ; 0 ; +; -- 7 input functions ; 3 ; 0 ; +; -- 6 input functions ; 3 ; 0 ; +; -- 5 input functions ; 0 ; 0 ; +; -- 4 input functions ; 1 ; 0 ; +; -- <=3 input functions ; 8 ; 0 ; +; Combinational ALUT usage for route-throughs ; 0 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; 0 ; +; -- Routing optimization registers ; 0 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 18 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 0 ; 0 ; +; Total block memory implementation bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 88 ; 0 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 12 ; 0 ; +; -- Output Ports ; 6 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+----------------------+--------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -370,18 +370,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; A[0] ; U22 ; 5A ; 68 ; 12 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[1] ; AF21 ; 4A ; 51 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[2] ; AB17 ; 4A ; 51 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; A[3] ; AA18 ; 4A ; 62 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[0] ; C19 ; 7A ; 59 ; 61 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[1] ; T13 ; 3B ; 15 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[2] ; B20 ; 7A ; 62 ; 61 ; 91 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; B[3] ; E26 ; 6A ; 68 ; 37 ; 54 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[0] ; H9 ; 8A ; 19 ; 61 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[1] ; B24 ; 7A ; 65 ; 61 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[2] ; K24 ; 6A ; 68 ; 41 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; -; op[3] ; V25 ; 5B ; 68 ; 19 ; 54 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[0] ; P8 ; 3A ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[1] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[2] ; R9 ; 3A ; 6 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[3] ; Y8 ; 3A ; 6 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[1] ; AB6 ; 3A ; 4 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[2] ; R8 ; 3A ; 7 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[3] ; R10 ; 3A ; 6 ; 0 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[0] ; AD6 ; 3A ; 7 ; 0 ; 51 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[1] ; U7 ; 3A ; 2 ; 0 ; 91 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[2] ; AD7 ; 3A ; 7 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[3] ; U9 ; 3B ; 10 ; 0 ; 91 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ @@ -390,31 +390,31 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -; OUT_1[0] ; A5 ; 8A ; 21 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[1] ; AA7 ; 3A ; 6 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[2] ; AF16 ; 4A ; 59 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; OUT_1[3] ; E11 ; 7A ; 40 ; 61 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; flags[0] ; F12 ; 7A ; 36 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; -; flags[1] ; W25 ; 5B ; 68 ; 26 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[0] ; AA6 ; 3A ; 4 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[1] ; Y9 ; 3A ; 4 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[3] ; W8 ; 3A ; 4 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; flags[0] ; AB10 ; 3B ; 12 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; flags[1] ; AA7 ; 3A ; 6 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ -+--------------------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+----------------+---------------+--------------+---------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; -+----------+----------------+---------------+--------------+---------------+ -; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; -; 3A ; 1 / 16 ( 6 % ) ; 2.5V ; -- ; 2.5V ; -; 3B ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ; -; 4A ; 4 / 80 ( 5 % ) ; 2.5V ; -- ; 2.5V ; -; 5A ; 1 / 16 ( 6 % ) ; 2.5V ; -- ; 2.5V ; -; 5B ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ; -; 6A ; 2 / 48 ( 4 % ) ; 2.5V ; -- ; 2.5V ; -; 7A ; 5 / 80 ( 6 % ) ; 2.5V ; -- ; 2.5V ; -; 8A ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ; -+----------+----------------+---------------+--------------+---------------+ ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 13 / 16 ( 81 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 5 / 32 ( 16 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -425,7 +425,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; A2 ; 396 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; ; A3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; ; A4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; -; A5 ; 344 ; 8A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A5 ; 344 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; A6 ; 392 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; ; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -451,8 +451,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; ; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA7 ; 47 ; 3A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA6 ; 45 ; 3A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA7 ; 47 ; 3A ; flags[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -463,7 +463,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA18 ; 151 ; 4A ; A[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -477,18 +477,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB6 ; 43 ; 3A ; B[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 61 ; 3B ; flags[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB17 ; 129 ; 4A ; A[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -529,8 +529,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD6 ; 51 ; 3A ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AD7 ; 53 ; 3A ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -590,12 +590,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AF16 ; 143 ; 4A ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF19 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AF21 ; 128 ; 4A ; A[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -619,11 +619,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; B17 ; 298 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; B19 ; 282 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B20 ; 278 ; 7A ; B[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; B24 ; 267 ; 7A ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -644,7 +644,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C19 ; 284 ; 7A ; B[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; C20 ; 280 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; C22 ; 266 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -688,7 +688,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; E8 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E11 ; 326 ; 7A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -703,7 +703,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; E23 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; E24 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; E25 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E26 ; 229 ; 6A ; B[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E26 ; 229 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; F1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; F2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; ; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -715,7 +715,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; F11 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F12 ; 333 ; 7A ; flags[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; ; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -764,7 +764,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H9 ; 349 ; 8A ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; ; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -831,7 +831,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; K21 ; 248 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; K22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; K23 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K24 ; 234 ; 6A ; op[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K24 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; K25 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; K26 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -919,7 +919,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; ; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P8 ; 52 ; 3A ; A[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -945,9 +945,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R8 ; 50 ; 3A ; B[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R9 ; 48 ; 3A ; A[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R10 ; 46 ; 3A ; B[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; @@ -972,11 +972,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 56 ; 3B ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T13 ; 68 ; 3B ; B[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; @@ -996,9 +996,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; ; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; -; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U7 ; 39 ; 3A ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U9 ; 54 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1011,7 +1011,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U22 ; 177 ; 5A ; A[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; U25 ; 211 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; @@ -1040,7 +1040,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V25 ; 197 ; 5B ; op[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; @@ -1049,10 +1049,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; ; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W8 ; 42 ; 3A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; B[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; @@ -1066,7 +1066,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; ; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; ; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W25 ; 207 ; 5B ; flags[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; W25 ; 207 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; W26 ; 209 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; ; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; @@ -1075,10 +1075,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; ; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 49 ; 3A ; A[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y9 ; 44 ; 3A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 55 ; 3B ; A[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; ; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; ; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; @@ -1103,42 +1103,42 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------+-------------------------------+ ; Pin Name ; Reason ; +----------+-------------------------------+ -; op[0] ; Incomplete set of assignments ; -; op[1] ; Incomplete set of assignments ; -; op[2] ; Incomplete set of assignments ; -; op[3] ; Incomplete set of assignments ; -; A[0] ; Incomplete set of assignments ; -; A[1] ; Incomplete set of assignments ; -; A[2] ; Incomplete set of assignments ; -; A[3] ; Incomplete set of assignments ; -; B[0] ; Incomplete set of assignments ; -; B[1] ; Incomplete set of assignments ; -; B[2] ; Incomplete set of assignments ; -; B[3] ; Incomplete set of assignments ; ; OUT_1[0] ; Incomplete set of assignments ; ; OUT_1[1] ; Incomplete set of assignments ; ; OUT_1[2] ; Incomplete set of assignments ; ; OUT_1[3] ; Incomplete set of assignments ; ; flags[0] ; Incomplete set of assignments ; ; flags[1] ; Incomplete set of assignments ; -; op[0] ; Missing location assignment ; -; op[1] ; Missing location assignment ; -; op[2] ; Missing location assignment ; -; op[3] ; Missing location assignment ; -; A[0] ; Missing location assignment ; -; A[1] ; Missing location assignment ; -; A[2] ; Missing location assignment ; -; A[3] ; Missing location assignment ; -; B[0] ; Missing location assignment ; -; B[1] ; Missing location assignment ; -; B[2] ; Missing location assignment ; -; B[3] ; Missing location assignment ; +; op[2] ; Incomplete set of assignments ; +; op[3] ; Incomplete set of assignments ; +; B[0] ; Incomplete set of assignments ; +; A[0] ; Incomplete set of assignments ; +; op[0] ; Incomplete set of assignments ; +; op[1] ; Incomplete set of assignments ; +; B[3] ; Incomplete set of assignments ; +; A[3] ; Incomplete set of assignments ; +; B[1] ; Incomplete set of assignments ; +; A[1] ; Incomplete set of assignments ; +; B[2] ; Incomplete set of assignments ; +; A[2] ; Incomplete set of assignments ; ; OUT_1[0] ; Missing location assignment ; ; OUT_1[1] ; Missing location assignment ; ; OUT_1[2] ; Missing location assignment ; ; OUT_1[3] ; Missing location assignment ; ; flags[0] ; Missing location assignment ; ; flags[1] ; Missing location assignment ; +; op[2] ; Missing location assignment ; +; op[3] ; Missing location assignment ; +; B[0] ; Missing location assignment ; +; A[0] ; Missing location assignment ; +; op[0] ; Missing location assignment ; +; op[1] ; Missing location assignment ; +; B[3] ; Missing location assignment ; +; A[3] ; Missing location assignment ; +; B[1] ; Missing location assignment ; +; A[1] ; Missing location assignment ; +; B[2] ; Missing location assignment ; +; A[2] ; Missing location assignment ; +----------+-------------------------------+ @@ -1147,7 +1147,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ -; |alu ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ; +; |alu ; 10.5 (7.5) ; 10.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ; +; |asu:adder_unit| ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ; +----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -1157,71 +1158,117 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ ; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -; op[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; op[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; A[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; B[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; flags[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; flags[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; op[0] ; ; ; -; op[1] ; ; ; -; op[2] ; ; ; -; op[3] ; ; ; -; A[0] ; ; ; -; A[1] ; ; ; -; A[2] ; ; ; -; A[3] ; ; ; -; B[0] ; ; ; -; B[1] ; ; ; -; B[2] ; ; ; -; B[3] ; ; ; -+---------------------+-------------------+---------+ ++----------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------------------+-------------------+---------+ +; op[2] ; ; ; +; - Mux0~0 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; - Mux3~2 ; 0 ; 0 ; +; - Mux3~3 ; 0 ; 0 ; +; op[3] ; ; ; +; - Mux0~0 ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; +; - Mux2~0 ; 1 ; 0 ; +; - Mux3~0 ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; - Mux3~2 ; 1 ; 0 ; +; - Mux3~3 ; 1 ; 0 ; +; B[0] ; ; ; +; - asu:adder_unit|OUT_1[0] ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; A[0] ; ; ; +; - asu:adder_unit|OUT_1[0] ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; op[0] ; ; ; +; - Mux0~0 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; - Mux3~2 ; 0 ; 0 ; +; - Mux3~3 ; 0 ; 0 ; +; op[1] ; ; ; +; - Mux0~0 ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; +; - Mux2~0 ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; - Mux3~2 ; 1 ; 0 ; +; - Mux3~3 ; 1 ; 0 ; +; B[3] ; ; ; +; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ; +; - Mux0~0 ; 1 ; 0 ; +; - Mux3~3 ; 1 ; 0 ; +; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ; +; A[3] ; ; ; +; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ; +; - Mux3~3 ; 1 ; 0 ; +; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ; +; - Mux0~0 ; 1 ; 0 ; +; B[1] ; ; ; +; - asu:adder_unit|OUT_1[1] ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; A[1] ; ; ; +; - asu:adder_unit|OUT_1[1] ; 1 ; 0 ; +; - Mux2~0 ; 1 ; 0 ; +; B[2] ; ; ; +; - asu:adder_unit|OUT_1[2] ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; A[2] ; ; ; +; - asu:adder_unit|OUT_1[2] ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; ++----------------------------------+-------------------+---------+ -+----------------------------------------------------+ -; Routing Usage Summary ; -+------------------------------+---------------------+ -; Routing Resource Type ; Usage ; -+------------------------------+---------------------+ -; Block interconnects ; 0 / 217,884 ( 0 % ) ; -; C12 interconnects ; 0 / 10,080 ( 0 % ) ; -; C2 interconnects ; 0 / 87,208 ( 0 % ) ; -; C4 interconnects ; 0 / 41,360 ( 0 % ) ; -; DQS bus muxes ; 0 / 21 ( 0 % ) ; -; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; -; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; -; Direct links ; 0 / 217,884 ( 0 % ) ; -; Global clocks ; 0 / 16 ( 0 % ) ; -; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; -; Local interconnects ; 0 / 58,160 ( 0 % ) ; -; Quadrant clocks ; 0 / 88 ( 0 % ) ; -; R14 interconnects ; 0 / 9,228 ( 0 % ) ; -; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ; -; R3 interconnects ; 0 / 94,896 ( 0 % ) ; -; R6 interconnects ; 0 / 194,640 ( 0 % ) ; -; Spine clocks ; 0 / 180 ( 0 % ) ; -; Wire stub REs ; 0 / 11,606 ( 0 % ) ; -+------------------------------+---------------------+ ++-------------------------------------------------------+ +; Routing Usage Summary ; ++------------------------------+------------------------+ +; Routing Resource Type ; Usage ; ++------------------------------+------------------------+ +; Block interconnects ; 25 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 0 / 10,080 ( 0 % ) ; +; C2 interconnects ; 12 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 7 / 41,360 ( < 1 % ) ; +; DQS bus muxes ; 0 / 21 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; +; Direct links ; 2 / 217,884 ( < 1 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; +; Local interconnects ; 6 / 58,160 ( < 1 % ) ; +; Quadrant clocks ; 0 / 88 ( 0 % ) ; +; R14 interconnects ; 0 / 9,228 ( 0 % ) ; +; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ; +; R3 interconnects ; 15 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 5 / 194,640 ( < 1 % ) ; +; Spine clocks ; 0 / 180 ( 0 % ) ; +; Wire stub REs ; 0 / 11,606 ( 0 % ) ; ++------------------------------+------------------------+ +------------------------------------------+ @@ -1283,24 +1330,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; Total Inapplicable ; 18 ; 18 ; 18 ; 18 ; 18 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 0 ; 0 ; 18 ; ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; -; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; OUT_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; OUT_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; OUT_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; OUT_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; flags[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; ; flags[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ @@ -1374,27 +1421,27 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36 + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03 Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1342 megabytes - Info: Processing ended: Wed Sep 9 14:22:51 2026 - Info: Elapsed time: 00:00:27 - Info: Total CPU time (on all processors): 00:00:39 + Info: Peak virtual memory: 1388 megabytes + Info: Processing ended: Tue Sep 15 10:03:59 2026 + Info: Elapsed time: 00:00:30 + Info: Total CPU time (on all processors): 00:00:43 diff --git a/Quartus/A1_Q4/output_files/alu.fit.summary b/Quartus/A1_Q4/output_files/alu.fit.summary index b9fef70..5e80952 100644 --- a/Quartus/A1_Q4/output_files/alu.fit.summary +++ b/Quartus/A1_Q4/output_files/alu.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Wed Sep 9 14:22:51 2026 +Fitter Status : Successful - Tue Sep 15 10:03:59 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : alu Top-level Entity Name : alu Family : Cyclone V Device : 5CGXFC5C6F27C7 Timing Models : Final -Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % ) +Logic utilization (in ALMs) : 11 / 29,080 ( < 1 % ) Total registers : 0 Total pins : 18 / 364 ( 5 % ) Total virtual pins : 0 diff --git a/Quartus/A1_Q4/output_files/alu.flow.rpt b/Quartus/A1_Q4/output_files/alu.flow.rpt index d44b849..2de001b 100644 --- a/Quartus/A1_Q4/output_files/alu.flow.rpt +++ b/Quartus/A1_Q4/output_files/alu.flow.rpt @@ -1,5 +1,5 @@ Flow report for alu -Wed Sep 9 14:23:06 2026 +Tue Sep 15 10:04:15 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,14 +41,14 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Wed Sep 9 14:23:06 2026 ; +; Flow Status ; Successful - Tue Sep 15 10:04:15 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; alu ; ; Top-level Entity Name ; alu ; ; Family ; Cyclone V ; ; Device ; 5CGXFC5C6F27C7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ; +; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ; ; Total registers ; 0 ; ; Total pins ; 18 / 364 ( 5 % ) ; ; Total virtual pins ; 0 ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/09/2026 14:22:13 ; +; Start date & time ; 09/15/2026 10:03:17 ; ; Main task ; Compilation ; ; Revision Name ; alu ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 268883478169649.178892773303605 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 253029099468756.178943059705529 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:23 ; -; Fitter ; 00:00:27 ; 1.0 ; 1342 MB ; 00:00:38 ; -; Assembler ; 00:00:05 ; 1.0 ; 516 MB ; 00:00:05 ; -; Timing Analyzer ; 00:00:05 ; 1.0 ; 760 MB ; 00:00:05 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ; -; Total ; 00:00:48 ; -- ; -- ; 00:01:12 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ; +; Fitter ; 00:00:30 ; 1.0 ; 1388 MB ; 00:00:43 ; +; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 793 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; +; Total ; 00:00:53 ; -- ; -- ; 00:01:21 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q4/output_files/alu.map.rpt b/Quartus/A1_Q4/output_files/alu.map.rpt index 78a883f..8d1caf9 100644 --- a/Quartus/A1_Q4/output_files/alu.map.rpt +++ b/Quartus/A1_Q4/output_files/alu.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for alu -Wed Sep 9 14:22:23 2026 +Tue Sep 15 10:03:28 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -14,14 +14,13 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. General Register Statistics - 9. Parameter Settings for User Entity Instance: Top-level Entity: |alu - 10. Parameter Settings for User Entity Instance: asu:adder_unit - 11. Parameter Settings for User Entity Instance: lu:logic_unit - 12. Port Connectivity Checks: "lu:logic_unit" - 13. Port Connectivity Checks: "asu:adder_unit" - 14. Post-Synthesis Netlist Statistics for Top Partition - 15. Elapsed Time Per Partition - 16. Analysis & Synthesis Messages + 9. Multiplexer Restructuring Statistics (Restructuring Performed) + 10. Parameter Settings for User Entity Instance: Top-level Entity: |alu + 11. Parameter Settings for User Entity Instance: asu:adder_unit + 12. Parameter Settings for User Entity Instance: lu:logic_unit + 13. Post-Synthesis Netlist Statistics for Top Partition + 14. Elapsed Time Per Partition + 15. Analysis & Synthesis Messages @@ -48,7 +47,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Sep 9 14:22:23 2026 ; +; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:03:28 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; alu ; ; Top-level Entity Name ; alu ; @@ -171,42 +170,42 @@ on the Quartus Prime software download page. +----------------------------+-------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ -; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ; -; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ; -; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+ +; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ; +; asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv ; ; +; lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv ; ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+ -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimate of Logic utilization (ALMs needed) ; 0 ; -; ; ; -; Combinational ALUT usage for logic ; 0 ; -; -- 7 input functions ; 0 ; -; -- 6 input functions ; 0 ; -; -- 5 input functions ; 0 ; -; -- 4 input functions ; 0 ; -; -- <=3 input functions ; 0 ; -; ; ; -; Dedicated logic registers ; 0 ; -; ; ; -; I/O pins ; 18 ; -; ; ; -; Total DSP Blocks ; 0 ; -; ; ; -; Maximum fan-out node ; op[0] ; -; Maximum fan-out ; 1 ; -; Total fan-out ; 18 ; -; Average fan-out ; 0.50 ; -+---------------------------------------------+-------+ ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimate of Logic utilization (ALMs needed) ; 10 ; +; ; ; +; Combinational ALUT usage for logic ; 14 ; +; -- 7 input functions ; 3 ; +; -- 6 input functions ; 3 ; +; -- 5 input functions ; 0 ; +; -- 4 input functions ; 1 ; +; -- <=3 input functions ; 7 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 18 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; op[2]~input ; +; Maximum fan-out ; 7 ; +; Total fan-out ; 84 ; +; Average fan-out ; 1.68 ; ++---------------------------------------------+-------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -214,7 +213,8 @@ on the Quartus Prime software download page. +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ -; |alu ; 0 (0) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ; +; |alu ; 14 (8) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ; +; |asu:adder_unit| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ; +----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -234,6 +234,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 7:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |alu|Mux2 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + +---------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Top-level Entity: |alu ; +----------------+-------+--------------------------------------------+ @@ -264,39 +273,26 @@ Note: In order to hide this table in the UI and the text report file, please set Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "lu:logic_unit" ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+ -; Y ; Output ; Warning ; Output or bidir port (4 bits) is wider than the port expression (2 bits) it drives; bit(s) "Y[3..2]" have no fanouts ; -; Y ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "asu:adder_unit" ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; COUT ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; OUT_CIN ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ - - +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ -; arriav_lcell_comb ; 1 ; -; normal ; 1 ; +; arriav_lcell_comb ; 14 ; +; extend ; 3 ; +; 7 data inputs ; 3 ; +; normal ; 6 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 1 ; +; 6 data inputs ; 3 ; +; shared ; 5 ; ; 0 data inputs ; 1 ; +; 2 data inputs ; 4 ; ; boundary_port ; 18 ; ; ; ; -; Max LUT depth ; 0.00 ; -; Average LUT depth ; 0.00 ; +; Max LUT depth ; 2.40 ; +; Average LUT depth ; 2.20 ; +-----------------------+-----------------------------+ @@ -315,49 +311,28 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Wed Sep 9 14:22:13 2026 + Info: Processing started: Tue Sep 15 10:03:17 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv - Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1 - Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 1 - Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6 + Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv Line: 4 + Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv Line: 3 + Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9 Info (12127): Elaborating entity "alu" for the top level hierarchy -Warning (10034): Output port "OUT_1" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 -Warning (10034): Output port "flags" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 -Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 13 -Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16 -Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "OUT_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 - Warning (13410): Pin "OUT_1[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 - Warning (13410): Pin "OUT_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 - Warning (13410): Pin "OUT_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 - Warning (13410): Pin "flags[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 - Warning (13410): Pin "flags[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8 +Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16 +Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 19 +Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Warning (21074): Design contains 12 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "op[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6 - Warning (15610): No output dependent on input pin "op[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6 - Warning (15610): No output dependent on input pin "op[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6 - Warning (15610): No output dependent on input pin "op[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6 - Warning (15610): No output dependent on input pin "A[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "A[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "A[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "A[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "B[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "B[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "B[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 - Warning (15610): No output dependent on input pin "B[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7 -Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 32 device resources after synthesis - the final resource count might be different Info (21058): Implemented 12 input pins Info (21059): Implemented 6 output pins -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 24 warnings - Info: Peak virtual memory: 425 megabytes - Info: Processing ended: Wed Sep 9 14:22:23 2026 - Info: Elapsed time: 00:00:10 - Info: Total CPU time (on all processors): 00:00:24 + Info (21061): Implemented 14 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 436 megabytes + Info: Processing ended: Tue Sep 15 10:03:28 2026 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:27 diff --git a/Quartus/A1_Q4/output_files/alu.map.summary b/Quartus/A1_Q4/output_files/alu.map.summary index 310d1dd..99da5d5 100644 --- a/Quartus/A1_Q4/output_files/alu.map.summary +++ b/Quartus/A1_Q4/output_files/alu.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Wed Sep 9 14:22:23 2026 +Analysis & Synthesis Status : Successful - Tue Sep 15 10:03:28 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : alu Top-level Entity Name : alu diff --git a/Quartus/A1_Q4/output_files/alu.pin b/Quartus/A1_Q4/output_files/alu.pin index a32065f..c6fd3cf 100644 --- a/Quartus/A1_Q4/output_files/alu.pin +++ b/Quartus/A1_Q4/output_files/alu.pin @@ -79,7 +79,7 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage MSEL2 : A2 : : : : 9A : DNU : A3 : : : : : DNU : A4 : : : : : -OUT_1[0] : A5 : output : 2.5 V : : 8A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A : CONF_DONE : A6 : : : : 9A : RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A : @@ -105,8 +105,8 @@ GND : AA2 : gnd : : GXB_NC : AA3 : : : : B0L : GXB_NC : AA4 : : : : B0L : GND : AA5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A : -OUT_1[1] : AA7 : output : 2.5 V : : 3A : N +OUT_1[0] : AA6 : output : 2.5 V : : 3A : N +flags[1] : AA7 : output : 2.5 V : : 3A : N VCC_AUX : AA8 : power : : 2.5V : : VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : VCCIO3B : AA10 : power : : 2.5V : 3B : @@ -117,7 +117,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : GND : AA15 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : -A[3] : AA18 : input : 2.5 V : : 4A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : VCCIO4A : AA20 : power : : 2.5V : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : @@ -131,18 +131,18 @@ GND : AB2 : : : GND : AB3 : gnd : : : : GND : AB4 : gnd : : : : AS_DATA2, DATA2 : AB5 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A : +B[1] : AB6 : input : 2.5 V : : 3A : N NC : AB7 : : : : : GND : AB8 : gnd : : : : VCCPD3A : AB9 : power : : 2.5V : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : +flags[0] : AB10 : output : 2.5 V : : 3B : N RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : VCCIO4A : AB13 : power : : 2.5V : 4A : VCC_AUX : AB14 : power : : 2.5V : : RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : -A[2] : AB17 : input : 2.5 V : : 4A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : GND : AB18 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A : VCC_AUX : AB20 : power : : 2.5V : : @@ -183,8 +183,8 @@ GND : AD2 : : : GND : AD3 : gnd : : : : GND : AD4 : gnd : : : : AS_DATA1, DATA1 : AD5 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +op[0] : AD6 : input : 2.5 V : : 3A : N +op[2] : AD7 : input : 2.5 V : : 3A : N RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : VCCIO3B : AD9 : power : : 2.5V : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : @@ -244,12 +244,12 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : VCCIO4A : AF15 : power : : 2.5V : 4A : -OUT_1[2] : AF16 : output : 2.5 V : : 4A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A : GND : AF20 : gnd : : : : -A[1] : AF21 : input : 2.5 V : : 4A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : @@ -273,11 +273,11 @@ VREFB7AN0 : B16 : power : : RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A : GND : B18 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : -B[2] : B20 : input : 2.5 V : : 7A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A : VCCIO7A : B23 : power : : 2.5V : 7A : -op[1] : B24 : input : 2.5 V : : 7A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : GND : C1 : gnd : : : : @@ -298,7 +298,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : VCCIO7A : C16 : power : : 2.5V : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : -B[0] : C19 : input : 2.5 V : : 7A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A : GND : C21 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A : @@ -342,7 +342,7 @@ GND : E7 : gnd : : VCCBAT : E8 : power : : 1.2V : : RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A : -OUT_1[3] : E11 : output : 2.5 V : : 7A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A : VCCIO7A : E12 : power : : 2.5V : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A : VCC_AUX : E14 : power : : 2.5V : : @@ -357,7 +357,7 @@ VCCIO6A : E22 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A : -B[3] : E26 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A : NC : F1 : : : : : NC : F2 : : : : : GND : F3 : gnd : : : : @@ -369,7 +369,7 @@ VCCPGM : F8 : power : : 1.8V/2.5 VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A : GND : F10 : gnd : : : : VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A : -flags[0] : F12 : output : 2.5 V : : 7A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A : VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A : DNU : F14 : : : : : VCCIO7A : F15 : power : : 2.5V : 7A : @@ -418,7 +418,7 @@ GND : H5 : : : GND : H6 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A : -op[0] : H9 : input : 2.5 V : : 8A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A : RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A : VCCIO7A : H11 : power : : 2.5V : 7A : RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A : @@ -485,7 +485,7 @@ VCC : K20 : power : : 1.1V RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A : GND : K22 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A : -op[2] : K24 : input : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A : RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : GND : L1 : gnd : : : : @@ -573,7 +573,7 @@ VCCE_GXBL : P4 : power : : 1.1V GND : P5 : gnd : : : : GND : P6 : : : : B1L : GND : P7 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A : +A[0] : P8 : input : 2.5 V : : 3A : N GND : P9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B : @@ -599,9 +599,9 @@ GND : R4 : gnd : : VCCE_GXBL : R5 : power : : 1.1V : : TMS : R6 : input : : : 3A : GND : R7 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A : +B[2] : R8 : input : 2.5 V : : 3A : N +A[2] : R9 : input : 2.5 V : : 3A : N +B[3] : R10 : input : 2.5 V : : 3A : N RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B : GND : R12 : gnd : : : : VCC : R13 : power : : 1.1V : : @@ -626,11 +626,11 @@ GND : T5 : gnd : : TDI : T6 : input : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A : RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B : +OUT_1[2] : T9 : output : 2.5 V : : 3B : N GND : T10 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B : -B[1] : T13 : input : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B : VCC : T14 : power : : 1.1V : : GND : T15 : gnd : : : : VCC : T16 : power : : 1.1V : : @@ -650,9 +650,9 @@ VCCL_GXBL : U3 : power : : 1.1V GND : U4 : gnd : : : : VCCE_GXBL : U5 : power : : 1.1V : : AS_DATA3, DATA3 : U6 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : +op[1] : U7 : input : 2.5 V : : 3A : N VCCIO3B : U8 : power : : 2.5V : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : +op[3] : U9 : input : 2.5 V : : 3B : N RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A : @@ -665,7 +665,7 @@ VCCIO4A : U18 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : VCCPD5A : U21 : power : : 2.5V : 5A : -A[0] : U22 : input : 2.5 V : : 5A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : GND : U23 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B : @@ -694,7 +694,7 @@ VCCIO5A : V21 : power : : 2.5V RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B : -op[3] : V25 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : GND : V26 : gnd : : : : GND : W1 : gnd : : : : GND : W2 : gnd : : : : @@ -703,10 +703,10 @@ GXB_NC : W4 : : : GND : W5 : gnd : : : : GND : W6 : : : : B0L : VCCA_FPLL : W7 : power : : 2.5V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : +OUT_1[3] : W8 : output : 2.5 V : : 3A : N GND : W9 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +B[0] : W11 : input : 2.5 V : : 3B : N RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : VCCIO4A : W14 : power : : 2.5V : 4A : @@ -720,7 +720,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : VREFB5AN0 : W23 : power : : : 5A : VCCIO5B : W24 : power : : 2.5V : 5B : -flags[1] : W25 : output : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B : RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B : GND : Y1 : : : : B0L : GND : Y2 : : : : B0L : @@ -729,10 +729,10 @@ GND : Y4 : gnd : : TCK : Y5 : input : : : 3A : nCSO, DATA4 : Y6 : : : : 3A : VCCIO3A : Y7 : power : : 2.5V : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : +A[3] : Y8 : input : 2.5 V : : 3A : N +OUT_1[1] : Y9 : output : 2.5 V : : 3A : N RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +A[1] : Y11 : input : 2.5 V : : 3B : N GND : Y12 : gnd : : : : RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : diff --git a/Quartus/A1_Q4/output_files/alu.sof b/Quartus/A1_Q4/output_files/alu.sof index c45c5aa..466d322 100644 Binary files a/Quartus/A1_Q4/output_files/alu.sof and b/Quartus/A1_Q4/output_files/alu.sof differ diff --git a/Quartus/A1_Q4/output_files/alu.sta.rpt b/Quartus/A1_Q4/output_files/alu.sta.rpt index ac2f2ac..6647ebd 100644 --- a/Quartus/A1_Q4/output_files/alu.sta.rpt +++ b/Quartus/A1_Q4/output_files/alu.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for alu -Wed Sep 9 14:23:04 2026 +Tue Sep 15 10:04:13 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -48,7 +48,11 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition 40. Report TCCS 41. Report RSKM 42. Unconstrained Paths Summary - 43. Timing Analyzer Messages + 43. Unconstrained Input Ports + 44. Unconstrained Output Ports + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. Timing Analyzer Messages @@ -94,12 +98,12 @@ on the Quartus Prime software download page. ; Number detected on machine ; 4 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.00 ; +; Average used ; 1.02 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; 2.1% ; +----------------------------+-------------+ @@ -300,18 +304,18 @@ No synchronizer chains to report. +-------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------+--------------+-----------------+-----------------+ -; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; ; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ; ; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ; ; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; ; B[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +-------+--------------+-----------------+-----------------+ @@ -321,11 +325,11 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; -; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; -; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -335,11 +339,11 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; -; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; -; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -349,11 +353,11 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; -; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; -; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -363,11 +367,11 @@ No synchronizer chains to report. ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; -; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; -; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; -; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ @@ -396,20 +400,88 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 0 ; 0 ; -; Unconstrained Input Port Paths ; 0 ; 0 ; -; Unconstrained Output Ports ; 0 ; 0 ; -; Unconstrained Output Port Paths ; 0 ; 0 ; +; Unconstrained Input Ports ; 12 ; 12 ; +; Unconstrained Input Port Paths ; 58 ; 58 ; +; Unconstrained Output Ports ; 6 ; 6 ; +; Unconstrained Output Port Paths ; 58 ; 58 ; +---------------------------------+-------+------+ ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Wed Sep 9 14:22:59 2026 + Info: Processing started: Tue Sep 15 10:04:07 2026 Info: Command: quartus_sta A1_Q4 -c alu Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -466,12 +538,12 @@ Info (332140): No Hold paths to report Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report -Info (332101): Design is fully constrained for setup requirements -Info (332101): Design is fully constrained for hold requirements +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 760 megabytes - Info: Processing ended: Wed Sep 9 14:23:04 2026 - Info: Elapsed time: 00:00:05 + Info: Peak virtual memory: 793 megabytes + Info: Processing ended: Tue Sep 15 10:04:13 2026 + Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q4/simulation/questa/alu.svo b/Quartus/A1_Q4/simulation/questa/alu.svo index f037f26..a1a9cb5 100644 --- a/Quartus/A1_Q4/simulation/questa/alu.svo +++ b/Quartus/A1_Q4/simulation/questa/alu.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/09/2026 14:23:06" +// DATE "09/15/2026 10:04:15" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -39,27 +39,27 @@ input logic [3:0] op ; input logic [3:0] A ; input logic [3:0] B ; output logic [3:0] OUT_1 ; -output logic flags [1:0]; +output logic [1:0] flags ; // Design Ports Information -// op[0] => Location: PIN_H9, I/O Standard: 2.5 V, Current Strength: Default -// op[1] => Location: PIN_B24, I/O Standard: 2.5 V, Current Strength: Default -// op[2] => Location: PIN_K24, I/O Standard: 2.5 V, Current Strength: Default -// op[3] => Location: PIN_V25, I/O Standard: 2.5 V, Current Strength: Default -// A[0] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default -// A[1] => Location: PIN_AF21, I/O Standard: 2.5 V, Current Strength: Default -// A[2] => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default -// A[3] => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default -// B[0] => Location: PIN_C19, I/O Standard: 2.5 V, Current Strength: Default -// B[1] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default -// B[2] => Location: PIN_B20, I/O Standard: 2.5 V, Current Strength: Default -// B[3] => Location: PIN_E26, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[2] => Location: PIN_AF16, I/O Standard: 2.5 V, Current Strength: Default -// OUT_1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default -// flags[0] => Location: PIN_F12, I/O Standard: 2.5 V, Current Strength: Default -// flags[1] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[0] => Location: PIN_AA6, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[1] => Location: PIN_Y9, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[3] => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default +// flags[0] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default +// flags[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default +// op[2] => Location: PIN_AD7, I/O Standard: 2.5 V, Current Strength: Default +// op[3] => Location: PIN_U9, I/O Standard: 2.5 V, Current Strength: Default +// B[0] => Location: PIN_W11, I/O Standard: 2.5 V, Current Strength: Default +// A[0] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// op[0] => Location: PIN_AD6, I/O Standard: 2.5 V, Current Strength: Default +// op[1] => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default +// B[3] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// A[3] => Location: PIN_Y8, I/O Standard: 2.5 V, Current Strength: Default +// B[1] => Location: PIN_AB6, I/O Standard: 2.5 V, Current Strength: Default +// A[1] => Location: PIN_Y11, I/O Standard: 2.5 V, Current Strength: Default +// B[2] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default +// A[2] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default wire gnd; @@ -73,24 +73,43 @@ assign unknown = 1'bx; tri1 devclrn; tri1 devpor; tri1 devoe; -wire \op[0]~input_o ; -wire \op[1]~input_o ; -wire \op[2]~input_o ; -wire \op[3]~input_o ; -wire \A[0]~input_o ; -wire \A[1]~input_o ; -wire \A[2]~input_o ; -wire \A[3]~input_o ; -wire \B[0]~input_o ; -wire \B[1]~input_o ; -wire \B[2]~input_o ; -wire \B[3]~input_o ; wire \~QUARTUS_CREATED_GND~I_combout ; +wire \op[0]~input_o ; +wire \B[3]~input_o ; +wire \A[3]~input_o ; +wire \op[2]~input_o ; +wire \op[1]~input_o ; +wire \op[3]~input_o ; +wire \Mux3~3_combout ; +wire \A[0]~input_o ; +wire \B[0]~input_o ; +wire \Mux3~0_combout ; +wire \B[2]~input_o ; +wire \A[2]~input_o ; +wire \A[1]~input_o ; +wire \B[1]~input_o ; +wire \adder_unit|_~1 ; +wire \adder_unit|_~2 ; +wire \adder_unit|_~7 ; +wire \adder_unit|_~8 ; +wire \adder_unit|_~10 ; +wire \adder_unit|_~11 ; +wire \adder_unit|_~13 ; +wire \adder_unit|_~14 ; +wire \Mux3~2_combout ; +wire \Mux3~1_combout ; +wire \Mux3~4_combout ; +wire \Mux2~0_combout ; +wire \Mux1~0_combout ; +wire \Mux0~0_combout ; +wire [0:0] \adder_unit|OUT_CIN ; +wire [3:0] \adder_unit|OUT_1 ; +wire [0:0] \adder_unit|COUT ; -// Location: IOOBUF_X21_Y61_N36 +// Location: IOOBUF_X4_Y0_N36 cyclonev_io_obuf \OUT_1[0]~output ( - .i(gnd), + .i(\Mux3~4_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -104,9 +123,9 @@ defparam \OUT_1[0]~output .open_drain_output = "false"; defparam \OUT_1[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X6_Y0_N53 +// Location: IOOBUF_X4_Y0_N2 cyclonev_io_obuf \OUT_1[1]~output ( - .i(gnd), + .i(\Mux2~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -120,9 +139,9 @@ defparam \OUT_1[1]~output .open_drain_output = "false"; defparam \OUT_1[1]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X59_Y0_N19 +// Location: IOOBUF_X10_Y0_N76 cyclonev_io_obuf \OUT_1[2]~output ( - .i(gnd), + .i(\Mux1~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -136,9 +155,9 @@ defparam \OUT_1[2]~output .open_drain_output = "false"; defparam \OUT_1[2]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X40_Y61_N93 +// Location: IOOBUF_X4_Y0_N19 cyclonev_io_obuf \OUT_1[3]~output ( - .i(gnd), + .i(\Mux0~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -152,9 +171,9 @@ defparam \OUT_1[3]~output .open_drain_output = "false"; defparam \OUT_1[3]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X36_Y61_N19 +// Location: IOOBUF_X12_Y0_N36 cyclonev_io_obuf \flags[0]~output ( - .i(gnd), + .i(\adder_unit|COUT [0]), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -168,9 +187,9 @@ defparam \flags[0]~output .open_drain_output = "false"; defparam \flags[0]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOOBUF_X68_Y26_N39 +// Location: IOOBUF_X6_Y0_N53 cyclonev_io_obuf \flags[1]~output ( - .i(gnd), + .i(\adder_unit|OUT_CIN [0]), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -184,7 +203,7 @@ defparam \flags[1]~output .open_drain_output = "false"; defparam \flags[1]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOIBUF_X19_Y61_N18 +// Location: IOIBUF_X7_Y0_N52 cyclonev_io_ibuf \op[0]~input ( .i(op[0]), .ibar(gnd), @@ -195,117 +214,7 @@ defparam \op[0]~input .bus_hold = "false"; defparam \op[0]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X65_Y61_N1 -cyclonev_io_ibuf \op[1]~input ( - .i(op[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[1]~input_o )); -// synopsys translate_off -defparam \op[1]~input .bus_hold = "false"; -defparam \op[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y41_N4 -cyclonev_io_ibuf \op[2]~input ( - .i(op[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[2]~input_o )); -// synopsys translate_off -defparam \op[2]~input .bus_hold = "false"; -defparam \op[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y19_N55 -cyclonev_io_ibuf \op[3]~input ( - .i(op[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\op[3]~input_o )); -// synopsys translate_off -defparam \op[3]~input .bus_hold = "false"; -defparam \op[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y12_N21 -cyclonev_io_ibuf \A[0]~input ( - .i(A[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[0]~input_o )); -// synopsys translate_off -defparam \A[0]~input .bus_hold = "false"; -defparam \A[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X51_Y0_N35 -cyclonev_io_ibuf \A[1]~input ( - .i(A[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[1]~input_o )); -// synopsys translate_off -defparam \A[1]~input .bus_hold = "false"; -defparam \A[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X51_Y0_N1 -cyclonev_io_ibuf \A[2]~input ( - .i(A[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[2]~input_o )); -// synopsys translate_off -defparam \A[2]~input .bus_hold = "false"; -defparam \A[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X62_Y0_N58 -cyclonev_io_ibuf \A[3]~input ( - .i(A[3]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\A[3]~input_o )); -// synopsys translate_off -defparam \A[3]~input .bus_hold = "false"; -defparam \A[3]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X59_Y61_N35 -cyclonev_io_ibuf \B[0]~input ( - .i(B[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[0]~input_o )); -// synopsys translate_off -defparam \B[0]~input .bus_hold = "false"; -defparam \B[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X15_Y0_N1 -cyclonev_io_ibuf \B[1]~input ( - .i(B[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[1]~input_o )); -// synopsys translate_off -defparam \B[1]~input .bus_hold = "false"; -defparam \B[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X62_Y61_N92 -cyclonev_io_ibuf \B[2]~input ( - .i(B[2]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\B[2]~input_o )); -// synopsys translate_off -defparam \B[2]~input .bus_hold = "false"; -defparam \B[2]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: IOIBUF_X68_Y37_N55 +// Location: IOIBUF_X6_Y0_N18 cyclonev_io_ibuf \B[3]~input ( .i(B[3]), .ibar(gnd), @@ -316,7 +225,467 @@ defparam \B[3]~input .bus_hold = "false"; defparam \B[3]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LABCELL_X46_Y55_N0 +// Location: IOIBUF_X6_Y0_N35 +cyclonev_io_ibuf \A[3]~input ( + .i(A[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[3]~input_o )); +// synopsys translate_off +defparam \A[3]~input .bus_hold = "false"; +defparam \A[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N35 +cyclonev_io_ibuf \op[2]~input ( + .i(op[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[2]~input_o )); +// synopsys translate_off +defparam \op[2]~input .bus_hold = "false"; +defparam \op[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X2_Y0_N92 +cyclonev_io_ibuf \op[1]~input ( + .i(op[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[1]~input_o )); +// synopsys translate_off +defparam \op[1]~input .bus_hold = "false"; +defparam \op[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N92 +cyclonev_io_ibuf \op[3]~input ( + .i(op[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[3]~input_o )); +// synopsys translate_off +defparam \op[3]~input .bus_hold = "false"; +defparam \op[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N18 +cyclonev_lcell_comb \Mux3~3 ( +// Equation(s): +// \Mux3~3_combout = ( \op[1]~input_o & ( \op[3]~input_o & ( (!\op[0]~input_o & (!\op[2]~input_o & (!\B[3]~input_o $ (!\A[3]~input_o )))) ) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\B[3]~input_o ), + .datac(!\A[3]~input_o ), + .datad(!\op[2]~input_o ), + .datae(!\op[1]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~3 .extended_lut = "off"; +defparam \Mux3~3 .lut_mask = 64'h0000000000002800; +defparam \Mux3~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N1 +cyclonev_io_ibuf \A[0]~input ( + .i(A[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[0]~input_o )); +// synopsys translate_off +defparam \A[0]~input .bus_hold = "false"; +defparam \A[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N41 +cyclonev_io_ibuf \B[0]~input ( + .i(B[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[0]~input_o )); +// synopsys translate_off +defparam \B[0]~input .bus_hold = "false"; +defparam \B[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N30 +cyclonev_lcell_comb \adder_unit|OUT_1[0] ( +// Equation(s): +// \adder_unit|OUT_1 [0] = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC )) +// \adder_unit|_~1 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC )) +// \adder_unit|_~2 = SHARE((\A[0]~input_o & \B[0]~input_o )) + + .dataa(gnd), + .datab(!\A[0]~input_o ), + .datac(!\B[0]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(), + .sumout(\adder_unit|OUT_1 [0]), + .cout(\adder_unit|_~1 ), + .shareout(\adder_unit|_~2 )); +// synopsys translate_off +defparam \adder_unit|OUT_1[0] .extended_lut = "off"; +defparam \adder_unit|OUT_1[0] .lut_mask = 64'h0000030300003C3C; +defparam \adder_unit|OUT_1[0] .shared_arith = "on"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N51 +cyclonev_lcell_comb \Mux3~0 ( +// Equation(s): +// \Mux3~0_combout = (!\op[3]~input_o & !\op[2]~input_o ) + + .dataa(!\op[3]~input_o ), + .datab(!\op[2]~input_o ), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~0 .extended_lut = "off"; +defparam \Mux3~0 .lut_mask = 64'h8888888888888888; +defparam \Mux3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N18 +cyclonev_io_ibuf \B[2]~input ( + .i(B[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[2]~input_o )); +// synopsys translate_off +defparam \B[2]~input .bus_hold = "false"; +defparam \B[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X6_Y0_N1 +cyclonev_io_ibuf \A[2]~input ( + .i(A[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[2]~input_o )); +// synopsys translate_off +defparam \A[2]~input .bus_hold = "false"; +defparam \A[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N58 +cyclonev_io_ibuf \A[1]~input ( + .i(A[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[1]~input_o )); +// synopsys translate_off +defparam \A[1]~input .bus_hold = "false"; +defparam \A[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X4_Y0_N52 +cyclonev_io_ibuf \B[1]~input ( + .i(B[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[1]~input_o )); +// synopsys translate_off +defparam \B[1]~input .bus_hold = "false"; +defparam \B[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N33 +cyclonev_lcell_comb \adder_unit|OUT_1[1] ( +// Equation(s): +// \adder_unit|OUT_1 [1] = SUM(( !\A[1]~input_o $ (!\B[1]~input_o ) ) + ( \adder_unit|_~2 ) + ( \adder_unit|_~1 )) +// \adder_unit|_~7 = CARRY(( !\A[1]~input_o $ (!\B[1]~input_o ) ) + ( \adder_unit|_~2 ) + ( \adder_unit|_~1 )) +// \adder_unit|_~8 = SHARE((\A[1]~input_o & \B[1]~input_o )) + + .dataa(!\A[1]~input_o ), + .datab(gnd), + .datac(!\B[1]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(\adder_unit|_~1 ), + .sharein(\adder_unit|_~2 ), + .combout(), + .sumout(\adder_unit|OUT_1 [1]), + .cout(\adder_unit|_~7 ), + .shareout(\adder_unit|_~8 )); +// synopsys translate_off +defparam \adder_unit|OUT_1[1] .extended_lut = "off"; +defparam \adder_unit|OUT_1[1] .lut_mask = 64'h0000050500005A5A; +defparam \adder_unit|OUT_1[1] .shared_arith = "on"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N36 +cyclonev_lcell_comb \adder_unit|OUT_1[2] ( +// Equation(s): +// \adder_unit|OUT_1 [2] = SUM(( !\B[2]~input_o $ (!\A[2]~input_o ) ) + ( \adder_unit|_~8 ) + ( \adder_unit|_~7 )) +// \adder_unit|_~10 = CARRY(( !\B[2]~input_o $ (!\A[2]~input_o ) ) + ( \adder_unit|_~8 ) + ( \adder_unit|_~7 )) +// \adder_unit|_~11 = SHARE((\B[2]~input_o & \A[2]~input_o )) + + .dataa(gnd), + .datab(gnd), + .datac(!\B[2]~input_o ), + .datad(!\A[2]~input_o ), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(\adder_unit|_~7 ), + .sharein(\adder_unit|_~8 ), + .combout(), + .sumout(\adder_unit|OUT_1 [2]), + .cout(\adder_unit|_~10 ), + .shareout(\adder_unit|_~11 )); +// synopsys translate_off +defparam \adder_unit|OUT_1[2] .extended_lut = "off"; +defparam \adder_unit|OUT_1[2] .lut_mask = 64'h0000000F00000FF0; +defparam \adder_unit|OUT_1[2] .shared_arith = "on"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N39 +cyclonev_lcell_comb \adder_unit|OUT_1[3] ( +// Equation(s): +// \adder_unit|OUT_1 [3] = SUM(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 )) +// \adder_unit|_~13 = CARRY(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 )) +// \adder_unit|_~14 = SHARE((\A[3]~input_o & \B[3]~input_o )) + + .dataa(!\A[3]~input_o ), + .datab(gnd), + .datac(!\B[3]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(\adder_unit|_~10 ), + .sharein(\adder_unit|_~11 ), + .combout(), + .sumout(\adder_unit|OUT_1 [3]), + .cout(\adder_unit|_~13 ), + .shareout(\adder_unit|_~14 )); +// synopsys translate_off +defparam \adder_unit|OUT_1[3] .extended_lut = "off"; +defparam \adder_unit|OUT_1[3] .lut_mask = 64'h0000050500005A5A; +defparam \adder_unit|OUT_1[3] .shared_arith = "on"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N42 +cyclonev_lcell_comb \adder_unit|COUT[0] ( +// Equation(s): +// \adder_unit|COUT [0] = SUM(( GND ) + ( \adder_unit|_~14 ) + ( \adder_unit|_~13 )) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(\adder_unit|_~13 ), + .sharein(\adder_unit|_~14 ), + .combout(), + .sumout(\adder_unit|COUT [0]), + .cout(), + .shareout()); +// synopsys translate_off +defparam \adder_unit|COUT[0] .extended_lut = "off"; +defparam \adder_unit|COUT[0] .lut_mask = 64'h0000000000000000; +defparam \adder_unit|COUT[0] .shared_arith = "on"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N48 +cyclonev_lcell_comb \Mux3~2 ( +// Equation(s): +// \Mux3~2_combout = (\op[3]~input_o & (!\op[2]~input_o & (\op[0]~input_o & \op[1]~input_o ))) + + .dataa(!\op[3]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\op[0]~input_o ), + .datad(!\op[1]~input_o ), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~2 .extended_lut = "off"; +defparam \Mux3~2 .lut_mask = 64'h0004000400040004; +defparam \Mux3~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N24 +cyclonev_lcell_comb \Mux3~1 ( +// Equation(s): +// \Mux3~1_combout = ( \op[2]~input_o & ( !\op[3]~input_o & ( (!\B[0]~input_o & ((!\op[1]~input_o & (\op[0]~input_o & \A[0]~input_o )) # (\op[1]~input_o & (!\op[0]~input_o $ (!\A[0]~input_o ))))) # (\B[0]~input_o & (!\op[1]~input_o $ +// (((!\op[0]~input_o & !\A[0]~input_o ))))) ) ) ) + + .dataa(!\B[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\op[0]~input_o ), + .datad(!\A[0]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~1 .extended_lut = "off"; +defparam \Mux3~1 .lut_mask = 64'h0000166C00000000; +defparam \Mux3~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N54 +cyclonev_lcell_comb \Mux3~4 ( +// Equation(s): +// \Mux3~4_combout = ( \Mux3~2_combout & ( \Mux3~1_combout ) ) # ( !\Mux3~2_combout & ( \Mux3~1_combout ) ) # ( \Mux3~2_combout & ( !\Mux3~1_combout & ( ((!\adder_unit|COUT [0]) # ((\adder_unit|OUT_1 [0] & \Mux3~0_combout ))) # (\Mux3~3_combout ) ) ) +// ) # ( !\Mux3~2_combout & ( !\Mux3~1_combout & ( ((\adder_unit|OUT_1 [0] & \Mux3~0_combout )) # (\Mux3~3_combout ) ) ) ) + + .dataa(!\Mux3~3_combout ), + .datab(!\adder_unit|OUT_1 [0]), + .datac(!\Mux3~0_combout ), + .datad(!\adder_unit|COUT [0]), + .datae(!\Mux3~2_combout ), + .dataf(!\Mux3~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~4 .extended_lut = "off"; +defparam \Mux3~4 .lut_mask = 64'h5757FF57FFFFFFFF; +defparam \Mux3~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N12 +cyclonev_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [1] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[1]~input_o & \B[1]~input_o )) # (\op[1]~input_o & (!\A[1]~input_o +// $ (!\B[1]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[1]~input_o & !\B[1]~input_o ))))))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\B[1]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(!\adder_unit|OUT_1 [1]), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~0 .extended_lut = "on"; +defparam \Mux2~0 .lut_mask = 64'h0F0F166C00000000; +defparam \Mux2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N6 +cyclonev_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [2] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[2]~input_o & \B[2]~input_o )) # (\op[1]~input_o & (!\A[2]~input_o +// $ (!\B[2]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[2]~input_o & !\B[2]~input_o ))))))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\B[2]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(!\adder_unit|OUT_1 [2]), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~0 .extended_lut = "on"; +defparam \Mux1~0 .lut_mask = 64'h0F0F166C00000000; +defparam \Mux1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X7_Y1_N0 +cyclonev_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [3] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[3]~input_o & \B[3]~input_o )) # (\op[1]~input_o & (!\A[3]~input_o +// $ (!\B[3]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[3]~input_o & !\B[3]~input_o ))))))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\A[3]~input_o ), + .datad(!\B[3]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(!\adder_unit|OUT_1 [3]), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~0 .extended_lut = "on"; +defparam \Mux0~0 .lut_mask = 64'h0F0F166C00000000; +defparam \Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X6_Y1_N0 +cyclonev_lcell_comb \adder_unit|OUT_CIN[0] ( +// Equation(s): +// \adder_unit|OUT_CIN [0] = ( \A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) ) # ( !\A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # ( \A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # ( +// !\A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) ) + + .dataa(gnd), + .datab(!\B[3]~input_o ), + .datac(gnd), + .datad(gnd), + .datae(!\A[3]~input_o ), + .dataf(!\adder_unit|OUT_1 [3]), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\adder_unit|OUT_CIN [0]), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \adder_unit|OUT_CIN[0] .extended_lut = "off"; +defparam \adder_unit|OUT_CIN[0] .lut_mask = 64'h3333CCCCCCCC3333; +defparam \adder_unit|OUT_CIN[0] .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X8_Y13_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s): diff --git a/Quartus/A1_Q5/c5_pin_model_dump.txt b/Quartus/A1_Q5/c5_pin_model_dump.txt new file mode 100644 index 0000000..3a3970c --- /dev/null +++ b/Quartus/A1_Q5/c5_pin_model_dump.txt @@ -0,0 +1,88 @@ +io_4iomodule_c5_index: 61gpio_index: 2 +io_4iomodule_c5_index: 62gpio_index: 348 +io_4iomodule_c5_index: 40gpio_index: 6 +io_4iomodule_c5_index: 59gpio_index: 344 +io_4iomodule_c5_index: 31gpio_index: 10 +io_4iomodule_c5_index: 35gpio_index: 340 +io_4iomodule_c5_index: 42gpio_index: 14 +io_4iomodule_c5_index: 19gpio_index: 336 +io_4iomodule_c5_index: 29gpio_index: 19 +io_4iomodule_c5_index: 9gpio_index: 332 +io_4iomodule_c5_index: 34gpio_index: 22 +io_4iomodule_c5_index: 25gpio_index: 328 +io_4iomodule_c5_index: 17gpio_index: 27 +io_4iomodule_c5_index: 44gpio_index: 324 +io_4iomodule_c5_index: 57gpio_index: 30 +io_4iomodule_c5_index: 13gpio_index: 320 +io_4iomodule_c5_index: 5gpio_index: 35 +io_4iomodule_c5_index: 39gpio_index: 316 +io_4iomodule_c5_index: 14gpio_index: 38 +io_4iomodule_c5_index: 27gpio_index: 312 +io_4iomodule_c5_index: 21gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 308 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 26gpio_index: 304 +io_4iomodule_c5_index: 1gpio_index: 51 +io_4iomodule_c5_index: 38gpio_index: 300 +io_4iomodule_c5_index: 50gpio_index: 54 +io_4iomodule_c5_index: 36gpio_index: 296 +io_4iomodule_c5_index: 11gpio_index: 59 +io_4iomodule_c5_index: 2gpio_index: 292 +io_4iomodule_c5_index: 4gpio_index: 62 +io_4iomodule_c5_index: 6gpio_index: 288 +io_4iomodule_c5_index: 48gpio_index: 67 +io_4iomodule_c5_index: 24gpio_index: 284 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 12gpio_index: 280 +io_4iomodule_c5_index: 49gpio_index: 75 +io_4iomodule_c5_index: 63gpio_index: 276 +io_4iomodule_c5_index: 41gpio_index: 78 +io_4iomodule_c5_index: 37gpio_index: 272 +io_4iomodule_c5_index: 3gpio_index: 83 +io_4iomodule_c5_index: 33gpio_index: 268 +io_4iomodule_c5_index: 22gpio_index: 86 +io_4iomodule_c5_index: 54gpio_index: 264 +io_4iomodule_c5_index: 56gpio_index: 91 +io_4iomodule_c5_index: 32gpio_index: 260 +io_4iomodule_c5_index: 53gpio_index: 94 +io_4iomodule_c5_index: 52gpio_index: 256 +io_4iomodule_c5_index: 28gpio_index: 99 +io_4iomodule_c5_index: 45gpio_index: 252 +io_4iomodule_c5_index: 10gpio_index: 102 +io_4iomodule_c5_index: 43gpio_index: 248 +io_4iomodule_c5_index: 15gpio_index: 107 +io_4iomodule_c5_index: 7gpio_index: 244 +io_4iomodule_c5_index: 55gpio_index: 110 +io_4iomodule_c5_index: 60gpio_index: 240 +io_4iomodule_c5_index: 18gpio_index: 115 +io_4iomodule_c5_index: 58gpio_index: 236 +io_4iomodule_c5_index: 46gpio_index: 118 +io_4iomodule_c5_index: 30gpio_index: 232 +io_4iomodule_c5_index: 16gpio_index: 123 +io_4iomodule_c5_index: 47gpio_index: 228 +io_4iomodule_c5_index: 51gpio_index: 126 +io_4iomodule_c5_index: 23gpio_index: 224 +io_4iomodule_h_c5_index: 0gpio_index: 129 +io_4iomodule_h_c5_index: 18gpio_index: 133 +io_4iomodule_h_c5_index: 15gpio_index: 137 +io_4iomodule_h_c5_index: 16gpio_index: 141 +io_4iomodule_h_c5_index: 20gpio_index: 144 +io_4iomodule_h_c5_index: 23gpio_index: 148 +io_4iomodule_h_c5_index: 12gpio_index: 152 +io_4iomodule_h_c5_index: 9gpio_index: 156 +io_4iomodule_h_c5_index: 1gpio_index: 160 +io_4iomodule_h_c5_index: 5gpio_index: 164 +io_4iomodule_h_c5_index: 21gpio_index: 168 +io_4iomodule_h_c5_index: 6gpio_index: 172 +io_4iomodule_h_c5_index: 17gpio_index: 176 +io_4iomodule_h_c5_index: 2gpio_index: 180 +io_4iomodule_h_c5_index: 4gpio_index: 184 +io_4iomodule_h_c5_index: 3gpio_index: 188 +io_4iomodule_h_c5_index: 14gpio_index: 192 +io_4iomodule_h_c5_index: 7gpio_index: 196 +io_4iomodule_h_c5_index: 19gpio_index: 200 +io_4iomodule_h_c5_index: 11gpio_index: 204 +io_4iomodule_h_c5_index: 8gpio_index: 208 +io_4iomodule_h_c5_index: 13gpio_index: 212 +io_4iomodule_h_c5_index: 22gpio_index: 216 +io_4iomodule_h_c5_index: 10gpio_index: 220 diff --git a/Quartus/A1_Q5/db/.cmp.kpt b/Quartus/A1_Q5/db/.cmp.kpt new file mode 100644 index 0000000..d126d82 Binary files /dev/null and b/Quartus/A1_Q5/db/.cmp.kpt differ diff --git a/Quartus/A1_Q5/db/A1_Q5.map_bb.logdb b/Quartus/A1_Q5/db/A1_Q5.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A1_Q5/db/A1_Q5.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A1_Q5/db/shifter.(0).cnf.cdb b/Quartus/A1_Q5/db/shifter.(0).cnf.cdb new file mode 100644 index 0000000..3976864 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.(0).cnf.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.(0).cnf.hdb b/Quartus/A1_Q5/db/shifter.(0).cnf.hdb new file mode 100644 index 0000000..4ac19de Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.(0).cnf.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.asm.qmsg b/Quartus/A1_Q5/db/shifter.asm.qmsg new file mode 100644 index 0000000..d4b946c --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430803604 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:43 2026 " "Processing started: Tue Sep 15 10:06:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430803605 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430803605 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430804252 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430808582 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:48 2026 " "Processing ended: Tue Sep 15 10:06:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430808780 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430808780 ""} diff --git a/Quartus/A1_Q5/db/shifter.asm.rdb b/Quartus/A1_Q5/db/shifter.asm.rdb new file mode 100644 index 0000000..5d0fe9d Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.asm.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cbx.xml b/Quartus/A1_Q5/db/shifter.cbx.xml new file mode 100644 index 0000000..5ffbaaf --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Quartus/A1_Q5/db/shifter.cmp.bpm b/Quartus/A1_Q5/db/shifter.cmp.bpm new file mode 100644 index 0000000..cede5e0 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp.bpm differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.cdb b/Quartus/A1_Q5/db/shifter.cmp.cdb new file mode 100644 index 0000000..12ccafa Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.hdb b/Quartus/A1_Q5/db/shifter.cmp.hdb new file mode 100644 index 0000000..04c759e Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.idb b/Quartus/A1_Q5/db/shifter.cmp.idb new file mode 100644 index 0000000..ee299ad Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp.idb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp.logdb b/Quartus/A1_Q5/db/shifter.cmp.logdb new file mode 100644 index 0000000..9060170 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.cmp.logdb @@ -0,0 +1,70 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;30;0;0;0;0;0;0;0;8;0;0;0;0;8;0;0;0;0;8;0;30;30;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,30;30;30;30;30;0;30;30;30;30;30;30;30;22;30;30;30;30;22;30;30;30;30;22;30;0;0;30, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,OUT_1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,C[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,28, +IO_RULES_SUMMARY,Number of I/O Rules Passed,6, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22, diff --git a/Quartus/A1_Q5/db/shifter.cmp.rdb b/Quartus/A1_Q5/db/shifter.cmp.rdb new file mode 100644 index 0000000..69284a8 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.cmp_merge.kpt b/Quartus/A1_Q5/db/shifter.cmp_merge.kpt new file mode 100644 index 0000000..7b34c2f Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cmp_merge.kpt differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..b19b6d1 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_85c_fast.hsd new file mode 100644 index 0000000..b6ce56d Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ff_85c_fast.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_0c_slow.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..9729dee Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_0c_slow.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..118df22 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q5/db/shifter.db_info b/Quartus/A1_Q5/db/shifter.db_info index 79de92a..21c503d 100644 --- a/Quartus/A1_Q5/db/shifter.db_info +++ b/Quartus/A1_Q5/db/shifter.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Fri Sep 4 13:08:10 2026 +Creation_Time = Tue Sep 15 10:05:43 2026 diff --git a/Quartus/A1_Q5/db/shifter.eda.qmsg b/Quartus/A1_Q5/db/shifter.eda.qmsg new file mode 100644 index 0000000..910dd95 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430816693 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:56 2026 " "Processing started: Tue Sep 15 10:06:56 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430816694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430816694 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430817425 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "shifter.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/ simulation " "Generated file shifter.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430817488 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:57 2026 " "Processing ended: Tue Sep 15 10:06:57 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430817524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430817524 ""} diff --git a/Quartus/A1_Q5/db/shifter.fit.qmsg b/Quartus/A1_Q5/db/shifter.fit.qmsg new file mode 100644 index 0000000..3a99f2c --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.fit.qmsg @@ -0,0 +1,44 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430770929 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430770930 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "shifter 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"shifter\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430770935 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430771006 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430771421 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430771454 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430771502 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "30 30 " "No exact pin location assignment(s) for 30 pins of 30 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430771778 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430778347 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778461 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430778464 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430778464 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430778465 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430778465 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430778465 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430778465 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430778465 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430778465 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430778484 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430784343 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430784344 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430784344 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430784345 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430784346 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430784346 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430784347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430784351 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430784396 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430788050 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430789723 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430790074 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430790074 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430790662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y24 X68_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36"} { { 12 { 0 ""} 57 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430796160 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430796160 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430796398 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430796398 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430796401 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430797416 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797458 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430797888 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430797888 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430798495 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430801226 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1347 " "Peak virtual memory: 1347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:42 2026 " "Processing ended: Tue Sep 15 10:06:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430802055 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430802055 ""} diff --git a/Quartus/A1_Q5/db/shifter.hier_info b/Quartus/A1_Q5/db/shifter.hier_info new file mode 100644 index 0000000..f3e0c16 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.hier_info @@ -0,0 +1,134 @@ +|shifter +op[0] => Mux0.IN8 +op[0] => Mux1.IN8 +op[0] => Mux2.IN8 +op[0] => Mux3.IN8 +op[0] => Mux4.IN8 +op[0] => Mux5.IN8 +op[0] => Mux6.IN8 +op[0] => Mux7.IN8 +op[1] => Mux0.IN7 +op[1] => Mux1.IN7 +op[1] => Mux2.IN7 +op[1] => Mux3.IN7 +op[1] => Mux4.IN7 +op[1] => Mux5.IN7 +op[1] => Mux6.IN7 +op[1] => Mux7.IN7 +op[2] => Mux0.IN6 +op[2] => Mux1.IN6 +op[2] => Mux2.IN6 +op[2] => Mux3.IN6 +op[2] => Mux4.IN6 +op[2] => Mux5.IN6 +op[2] => Mux6.IN6 +op[2] => Mux7.IN6 +A[0] => ShiftLeft0.IN8 +A[0] => ShiftRight0.IN8 +A[0] => ShiftRight1.IN8 +A[0] => ShiftLeft1.IN8 +A[0] => ShiftRight2.IN8 +A[0] => ShiftRight3.IN8 +A[0] => Mux7.IN9 +A[0] => Mux7.IN10 +A[1] => ShiftLeft0.IN7 +A[1] => ShiftRight0.IN7 +A[1] => ShiftRight1.IN7 +A[1] => ShiftLeft1.IN7 +A[1] => ShiftRight2.IN7 +A[1] => ShiftRight3.IN7 +A[1] => Mux6.IN9 +A[1] => Mux6.IN10 +A[2] => ShiftLeft0.IN6 +A[2] => ShiftRight0.IN6 +A[2] => ShiftRight1.IN6 +A[2] => ShiftLeft1.IN6 +A[2] => ShiftRight2.IN6 +A[2] => ShiftRight3.IN6 +A[2] => Mux5.IN9 +A[2] => Mux5.IN10 +A[3] => ShiftLeft0.IN5 +A[3] => ShiftRight0.IN5 +A[3] => ShiftRight1.IN5 +A[3] => ShiftLeft1.IN5 +A[3] => ShiftRight2.IN5 +A[3] => ShiftRight3.IN5 +A[3] => Mux4.IN9 +A[3] => Mux4.IN10 +A[4] => ShiftLeft0.IN4 +A[4] => ShiftRight0.IN4 +A[4] => ShiftRight1.IN4 +A[4] => ShiftLeft1.IN4 +A[4] => ShiftRight2.IN4 +A[4] => ShiftRight3.IN4 +A[4] => Mux3.IN9 +A[4] => Mux3.IN10 +A[5] => ShiftLeft0.IN3 +A[5] => ShiftRight0.IN3 +A[5] => ShiftRight1.IN3 +A[5] => ShiftLeft1.IN3 +A[5] => ShiftRight2.IN3 +A[5] => ShiftRight3.IN3 +A[5] => Mux2.IN9 +A[5] => Mux2.IN10 +A[6] => ShiftLeft0.IN2 +A[6] => ShiftRight0.IN2 +A[6] => ShiftRight1.IN2 +A[6] => ShiftLeft1.IN2 +A[6] => ShiftRight2.IN2 +A[6] => ShiftRight3.IN2 +A[6] => Mux1.IN9 +A[6] => Mux1.IN10 +A[7] => ShiftLeft0.IN1 +A[7] => ShiftRight0.IN1 +A[7] => ShiftRight1.IN0 +A[7] => ShiftRight1.IN1 +A[7] => ShiftLeft1.IN1 +A[7] => ShiftRight2.IN1 +A[7] => ShiftRight3.IN0 +A[7] => ShiftRight3.IN1 +A[7] => Mux0.IN9 +A[7] => Mux0.IN10 +C[0] => ShiftLeft0.IN16 +C[0] => ShiftRight0.IN16 +C[0] => ShiftRight1.IN16 +C[1] => ShiftLeft0.IN15 +C[1] => ShiftRight0.IN15 +C[1] => ShiftRight1.IN15 +C[2] => ShiftLeft0.IN14 +C[2] => ShiftRight0.IN14 +C[2] => ShiftRight1.IN14 +C[3] => ShiftLeft0.IN13 +C[3] => ShiftRight0.IN13 +C[3] => ShiftRight1.IN13 +C[4] => ShiftLeft0.IN12 +C[4] => ShiftRight0.IN12 +C[4] => ShiftRight1.IN12 +C[5] => ShiftLeft0.IN11 +C[5] => ShiftRight0.IN11 +C[5] => ShiftRight1.IN11 +C[6] => ShiftLeft0.IN10 +C[6] => ShiftRight0.IN10 +C[6] => ShiftRight1.IN10 +C[7] => ShiftLeft0.IN9 +C[7] => ShiftRight0.IN9 +C[7] => ShiftRight1.IN9 +B[0] => ShiftLeft1.IN11 +B[0] => ShiftRight2.IN11 +B[0] => ShiftRight3.IN11 +B[1] => ShiftLeft1.IN10 +B[1] => ShiftRight2.IN10 +B[1] => ShiftRight3.IN10 +B[2] => ShiftLeft1.IN9 +B[2] => ShiftRight2.IN9 +B[2] => ShiftRight3.IN9 +OUT_1[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +OUT_1[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/Quartus/A1_Q5/db/shifter.hif b/Quartus/A1_Q5/db/shifter.hif new file mode 100644 index 0000000..a2ea335 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.hif differ diff --git a/Quartus/A1_Q5/db/shifter.lpc.html b/Quartus/A1_Q5/db/shifter.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/Quartus/A1_Q5/db/shifter.lpc.rdb b/Quartus/A1_Q5/db/shifter.lpc.rdb new file mode 100644 index 0000000..7be5d4c Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.lpc.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.lpc.txt b/Quartus/A1_Q5/db/shifter.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A1_Q5/db/shifter.map.ammdb b/Quartus/A1_Q5/db/shifter.map.ammdb new file mode 100644 index 0000000..25b1b34 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.ammdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.bpm b/Quartus/A1_Q5/db/shifter.map.bpm new file mode 100644 index 0000000..e4cbac7 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.bpm differ diff --git a/Quartus/A1_Q5/db/shifter.map.cdb b/Quartus/A1_Q5/db/shifter.map.cdb new file mode 100644 index 0000000..5ed5000 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.hdb b/Quartus/A1_Q5/db/shifter.map.hdb new file mode 100644 index 0000000..3e8e620 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.map.kpt b/Quartus/A1_Q5/db/shifter.map.kpt new file mode 100644 index 0000000..955c790 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.kpt differ diff --git a/Quartus/A1_Q5/db/shifter.map.qmsg b/Quartus/A1_Q5/db/shifter.map.qmsg new file mode 100644 index 0000000..1208da4 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.map.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430758021 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:05:57 2026 " "Processing started: Tue Sep 15 10:05:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430758022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430758022 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430758320 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430758321 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Found entity 1: shifter" { } { { "../../modules/shifter.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430767297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430767297 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter " "Elaborating entity \"shifter\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430767432 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430768701 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430769122 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430769122 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430769167 ""} { "Info" "ICUT_CUT_TM_LCELLS" "85 " "Implemented 85 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430769167 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430769167 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:09 2026 " "Processing ended: Tue Sep 15 10:06:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430769173 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430769173 ""} diff --git a/Quartus/A1_Q5/db/shifter.map.rdb b/Quartus/A1_Q5/db/shifter.map.rdb new file mode 100644 index 0000000..35d36c8 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.cdb b/Quartus/A1_Q5/db/shifter.map_bb.cdb new file mode 100644 index 0000000..e5d06b6 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map_bb.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.map_bb.hdb b/Quartus/A1_Q5/db/shifter.map_bb.hdb new file mode 100644 index 0000000..21bfada Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.map_bb.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.pre_map.hdb b/Quartus/A1_Q5/db/shifter.pre_map.hdb new file mode 100644 index 0000000..5c8fd3b Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.pre_map.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.root_partition.map.reg_db.cdb b/Quartus/A1_Q5/db/shifter.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..3ca2724 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.root_partition.map.reg_db.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.routing.rdb b/Quartus/A1_Q5/db/shifter.routing.rdb new file mode 100644 index 0000000..c06b242 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.routing.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv.hdb b/Quartus/A1_Q5/db/shifter.rtlv.hdb new file mode 100644 index 0000000..8885f64 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.rtlv.hdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb new file mode 100644 index 0000000..d38b2ea Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.rtlv_sg_swap.cdb b/Quartus/A1_Q5/db/shifter.rtlv_sg_swap.cdb new file mode 100644 index 0000000..5e9299c Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.rtlv_sg_swap.cdb differ diff --git a/Quartus/A1_Q5/db/shifter.sld_design_entry_dsc.sci b/Quartus/A1_Q5/db/shifter.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.sld_design_entry_dsc.sci differ diff --git a/Quartus/A1_Q5/db/shifter.smart_action.txt b/Quartus/A1_Q5/db/shifter.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/Quartus/A1_Q5/db/shifter.sta.qmsg b/Quartus/A1_Q5/db/shifter.sta.qmsg new file mode 100644 index 0000000..2fb2152 --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430810263 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:06:49 2026 " "Processing started: Tue Sep 15 10:06:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430810263 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810263 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q5 -c shifter " "Command: quartus_sta A1_Q5 -c shifter" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430810264 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430810318 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430810787 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430810787 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430810861 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "shifter.sdc " "Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430811445 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430811446 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430811446 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430811447 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430811448 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430811452 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430811453 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811454 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811458 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811459 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811460 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430811461 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430811463 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430811501 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430812500 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430812608 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430812608 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430812609 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812610 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812611 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812612 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812613 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430812614 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430812616 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430812867 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430813469 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813518 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813519 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813520 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813521 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813522 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813523 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430813525 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430813673 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430813674 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813675 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813676 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813677 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430813678 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815121 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430815122 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "750 " "Peak virtual memory: 750 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:06:55 2026 " "Processing ended: Tue Sep 15 10:06:55 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430815157 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430815157 ""} diff --git a/Quartus/A1_Q5/db/shifter.sta.rdb b/Quartus/A1_Q5/db/shifter.sta.rdb new file mode 100644 index 0000000..bea46c3 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.sta.rdb differ diff --git a/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb new file mode 100644 index 0000000..bbfea3d Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q5/db/shifter.tis_db_list.ddb b/Quartus/A1_Q5/db/shifter.tis_db_list.ddb new file mode 100644 index 0000000..06ddd4e Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tis_db_list.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb new file mode 100644 index 0000000..adc4878 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb new file mode 100644 index 0000000..406700f Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb new file mode 100644 index 0000000..e4573dc Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb new file mode 100644 index 0000000..fd2ebcf Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb new file mode 100644 index 0000000..ff330e9 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb new file mode 100644 index 0000000..6588c1f Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q5/db/shifter.tmw_info b/Quartus/A1_Q5/db/shifter.tmw_info new file mode 100644 index 0000000..ab250eb --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:02 +start_analysis_synthesis:s:00:00:13-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:33-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation +start_eda_netlist_writer:s:00:00:03-start_full_compilation diff --git a/Quartus/A1_Q5/db/shifter.vpr.ammdb b/Quartus/A1_Q5/db/shifter.vpr.ammdb new file mode 100644 index 0000000..cae37eb Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.vpr.ammdb differ diff --git a/Quartus/A1_Q5/db/shifter_partition_pins.json b/Quartus/A1_Q5/db/shifter_partition_pins.json new file mode 100644 index 0000000..753304c --- /dev/null +++ b/Quartus/A1_Q5/db/shifter_partition_pins.json @@ -0,0 +1,129 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "OUT_1[0]", + "strict" : false + }, + { + "name" : "OUT_1[1]", + "strict" : false + }, + { + "name" : "OUT_1[2]", + "strict" : false + }, + { + "name" : "OUT_1[3]", + "strict" : false + }, + { + "name" : "OUT_1[4]", + "strict" : false + }, + { + "name" : "OUT_1[5]", + "strict" : false + }, + { + "name" : "OUT_1[6]", + "strict" : false + }, + { + "name" : "OUT_1[7]", + "strict" : false + }, + { + "name" : "op[0]", + "strict" : false + }, + { + "name" : "A[0]", + "strict" : false + }, + { + "name" : "op[2]", + "strict" : false + }, + { + "name" : "op[1]", + "strict" : false + }, + { + "name" : "C[2]", + "strict" : false + }, + { + "name" : "C[3]", + "strict" : false + }, + { + "name" : "C[4]", + "strict" : false + }, + { + "name" : "C[5]", + "strict" : false + }, + { + "name" : "C[6]", + "strict" : false + }, + { + "name" : "C[7]", + "strict" : false + }, + { + "name" : "A[7]", + "strict" : false + }, + { + "name" : "C[0]", + "strict" : false + }, + { + "name" : "C[1]", + "strict" : false + }, + { + "name" : "A[6]", + "strict" : false + }, + { + "name" : "A[4]", + "strict" : false + }, + { + "name" : "A[5]", + "strict" : false + }, + { + "name" : "A[2]", + "strict" : false + }, + { + "name" : "A[1]", + "strict" : false + }, + { + "name" : "A[3]", + "strict" : false + }, + { + "name" : "B[2]", + "strict" : false + }, + { + "name" : "B[0]", + "strict" : false + }, + { + "name" : "B[1]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/Quartus/A1_Q5/incremental_db/README b/Quartus/A1_Q5/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/Quartus/A1_Q5/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.db_info b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.db_info new file mode 100644 index 0000000..495b5f2 --- /dev/null +++ b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Tue Sep 15 10:06:07 2026 diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb new file mode 100644 index 0000000..2ea8512 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb new file mode 100644 index 0000000..8f9fcbe Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.dfp b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.dfp differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb new file mode 100644 index 0000000..ec3c1e0 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb new file mode 100644 index 0000000..b0cba88 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.sig b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb new file mode 100644 index 0000000..8b0d586 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.logdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb new file mode 100644 index 0000000..1140261 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb new file mode 100644 index 0000000..0041519 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi new file mode 100644 index 0000000..299e850 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.dpi differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..7211204 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hb_info b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hb_info differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..97d1f57 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.sig b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb new file mode 100644 index 0000000..06f3b87 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.kpt b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.kpt new file mode 100644 index 0000000..b3b314f Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.root_partition.map.kpt differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb new file mode 100644 index 0000000..053a0b9 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrp.hdb differ diff --git a/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb new file mode 100644 index 0000000..0a75dc7 Binary files /dev/null and b/Quartus/A1_Q5/incremental_db/compiled_partitions/shifter.rrs.cdb differ diff --git a/Quartus/A1_Q5/output_files/shifter.asm.rpt b/Quartus/A1_Q5/output_files/shifter.asm.rpt new file mode 100644 index 0000000..1f227bb --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for shifter +Tue Sep 15 10:06:48 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: shifter.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Sep 15 10:06:48 2026 ; +; Revision Name ; shifter ; +; Top-level Entity Name ; shifter ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++---------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------------------------------------------------+ +; File Name ; ++---------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/output_files/shifter.sof ; ++---------------------------------------------------------------------------------+ + + ++---------------------------------------+ +; Assembler Device Options: shifter.sof ; ++----------------+----------------------+ +; Option ; Setting ; ++----------------+----------------------+ +; JTAG usercode ; 0x007990C3 ; +; Checksum ; 0x007990C3 ; ++----------------+----------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:06:43 2026 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 518 megabytes + Info: Processing ended: Tue Sep 15 10:06:48 2026 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/Quartus/A1_Q5/output_files/shifter.done b/Quartus/A1_Q5/output_files/shifter.done new file mode 100644 index 0000000..458a2c6 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.done @@ -0,0 +1 @@ +Tue Sep 15 10:06:58 2026 diff --git a/Quartus/A1_Q5/output_files/shifter.eda.rpt b/Quartus/A1_Q5/output_files/shifter.eda.rpt new file mode 100644 index 0000000..554c950 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for shifter +Tue Sep 15 10:06:57 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:06:57 2026 ; +; Revision Name ; shifter ; +; Top-level Entity Name ; shifter ; +; Family ; Cyclone V ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Tool Name ; Questa Altera FPGA (SystemVerilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/shifter.svo ; ++--------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:06:56 2026 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file shifter.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/simulation/questa/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 670 megabytes + Info: Processing ended: Tue Sep 15 10:06:57 2026 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Quartus/A1_Q5/output_files/shifter.fit.rpt b/Quartus/A1_Q5/output_files/shifter.fit.rpt new file mode 100644 index 0000000..75ccc78 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.fit.rpt @@ -0,0 +1,1751 @@ +Fitter report for shifter +Tue Sep 15 10:06:41 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. I/O Assignment Warnings + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Routing Usage Summary + 20. I/O Rules Summary + 21. I/O Rules Details + 22. I/O Rules Matrix + 23. Fitter Device Options + 24. Operating Settings and Conditions + 25. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Tue Sep 15 10:06:41 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; shifter ; +; Top-level Entity Name ; shifter ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 30 / 364 ( 8 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total RAM Blocks ; 0 / 446 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.6% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; +; -- Achieved ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; 0.00 % ( 0 / 146 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 146 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q5/output_files/shifter.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 48 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 48 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 50 / 29,080 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 0 ; ; +; [b] ALMs used for LUT logic ; 50 ; ; +; [c] ALMs used for registers ; 0 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 2 / 29,080 ; < 1 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 7 / 2,908 ; < 1 % ; +; -- Logic LABs ; 7 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 86 ; ; +; -- 7 input functions ; 3 ; ; +; -- 6 input functions ; 23 ; ; +; -- 5 input functions ; 41 ; ; +; -- 4 input functions ; 9 ; ; +; -- <=3 input functions ; 10 ; ; +; Combinational ALUT usage for route-throughs ; 0 ; ; +; ; ; ; +; Dedicated logic registers ; 0 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58,160 ; 0 % ; +; -- Secondary logic registers ; 0 / 58,160 ; 0 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; ; +; -- Routing optimization registers ; 0 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 30 / 364 ; 8 % ; +; -- Clock pins ; 2 / 14 ; 14 % ; +; -- Dedicated input pins ; 0 / 23 ; 0 % ; +; ; ; ; +; M10K blocks ; 0 / 446 ; 0 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 0 / 4,567,040 ; 0 % ; +; Total block memory implementation bits ; 0 / 4,567,040 ; 0 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 150 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 0 ; ; +; -- Global clocks ; 0 / 16 ; 0 % ; +; -- Quadrant clocks ; 0 / 88 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ; +; SERDES Transmitters ; 0 / 88 ; 0 % ; +; SERDES Receivers ; 0 / 88 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Hard IPs ; 0 / 2 ; 0 % ; +; Standard RX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA RX Deserializers ; 0 / 6 ; 0 % ; +; Standard TX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA TX Serializers ; 0 / 6 ; 0 % ; +; Channel PLLs ; 0 / 6 ; 0 % ; +; Impedance control blocks ; 0 / 3 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; +; Peak interconnect usage (total/H/V) ; 1.0% / 0.9% / 1.3% ; ; +; Maximum fan-out ; 29 ; ; +; Highest non-global fan-out ; 29 ; ; +; Total fan-out ; 462 ; ; +; Average fan-out ; 3.16 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+----------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 48 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 48 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 50 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; +; [b] ALMs used for LUT logic ; 50 ; 0 ; +; [c] ALMs used for registers ; 0 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 2 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 7 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; +; -- Logic LABs ; 7 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 86 ; 0 ; +; -- 7 input functions ; 3 ; 0 ; +; -- 6 input functions ; 23 ; 0 ; +; -- 5 input functions ; 41 ; 0 ; +; -- 4 input functions ; 9 ; 0 ; +; -- <=3 input functions ; 10 ; 0 ; +; Combinational ALUT usage for route-throughs ; 0 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; 0 ; +; -- Routing optimization registers ; 0 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 30 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 0 ; 0 ; +; Total block memory implementation bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 462 ; 0 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 22 ; 0 ; +; -- Output Ports ; 8 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+----------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; A[0] ; N24 ; 6A ; 68 ; 33 ; 3 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[1] ; R26 ; 5B ; 68 ; 24 ; 20 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[2] ; H25 ; 6A ; 68 ; 35 ; 54 ; 11 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[3] ; AB26 ; 5B ; 68 ; 22 ; 77 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[4] ; Y26 ; 5B ; 68 ; 24 ; 54 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[5] ; W25 ; 5B ; 68 ; 26 ; 37 ; 13 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[6] ; Y25 ; 5B ; 68 ; 24 ; 37 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; A[7] ; N25 ; 5B ; 68 ; 27 ; 3 ; 24 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[0] ; U25 ; 5B ; 68 ; 27 ; 37 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[1] ; M24 ; 6A ; 68 ; 33 ; 20 ; 19 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; B[2] ; AA26 ; 5B ; 68 ; 22 ; 94 ; 22 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[0] ; W26 ; 5B ; 68 ; 26 ; 54 ; 15 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[1] ; G26 ; 6A ; 68 ; 33 ; 54 ; 16 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[2] ; P21 ; 5B ; 68 ; 26 ; 3 ; 9 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[3] ; G25 ; 6A ; 68 ; 35 ; 37 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[4] ; J25 ; 6A ; 68 ; 32 ; 77 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[5] ; G24 ; 6A ; 68 ; 41 ; 54 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[6] ; R20 ; 5B ; 68 ; 22 ; 43 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; C[7] ; M21 ; 6A ; 68 ; 32 ; 60 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[0] ; P26 ; 5B ; 68 ; 27 ; 20 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[1] ; J26 ; 6A ; 68 ; 32 ; 94 ; 14 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[2] ; P22 ; 5B ; 68 ; 26 ; 20 ; 29 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; OUT_1[0] ; F26 ; 6A ; 68 ; 33 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[1] ; N23 ; 6A ; 68 ; 35 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[2] ; D26 ; 6A ; 68 ; 37 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[3] ; U26 ; 5B ; 68 ; 27 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[4] ; N20 ; 6A ; 68 ; 32 ; 43 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[5] ; M25 ; 6A ; 68 ; 37 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[6] ; T26 ; 5B ; 68 ; 24 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; OUT_1[7] ; M22 ; 6A ; 68 ; 35 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 15 / 32 ( 47 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 15 / 48 ( 31 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; 396 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; A3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A5 ; 344 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 392 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A11 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 332 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 330 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A21 ; 274 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; 270 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A23 ; 268 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 269 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA14 ; 87 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA26 ; 201 ; 5B ; B[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; AB1 ; 21 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB2 ; 20 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB24 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB25 ; 189 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 199 ; 5B ; A[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; 18 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC4 ; 19 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC8 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC9 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC23 ; 168 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC25 ; 193 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD1 ; 25 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD2 ; 24 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF11 ; 101 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B5 ; 394 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; B6 ; 346 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 350 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B9 ; 314 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 334 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 328 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B14 ; 302 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 304 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; ; 7A ; VREFB7AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B17 ; 298 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 282 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C7 ; 358 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; C9 ; 312 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 318 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; 338 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 336 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 307 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 306 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 280 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 266 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 264 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; C25 ; 253 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C26 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 395 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; D6 ; 352 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 356 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 372 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 340 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 342 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 341 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D15 ; 309 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 293 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 291 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D19 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D20 ; 277 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 275 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D23 ; 262 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D25 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D26 ; 227 ; 6A ; OUT_1[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 354 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 315 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 299 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 285 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; 283 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E21 ; 259 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E23 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E24 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E25 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E26 ; 229 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F16 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F18 ; 301 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F21 ; 260 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 261 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F23 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F24 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F25 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F26 ; 219 ; 6A ; OUT_1[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 329 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 331 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 279 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 281 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G19 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G22 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G24 ; 237 ; 6A ; C[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G25 ; 223 ; 6A ; C[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G26 ; 221 ; 6A ; C[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H5 ; 400 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 263 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H17 ; 273 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 271 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H23 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H24 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 225 ; 6A ; A[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 399 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 287 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J16 ; 265 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J20 ; 254 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 256 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J25 ; 215 ; 6A ; C[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J26 ; 217 ; 6A ; op[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K5 ; 397 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 373 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 363 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 361 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 367 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 305 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K21 ; 248 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K23 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K25 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K26 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L6 ; 393 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L7 ; 371 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 359 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 353 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; 337 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 303 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; 246 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L23 ; 238 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 240 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L26 ; ; 6A ; VREFB6AN0 ; power ; ; ; -- ; ; -- ; -- ; +; M1 ; 5 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M2 ; 4 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M7 ; 391 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; 351 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 345 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 335 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 321 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M21 ; 216 ; 6A ; C[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M22 ; 224 ; 6A ; OUT_1[7] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M24 ; 220 ; 6A ; B[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M25 ; 226 ; 6A ; OUT_1[5] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M26 ; 228 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; 1 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; N8 ; 36 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; N9 ; 343 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; 76 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; 319 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N20 ; 214 ; 6A ; OUT_1[4] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N22 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 222 ; 6A ; OUT_1[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N24 ; 218 ; 6A ; A[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N25 ; 210 ; 5B ; A[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N26 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P1 ; 6 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P2 ; 7 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 200 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 206 ; 5B ; C[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P22 ; 208 ; 5B ; op[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P23 ; 192 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; P26 ; 212 ; 5B ; op[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R20 ; 198 ; 5B ; C[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R21 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R22 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R23 ; 190 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R24 ; 194 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; 196 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R26 ; 204 ; 5B ; A[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; T1 ; 9 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T2 ; 8 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T4 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T19 ; 179 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 182 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 184 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T23 ; 186 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 188 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T26 ; 202 ; 5B ; OUT_1[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; 108 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U25 ; 211 ; 5B ; B[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; U26 ; 213 ; 5B ; OUT_1[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; V1 ; 13 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V2 ; 12 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; 26 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; 10 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W4 ; 11 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W25 ; 207 ; 5B ; A[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; W26 ; 209 ; 5B ; C[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; 203 ; 5B ; A[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; Y26 ; 205 ; 5B ; A[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; OUT_1[0] ; Incomplete set of assignments ; +; OUT_1[1] ; Incomplete set of assignments ; +; OUT_1[2] ; Incomplete set of assignments ; +; OUT_1[3] ; Incomplete set of assignments ; +; OUT_1[4] ; Incomplete set of assignments ; +; OUT_1[5] ; Incomplete set of assignments ; +; OUT_1[6] ; Incomplete set of assignments ; +; OUT_1[7] ; Incomplete set of assignments ; +; op[0] ; Incomplete set of assignments ; +; A[0] ; Incomplete set of assignments ; +; op[2] ; Incomplete set of assignments ; +; op[1] ; Incomplete set of assignments ; +; C[2] ; Incomplete set of assignments ; +; C[3] ; Incomplete set of assignments ; +; C[4] ; Incomplete set of assignments ; +; C[5] ; Incomplete set of assignments ; +; C[6] ; Incomplete set of assignments ; +; C[7] ; Incomplete set of assignments ; +; A[7] ; Incomplete set of assignments ; +; C[0] ; Incomplete set of assignments ; +; C[1] ; Incomplete set of assignments ; +; A[6] ; Incomplete set of assignments ; +; A[4] ; Incomplete set of assignments ; +; A[5] ; Incomplete set of assignments ; +; A[2] ; Incomplete set of assignments ; +; A[1] ; Incomplete set of assignments ; +; A[3] ; Incomplete set of assignments ; +; B[2] ; Incomplete set of assignments ; +; B[0] ; Incomplete set of assignments ; +; B[1] ; Incomplete set of assignments ; +; OUT_1[0] ; Missing location assignment ; +; OUT_1[1] ; Missing location assignment ; +; OUT_1[2] ; Missing location assignment ; +; OUT_1[3] ; Missing location assignment ; +; OUT_1[4] ; Missing location assignment ; +; OUT_1[5] ; Missing location assignment ; +; OUT_1[6] ; Missing location assignment ; +; OUT_1[7] ; Missing location assignment ; +; op[0] ; Missing location assignment ; +; A[0] ; Missing location assignment ; +; op[2] ; Missing location assignment ; +; op[1] ; Missing location assignment ; +; C[2] ; Missing location assignment ; +; C[3] ; Missing location assignment ; +; C[4] ; Missing location assignment ; +; C[5] ; Missing location assignment ; +; C[6] ; Missing location assignment ; +; C[7] ; Missing location assignment ; +; A[7] ; Missing location assignment ; +; C[0] ; Missing location assignment ; +; C[1] ; Missing location assignment ; +; A[6] ; Missing location assignment ; +; A[4] ; Missing location assignment ; +; A[5] ; Missing location assignment ; +; A[2] ; Missing location assignment ; +; A[1] ; Missing location assignment ; +; A[3] ; Missing location assignment ; +; B[2] ; Missing location assignment ; +; B[0] ; Missing location assignment ; +; B[1] ; Missing location assignment ; ++----------+-------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +; |shifter ; 48.0 (48.0) ; 50.0 (50.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 86 (86) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; OUT_1[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; C[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++----------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------+-------------------+---------+ +; op[0] ; ; ; +; - Mux3~2 ; 0 ; 0 ; +; - Mux4~2 ; 0 ; 0 ; +; - Mux7~2 ; 0 ; 0 ; +; - Mux5~1 ; 0 ; 0 ; +; - Mux5~2 ; 0 ; 0 ; +; - Mux5~3 ; 0 ; 0 ; +; - Mux5~4 ; 0 ; 0 ; +; - Mux5~5 ; 0 ; 0 ; +; - Mux6~1 ; 0 ; 0 ; +; - Mux4~1 ; 0 ; 0 ; +; - Mux3~1 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux1~2 ; 0 ; 0 ; +; - Mux1~3 ; 0 ; 0 ; +; - Mux1~4 ; 0 ; 0 ; +; - Mux1~5 ; 0 ; 0 ; +; - Mux1~6 ; 0 ; 0 ; +; - Mux0~0 ; 0 ; 0 ; +; A[0] ; ; ; +; - ShiftRight1~1 ; 0 ; 0 ; +; - ShiftRight3~1 ; 0 ; 0 ; +; - Mux7~2 ; 0 ; 0 ; +; - ShiftLeft1~0 ; 0 ; 0 ; +; - ShiftLeft0~1 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftLeft0~3 ; 0 ; 0 ; +; - ShiftLeft1~2 ; 0 ; 0 ; +; - ShiftLeft0~5 ; 0 ; 0 ; +; - ShiftLeft1~5 ; 0 ; 0 ; +; op[2] ; ; ; +; - Mux3~2 ; 0 ; 0 ; +; - Mux4~2 ; 0 ; 0 ; +; - Mux7~3 ; 0 ; 0 ; +; - Mux7~2 ; 0 ; 0 ; +; - Mux5~0 ; 0 ; 0 ; +; - Mux5~1 ; 0 ; 0 ; +; - Mux5~2 ; 0 ; 0 ; +; - Mux5~3 ; 0 ; 0 ; +; - Mux5~4 ; 0 ; 0 ; +; - Mux5~5 ; 0 ; 0 ; +; - Mux6~1 ; 0 ; 0 ; +; - Mux5~6 ; 0 ; 0 ; +; - Mux5~7 ; 0 ; 0 ; +; - Mux6~3 ; 0 ; 0 ; +; - Mux6~4 ; 0 ; 0 ; +; - Mux5~10 ; 0 ; 0 ; +; - Mux5~11 ; 0 ; 0 ; +; - Mux4~0 ; 0 ; 0 ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux1~1 ; 0 ; 0 ; +; - Mux1~2 ; 0 ; 0 ; +; - Mux1~3 ; 0 ; 0 ; +; - Mux1~4 ; 0 ; 0 ; +; - Mux1~5 ; 0 ; 0 ; +; - Mux1~6 ; 0 ; 0 ; +; - Mux2~2 ; 0 ; 0 ; +; - Mux1~9 ; 0 ; 0 ; +; - Mux0~0 ; 0 ; 0 ; +; op[1] ; ; ; +; - Mux7~3 ; 1 ; 0 ; +; - Mux7~0 ; 1 ; 0 ; +; - Mux5~1 ; 1 ; 0 ; +; - Mux5~4 ; 1 ; 0 ; +; - Mux5~5 ; 1 ; 0 ; +; - Mux6~1 ; 1 ; 0 ; +; - Mux4~1 ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; +; - Mux1~1 ; 1 ; 0 ; +; - Mux1~4 ; 1 ; 0 ; +; - Mux1~5 ; 1 ; 0 ; +; - Mux1~6 ; 1 ; 0 ; +; - Mux0~1 ; 1 ; 0 ; +; C[2] ; ; ; +; - Mux7~0 ; 1 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; - Mux5~2 ; 1 ; 0 ; +; - Mux5~3 ; 1 ; 0 ; +; - ShiftRight0~3 ; 1 ; 0 ; +; - ShiftLeft0~5 ; 1 ; 0 ; +; - Mux1~2 ; 1 ; 0 ; +; - Mux1~3 ; 1 ; 0 ; +; - ShiftLeft0~7 ; 1 ; 0 ; +; C[3] ; ; ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; C[4] ; ; ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; C[5] ; ; ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; C[6] ; ; ; +; - ShiftLeft0~0 ; 1 ; 0 ; +; - ShiftRight0~0 ; 1 ; 0 ; +; C[7] ; ; ; +; - ShiftLeft0~0 ; 0 ; 0 ; +; - ShiftRight0~0 ; 0 ; 0 ; +; A[7] ; ; ; +; - ShiftRight1~0 ; 0 ; 0 ; +; - Mux7~0 ; 0 ; 0 ; +; - ShiftRight3~0 ; 0 ; 0 ; +; - ShiftRight0~1 ; 0 ; 0 ; +; - ShiftRight2~0 ; 0 ; 0 ; +; - Mux6~3 ; 0 ; 0 ; +; - ShiftRight1~3 ; 0 ; 0 ; +; - Mux6~4 ; 0 ; 0 ; +; - ShiftRight0~2 ; 0 ; 0 ; +; - ShiftRight2~1 ; 0 ; 0 ; +; - Mux5~10 ; 0 ; 0 ; +; - ShiftRight1~4 ; 0 ; 0 ; +; - Mux5~11 ; 0 ; 0 ; +; - ShiftRight0~3 ; 0 ; 0 ; +; - ShiftRight2~2 ; 0 ; 0 ; +; - Mux4~0 ; 0 ; 0 ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux2~2 ; 0 ; 0 ; +; - Mux1~9 ; 0 ; 0 ; +; - ShiftLeft0~6 ; 0 ; 0 ; +; - ShiftRight0~4 ; 0 ; 0 ; +; - ShiftLeft1~6 ; 0 ; 0 ; +; - ShiftRight2~4 ; 0 ; 0 ; +; - Mux0~1 ; 0 ; 0 ; +; C[0] ; ; ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight1~1 ; 1 ; 0 ; +; - ShiftRight1~2 ; 1 ; 0 ; +; - Mux5~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - Mux5~7 ; 1 ; 0 ; +; - ShiftRight1~3 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftRight1~4 ; 1 ; 0 ; +; - ShiftLeft0~3 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftLeft0~4 ; 1 ; 0 ; +; - ShiftLeft0~6 ; 1 ; 0 ; +; C[1] ; ; ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight1~1 ; 1 ; 0 ; +; - ShiftRight1~2 ; 1 ; 0 ; +; - Mux5~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftLeft0~1 ; 1 ; 0 ; +; - Mux5~6 ; 1 ; 0 ; +; - ShiftRight1~3 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - ShiftRight1~4 ; 1 ; 0 ; +; - ShiftLeft0~3 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftLeft0~4 ; 1 ; 0 ; +; - Mux1~0 ; 1 ; 0 ; +; - ShiftLeft0~6 ; 1 ; 0 ; +; A[6] ; ; ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftRight2~0 ; 1 ; 0 ; +; - Mux6~3 ; 1 ; 0 ; +; - ShiftRight1~3 ; 1 ; 0 ; +; - ShiftRight0~2 ; 1 ; 0 ; +; - ShiftRight2~1 ; 1 ; 0 ; +; - Mux5~10 ; 1 ; 0 ; +; - ShiftRight1~4 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftRight3~2 ; 1 ; 0 ; +; - Mux1~11 ; 1 ; 0 ; +; - ShiftLeft0~6 ; 1 ; 0 ; +; - ShiftLeft1~6 ; 1 ; 0 ; +; A[4] ; ; ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - Mux6~2 ; 1 ; 0 ; +; - Mux5~9 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftRight3~2 ; 1 ; 0 ; +; - ShiftLeft0~4 ; 1 ; 0 ; +; - ShiftLeft1~4 ; 1 ; 0 ; +; - Mux3~1 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; - Mux1~8 ; 1 ; 0 ; +; - ShiftLeft0~6 ; 1 ; 0 ; +; - ShiftLeft1~6 ; 1 ; 0 ; +; A[5] ; ; ; +; - ShiftRight1~0 ; 1 ; 0 ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftRight0~1 ; 1 ; 0 ; +; - ShiftRight2~0 ; 1 ; 0 ; +; - Mux6~3 ; 1 ; 0 ; +; - ShiftRight1~3 ; 1 ; 0 ; +; - Mux5~9 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftRight3~2 ; 1 ; 0 ; +; - Mux2~4 ; 1 ; 0 ; +; - Mux1~8 ; 1 ; 0 ; +; - ShiftLeft0~6 ; 1 ; 0 ; +; - ShiftLeft1~6 ; 1 ; 0 ; +; A[2] ; ; ; +; - ShiftRight1~1 ; 1 ; 0 ; +; - ShiftRight3~1 ; 1 ; 0 ; +; - Mux6~2 ; 1 ; 0 ; +; - ShiftLeft1~1 ; 1 ; 0 ; +; - ShiftLeft0~2 ; 1 ; 0 ; +; - Mux5~13 ; 1 ; 0 ; +; - ShiftLeft0~3 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftLeft0~4 ; 1 ; 0 ; +; - ShiftLeft1~4 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; A[1] ; ; ; +; - ShiftRight1~1 ; 0 ; 0 ; +; - ShiftRight3~1 ; 0 ; 0 ; +; - ShiftLeft1~0 ; 0 ; 0 ; +; - ShiftLeft0~1 ; 0 ; 0 ; +; - Mux6~6 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftLeft0~2 ; 0 ; 0 ; +; - ShiftLeft0~3 ; 0 ; 0 ; +; - ShiftLeft1~2 ; 0 ; 0 ; +; - ShiftLeft0~4 ; 0 ; 0 ; +; - ShiftLeft1~4 ; 0 ; 0 ; +; A[3] ; ; ; +; - ShiftRight1~1 ; 1 ; 0 ; +; - ShiftRight3~1 ; 1 ; 0 ; +; - Mux6~2 ; 1 ; 0 ; +; - Mux5~9 ; 1 ; 0 ; +; - ShiftLeft0~3 ; 1 ; 0 ; +; - ShiftRight1~5 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftRight3~2 ; 1 ; 0 ; +; - Mux4~1 ; 1 ; 0 ; +; - ShiftLeft0~4 ; 1 ; 0 ; +; - ShiftLeft1~4 ; 1 ; 0 ; +; - Mux2~1 ; 1 ; 0 ; +; - Mux1~8 ; 1 ; 0 ; +; B[2] ; ; ; +; - Mux7~1 ; 1 ; 0 ; +; - Mux5~1 ; 1 ; 0 ; +; - Mux5~3 ; 1 ; 0 ; +; - Mux5~4 ; 1 ; 0 ; +; - Mux5~5 ; 1 ; 0 ; +; - Mux6~1 ; 1 ; 0 ; +; - ShiftLeft1~3 ; 1 ; 0 ; +; - ShiftRight2~2 ; 1 ; 0 ; +; - Mux4~0 ; 1 ; 0 ; +; - ShiftLeft1~5 ; 1 ; 0 ; +; - ShiftRight2~3 ; 1 ; 0 ; +; - Mux3~0 ; 1 ; 0 ; +; - Mux1~1 ; 1 ; 0 ; +; - Mux1~2 ; 1 ; 0 ; +; - Mux1~4 ; 1 ; 0 ; +; - Mux1~5 ; 1 ; 0 ; +; - Mux1~6 ; 1 ; 0 ; +; - Mux2~2 ; 1 ; 0 ; +; - Mux1~9 ; 1 ; 0 ; +; - ShiftLeft1~7 ; 1 ; 0 ; +; - ShiftRight2~4 ; 1 ; 0 ; +; - Mux7~3 ; 1 ; 0 ; +; B[0] ; ; ; +; - Mux7~3 ; 1 ; 0 ; +; - ShiftRight3~0 ; 1 ; 0 ; +; - ShiftRight3~1 ; 1 ; 0 ; +; - Mux5~0 ; 1 ; 0 ; +; - ShiftLeft1~0 ; 1 ; 0 ; +; - ShiftRight2~0 ; 1 ; 0 ; +; - Mux5~7 ; 1 ; 0 ; +; - Mux6~3 ; 1 ; 0 ; +; - ShiftLeft1~1 ; 1 ; 0 ; +; - ShiftRight2~1 ; 1 ; 0 ; +; - Mux5~10 ; 1 ; 0 ; +; - ShiftLeft1~2 ; 1 ; 0 ; +; - ShiftRight3~2 ; 1 ; 0 ; +; - ShiftRight2~2 ; 1 ; 0 ; +; - ShiftLeft1~4 ; 1 ; 0 ; +; - ShiftLeft1~5 ; 1 ; 0 ; +; - ShiftLeft1~6 ; 1 ; 0 ; +; - ShiftRight2~4 ; 1 ; 0 ; +; B[1] ; ; ; +; - Mux7~3 ; 0 ; 0 ; +; - ShiftRight3~0 ; 0 ; 0 ; +; - ShiftRight3~1 ; 0 ; 0 ; +; - Mux5~0 ; 0 ; 0 ; +; - ShiftLeft1~0 ; 0 ; 0 ; +; - ShiftRight2~0 ; 0 ; 0 ; +; - Mux5~6 ; 0 ; 0 ; +; - Mux6~3 ; 0 ; 0 ; +; - ShiftLeft1~1 ; 0 ; 0 ; +; - ShiftRight2~1 ; 0 ; 0 ; +; - Mux5~10 ; 0 ; 0 ; +; - ShiftLeft1~2 ; 0 ; 0 ; +; - ShiftRight3~2 ; 0 ; 0 ; +; - ShiftRight2~2 ; 0 ; 0 ; +; - ShiftLeft1~4 ; 0 ; 0 ; +; - ShiftLeft1~5 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - ShiftLeft1~6 ; 0 ; 0 ; +; - ShiftRight2~4 ; 0 ; 0 ; ++----------------------+-------------------+---------+ + + ++--------------------------------------------------------+ +; Routing Usage Summary ; ++------------------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++------------------------------+-------------------------+ +; Block interconnects ; 142 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 3 / 10,080 ( < 1 % ) ; +; C2 interconnects ; 44 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 22 / 41,360 ( < 1 % ) ; +; DQS bus muxes ; 0 / 21 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; +; Direct links ; 18 / 217,884 ( < 1 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; +; Local interconnects ; 36 / 58,160 ( < 1 % ) ; +; Quadrant clocks ; 0 / 88 ( 0 % ) ; +; R14 interconnects ; 10 / 9,228 ( < 1 % ) ; +; R14/C12 interconnect drivers ; 3 / 15,096 ( < 1 % ) ; +; R3 interconnects ; 66 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 49 / 194,640 ( < 1 % ) ; +; Spine clocks ; 0 / 180 ( 0 % ) ; +; Wire stub REs ; 0 / 11,606 ( 0 % ) ; ++------------------------------+-------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 30 ; 30 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 30 ; 30 ; 30 ; 30 ; 30 ; 0 ; 30 ; 30 ; 30 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 30 ; 30 ; 30 ; 22 ; 30 ; 0 ; 0 ; 30 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; OUT_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; OUT_1[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; C[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CGXFC5C6F27C7 for design "shifter" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 30 pins of 30 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Info (184020): Starting Fitter periphery placement operations +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07 +Critical Warning (332012): Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:04 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y24 to location X68_Y36 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1347 megabytes + Info: Processing ended: Tue Sep 15 10:06:42 2026 + Info: Elapsed time: 00:00:32 + Info: Total CPU time (on all processors): 00:00:48 + + diff --git a/Quartus/A1_Q5/output_files/shifter.fit.summary b/Quartus/A1_Q5/output_files/shifter.fit.summary new file mode 100644 index 0000000..32518c6 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Sep 15 10:06:41 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : shifter +Top-level Entity Name : shifter +Family : Cyclone V +Device : 5CGXFC5C6F27C7 +Timing Models : Final +Logic utilization (in ALMs) : 48 / 29,080 ( < 1 % ) +Total registers : 0 +Total pins : 30 / 364 ( 8 % ) +Total virtual pins : 0 +Total block memory bits : 0 / 4,567,040 ( 0 % ) +Total RAM Blocks : 0 / 446 ( 0 % ) +Total DSP Blocks : 0 / 150 ( 0 % ) +Total HSSI RX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) +Total HSSI TX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) +Total PLLs : 0 / 12 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) diff --git a/Quartus/A1_Q5/output_files/shifter.flow.rpt b/Quartus/A1_Q5/output_files/shifter.flow.rpt new file mode 100644 index 0000000..0ddbe7f --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.flow.rpt @@ -0,0 +1,136 @@ +Flow report for shifter +Tue Sep 15 10:06:57 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Tue Sep 15 10:06:57 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; shifter ; +; Top-level Entity Name ; shifter ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 48 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 30 / 364 ( 8 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 09/15/2026 10:05:58 ; +; Main task ; Compilation ; +; Revision Name ; shifter ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; COMPILER_SIGNATURE_ID ; 253029099468756.178943075805931 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; +; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 413 MB ; 00:00:25 ; +; Fitter ; 00:00:31 ; 1.0 ; 1347 MB ; 00:00:48 ; +; Assembler ; 00:00:05 ; 1.0 ; 518 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 750 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ; +; Total ; 00:00:55 ; -- ; -- ; 00:01:24 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+---------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+---------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ++----------------------+---------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter +quartus_fit --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter +quartus_asm --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter +quartus_sta A1_Q5 -c shifter +quartus_eda --read_settings_files=off --write_settings_files=off A1_Q5 -c shifter + + + diff --git a/Quartus/A1_Q5/output_files/shifter.jdi b/Quartus/A1_Q5/output_files/shifter.jdi new file mode 100644 index 0000000..f79d763 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Quartus/A1_Q5/output_files/shifter.map.rpt b/Quartus/A1_Q5/output_files/shifter.map.rpt new file mode 100644 index 0000000..15eac32 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.map.rpt @@ -0,0 +1,310 @@ +Analysis & Synthesis report for shifter +Tue Sep 15 10:06:09 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Multiplexer Restructuring Statistics (Restructuring Performed) + 10. Parameter Settings for User Entity Instance: Top-level Entity: |shifter + 11. Post-Synthesis Netlist Statistics for Top Partition + 12. Elapsed Time Per Partition + 13. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:06:09 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; shifter ; +; Top-level Entity Name ; shifter ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 0 ; +; Total pins ; 30 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Top-level entity name ; shifter ; shifter ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+ +; ../../modules/shifter.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv ; ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimate of Logic utilization (ALMs needed) ; 56 ; +; ; ; +; Combinational ALUT usage for logic ; 85 ; +; -- 7 input functions ; 3 ; +; -- 6 input functions ; 23 ; +; -- 5 input functions ; 41 ; +; -- 4 input functions ; 9 ; +; -- <=3 input functions ; 9 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 30 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; op[2]~input ; +; Maximum fan-out ; 29 ; +; Total fan-out ; 462 ; +; Average fan-out ; 3.19 ; ++---------------------------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +; |shifter ; 85 (85) ; 0 (0) ; 0 ; 0 ; 30 ; 0 ; |shifter ; shifter ; work ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftLeft0 ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |shifter|ShiftRight2 ; +; 23:1 ; 2 bits ; 30 LEs ; 20 LEs ; 10 LEs ; No ; |shifter|Mux1 ; +; 21:1 ; 2 bits ; 28 LEs ; 20 LEs ; 8 LEs ; No ; |shifter|Mux5 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++-------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |shifter ; ++----------------+-------+------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------+ +; width ; 8 ; Signed Integer ; ++----------------+-------+------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_lcell_comb ; 85 ; +; extend ; 3 ; +; 7 data inputs ; 3 ; +; normal ; 82 ; +; 2 data inputs ; 3 ; +; 3 data inputs ; 6 ; +; 4 data inputs ; 9 ; +; 5 data inputs ; 41 ; +; 6 data inputs ; 23 ; +; boundary_port ; 30 ; +; ; ; +; Max LUT depth ; 4.00 ; +; Average LUT depth ; 3.75 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:05:57 2026 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q5 -c shifter +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv + Info (12023): Found entity 1: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3 +Info (12127): Elaborating entity "shifter" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 115 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 22 input pins + Info (21059): Implemented 8 output pins + Info (21061): Implemented 85 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 430 megabytes + Info: Processing ended: Tue Sep 15 10:06:09 2026 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:25 + + diff --git a/Quartus/A1_Q5/output_files/shifter.map.summary b/Quartus/A1_Q5/output_files/shifter.map.summary new file mode 100644 index 0000000..ed8ac4b --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Sep 15 10:06:09 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : shifter +Top-level Entity Name : shifter +Family : Cyclone V +Logic utilization (in ALMs) : N/A +Total registers : 0 +Total pins : 30 +Total virtual pins : 0 +Total block memory bits : 0 +Total DSP Blocks : 0 +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/Quartus/A1_Q5/output_files/shifter.pin b/Quartus/A1_Q5/output_files/shifter.pin new file mode 100644 index 0000000..39bcb45 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.pin @@ -0,0 +1,750 @@ + -- Copyright (C) 2025 Altera Corporation. All rights reserved. + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, the Altera Quartus Prime License Agreement, + -- the Altera IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Altera and sold by Altera or its authorized distributors. Please + -- refer to the Altera Software License Subscription Agreements + -- on the Quartus Prime software download page. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 3A: 2.5V + -- Bank 3B: 2.5V + -- Bank 4A: 2.5V + -- Bank 5A: 2.5V + -- Bank 5B: 2.5V + -- Bank 6A: 2.5V + -- Bank 7A: 2.5V + -- Bank 8A: 2.5V + -- Bank 9A: Dedicated configuration pins only, no VCCIO required. + -- RREF : External reference resistor for the quad, MUST be connected to + -- GND via a 2k Ohm resistor. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin + -- must not be connected. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +CHIP "shifter" ASSIGNED TO AN: 5CGXFC5C6F27C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +MSEL2 : A2 : : : : 9A : +DNU : A3 : : : : : +DNU : A4 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A : +CONF_DONE : A6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A : +VCCIO7A : A10 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A : +GND : A15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : +VCCIO7A : A20 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A : +GND : A25 : gnd : : : : +GND : AA1 : gnd : : : : +GND : AA2 : gnd : : : : +GXB_NC : AA3 : : : : B0L : +GXB_NC : AA4 : : : : B0L : +GND : AA5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : +VCC_AUX : AA8 : power : : 2.5V : : +VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : +NC : AA12 : : : : : +VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4A : +GND : AA15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : +VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : +VCCIO4A : AA20 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B : +GND : AA25 : gnd : : : : +B[2] : AA26 : input : 2.5 V : : 5B : N +GND : AB1 : : : : B0L : +GND : AB2 : : : : B0L : +GND : AB3 : gnd : : : : +GND : AB4 : gnd : : : : +AS_DATA2, DATA2 : AB5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A : +NC : AB7 : : : : : +GND : AB8 : gnd : : : : +VCCPD3A : AB9 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B : +VCCIO4A : AB13 : power : : 2.5V : 4A : +VCC_AUX : AB14 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : +GND : AB18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A : +VCC_AUX : AB20 : power : : 2.5V : : +VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A : +VCCIO5A : AB23 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : +A[3] : AB26 : input : 2.5 V : : 5B : N +GND : AC1 : gnd : : : : +GND : AC2 : gnd : : : : +GXB_NC : AC3 : : : : B0L : +GXB_NC : AC4 : : : : B0L : +GND : AC5 : gnd : : : : +VCCIO3A : AC6 : power : : 2.5V : 3A : +VREFB3AN0 : AC7 : power : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B : +GND : AC11 : gnd : : : : +VREFB3BN0 : AC12 : power : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : +VCCIO4A : AC16 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A : +GND : AC21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B : +GND : AC26 : gnd : : : : +GND : AD1 : : : : B0L : +GND : AD2 : : : : B0L : +GND : AD3 : gnd : : : : +GND : AD4 : gnd : : : : +AS_DATA1, DATA1 : AD5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : +VCCIO3B : AD9 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A : +GND : AD14 : gnd : : : : +VREFB4AN0 : AD15 : power : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : +VCCIO4A : AD19 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : +GND : AD24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A : +GND : AE1 : gnd : : : : +GND : AE2 : gnd : : : : +GXB_NC : AE3 : : : : B0L : +GXB_NC : AE4 : : : : B0L : +GND : AE5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B : +GND : AE7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : +VCCIO4A : AE12 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : +GND : AE17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : +VCCIO4A : AE22 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A : +GND : AF2 : gnd : : : : +GND : AF3 : gnd : : : : +GND : AF4 : gnd : : : : +AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : +GND : AF10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : +VCCIO4A : AF15 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A : +GND : AF20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : +GND : AF25 : gnd : : : : +RREF : B1 : : : : : +GND : B2 : gnd : : : : +GND : B3 : gnd : : : : +GND : B4 : gnd : : : : +nSTATUS : B5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A : +GND : B8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A : +VCCIO7A : B13 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A : +VREFB7AN0 : B16 : power : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A : +VCCIO7A : B23 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : +GND : C1 : gnd : : : : +GND : C2 : gnd : : : : +NC : C3 : : : : : +NC : C4 : : : : : +GND : C5 : gnd : : : : +VCCIO8A : C6 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A : +VREFB8AN0 : C8 : power : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7A : +GND : C11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A : +VCCIO7A : C16 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A : +GND : C21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A : +DNU : C24 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 6A : +VCCIO6A : C26 : power : : 2.5V : 6A : +NC : D1 : : : : : +NC : D2 : : : : : +GND : D3 : gnd : : : : +GND : D4 : gnd : : : : +nCE : D5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A : +VCCIO8A : D9 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A : +GND : D14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A : +VCCIO7A : D19 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A : +GND : D23 : : : : 7A : +GND : D24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A : +OUT_1[2] : D26 : output : 2.5 V : : 6A : N +GND : E1 : gnd : : : : +GND : E2 : gnd : : : : +NC : E3 : : : : : +NC : E4 : : : : : +GND : E5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A : +GND : E7 : gnd : : : : +VCCBAT : E8 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A : +VCCIO7A : E12 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A : +VCC_AUX : E14 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7A : +GND : E17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6A : +VCCIO6A : E22 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A : +NC : F1 : : : : : +NC : F2 : : : : : +GND : F3 : gnd : : : : +GND : F4 : gnd : : : : +nCONFIG : F5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A : +VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A : +GND : F10 : gnd : : : : +VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A : +VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A : +DNU : F14 : : : : : +VCCIO7A : F15 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A : +VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A : +VCCPD7A8A : F19 : power : : 2.5V : 7A, 8A : +GND : F20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A : +VCCIO6A : F25 : power : : 2.5V : 6A : +OUT_1[0] : F26 : output : 2.5 V : : 6A : N +GND : G1 : gnd : : : : +GND : G2 : gnd : : : : +NC : G3 : : : : : +NC : G4 : : : : : +GND : G5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A : +VCCIO8A : G8 : power : : 2.5V : 8A : +VCC_AUX : G9 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7A : +GND : G13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A : +VCCIO7A : G18 : power : : 2.5V : 7A : +VCC_AUX : G19 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A : +VCCA_FPLL : G21 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A : +GND : G23 : gnd : : : : +C[5] : G24 : input : 2.5 V : : 6A : N +C[3] : G25 : input : 2.5 V : : 6A : N +C[1] : G26 : input : 2.5 V : : 6A : N +NC : H1 : : : : : +NC : H2 : : : : : +GND : H3 : gnd : : : : +GND : H4 : gnd : : : : +GND : H5 : : : : 9A : +GND : H6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A : +VCCIO7A : H11 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A : +GND : H16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A : +VCCIO6A : H21 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A : +A[2] : H25 : input : 2.5 V : : 6A : N +GND : H26 : gnd : : : : +GND : J1 : gnd : : : : +GND : J2 : gnd : : : : +VCCL_GXBL : J3 : power : : 1.1V : : +GND : J4 : gnd : : : : +MSEL4 : J5 : : : : 9A : +VCCA_FPLL : J6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A : +GND : J9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7A : +VCC : J13 : power : : 1.1V : : +GND : J14 : gnd : : : : +VCC : J15 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7A : +VCC : J17 : power : : 1.1V : : +GND : J18 : gnd : : : : +VCC : J19 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A : +VCCPD6A : J22 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A : +VCCIO6A : J24 : power : : 2.5V : 6A : +C[4] : J25 : input : 2.5 V : : 6A : N +op[1] : J26 : input : 2.5 V : : 6A : N +GXB_NC : K1 : : : : B1L : +GXB_NC : K2 : : : : B1L : +GND : K3 : gnd : : : : +VCCE_GXBL : K4 : power : : 1.1V : : +MSEL3 : K5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 8A : +VCCIO8A : K7 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCC : K14 : power : : 1.1V : : +GND : K15 : gnd : : : : +VCC : K16 : power : : 1.1V : : +GND : K17 : gnd : : : : +VCC : K18 : power : : 1.1V : : +GND : K19 : gnd : : : : +VCC : K20 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A : +GND : K22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : +GND : L1 : gnd : : : : +GND : L2 : gnd : : : : +VCCH_GXBL : L3 : power : : 2.5V : : +GND : L4 : gnd : : : : +NC : L5 : : : : : +MSEL1 : L6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 8A : +GND : L10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 7A : +VCC : L13 : power : : 1.1V : : +GND : L14 : gnd : : : : +VCC : L15 : power : : 1.1V : : +GND : L16 : gnd : : : : +VCC : L17 : power : : 1.1V : : +GND : L18 : gnd : : : : +VCC : L19 : power : : 1.1V : : +GND : L20 : gnd : : : : +VCCPD6A : L21 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A : +GND : L25 : gnd : : : : +VREFB6AN0 : L26 : power : : : 6A : +GND : M1 : : : : B1L : +GND : M2 : : : : B1L : +GND : M3 : gnd : : : : +VCCE_GXBL : M4 : power : : 1.1V : : +GND : M5 : gnd : : : : +NC : M6 : : : : : +MSEL0 : M7 : : : : 9A : +GND : M8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 7A : +GND : M13 : gnd : : : : +VCC : M14 : power : : 1.1V : : +GND : M15 : gnd : : : : +VCC : M16 : power : : 1.1V : : +GND : M17 : gnd : : : : +VCC : M18 : power : : 1.1V : : +GND : M19 : gnd : : : : +VCC : M20 : power : : 1.1V : : +C[7] : M21 : input : 2.5 V : : 6A : N +OUT_1[7] : M22 : output : 2.5 V : : 6A : N +VCCIO6A : M23 : power : : 2.5V : 6A : +B[1] : M24 : input : 2.5 V : : 6A : N +OUT_1[5] : M25 : output : 2.5 V : : 6A : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : +GND : N1 : gnd : : : : +GND : N2 : gnd : : : : +VCCL_GXBL : N3 : power : : 1.1V : : +GND : N4 : gnd : : : : +VCCE_GXBL : N5 : power : : 1.1V : : +GND : N6 : gnd : : : : +GND : N7 : : : : B1L : +DCLK : N8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N10 : : : : 3B : +GND : N11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 7A : +VCC : N13 : power : : 1.1V : : +GND : N14 : gnd : : : : +VCC : N15 : power : : 1.1V : : +GND : N16 : gnd : : : : +VCC : N17 : power : : 1.1V : : +GND : N18 : gnd : : : : +VCC : N19 : power : : 1.1V : : +OUT_1[4] : N20 : output : 2.5 V : : 6A : N +GND : N21 : gnd : : : : +VCCPD5B : N22 : power : : 2.5V : 5B : +OUT_1[1] : N23 : output : 2.5 V : : 6A : N +A[0] : N24 : input : 2.5 V : : 6A : N +A[7] : N25 : input : 2.5 V : : 5B : N +VCCIO5B : N26 : power : : 2.5V : 5B : +GXB_NC : P1 : : : : B1L : +GXB_NC : P2 : : : : B1L : +GND : P3 : gnd : : : : +VCCE_GXBL : P4 : power : : 1.1V : : +GND : P5 : gnd : : : : +GND : P6 : : : : B1L : +GND : P7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A : +GND : P9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B : +GND : P13 : gnd : : : : +VCC : P14 : power : : 1.1V : : +GND : P15 : gnd : : : : +VCC : P16 : power : : 1.1V : : +GND : P17 : gnd : : : : +VCC : P18 : power : : 1.1V : : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B : +C[2] : P21 : input : 2.5 V : : 5B : N +op[2] : P22 : input : 2.5 V : : 5B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B : +GND : P24 : gnd : : : : +VREFB5BN0 : P25 : power : : : 5B : +op[0] : P26 : input : 2.5 V : : 5B : N +GND : R1 : gnd : : : : +GND : R2 : gnd : : : : +VCCH_GXBL : R3 : power : : 2.5V : : +GND : R4 : gnd : : : : +VCCE_GXBL : R5 : power : : 1.1V : : +TMS : R6 : input : : : 3A : +GND : R7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B : +GND : R12 : gnd : : : : +VCC : R13 : power : : 1.1V : : +GND : R14 : gnd : : : : +VCC : R15 : power : : 1.1V : : +GND : R16 : gnd : : : : +VCC : R17 : power : : 1.1V : : +GND : R18 : gnd : : : : +VCC : R19 : power : : 1.1V : : +C[6] : R20 : input : 2.5 V : : 5B : N +VCCPD5B : R21 : power : : 2.5V : 5B : +VCCIO5B : R22 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B : +A[1] : R26 : input : 2.5 V : : 5B : N +GND : T1 : : : : B1L : +GND : T2 : : : : B1L : +GND : T3 : gnd : : : : +VCCH_GXBL : T4 : power : : 2.5V : : +GND : T5 : gnd : : : : +TDI : T6 : input : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B : +GND : T10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B : +VCC : T14 : power : : 1.1V : : +GND : T15 : gnd : : : : +VCC : T16 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 4A : +VCC : T18 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5A : +GND : T20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B : +VCCIO5B : T25 : power : : 2.5V : 5B : +OUT_1[6] : T26 : output : 2.5 V : : 5B : N +GND : U1 : gnd : : : : +GND : U2 : gnd : : : : +VCCL_GXBL : U3 : power : : 1.1V : : +GND : U4 : gnd : : : : +VCCE_GXBL : U5 : power : : 1.1V : : +AS_DATA3, DATA3 : U6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : +VCCIO3B : U8 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A : +GND : U13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : +VCCIO4A : U18 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : +VCCPD5A : U21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : +GND : U23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B : +B[0] : U25 : input : 2.5 V : : 5B : N +OUT_1[3] : U26 : output : 2.5 V : : 5B : N +GND : V1 : : : : B1L : +GND : V2 : : : : B1L : +GND : V3 : gnd : : : : +GND : V4 : gnd : : : : +GND : V5 : gnd : : : : +GND : V6 : : : : B0L : +TDO : V7 : output : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : +VCCIO3B : V11 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A : +GND : V16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A : +VCCIO5A : V21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : +GND : V26 : gnd : : : : +GND : W1 : gnd : : : : +GND : W2 : gnd : : : : +GXB_NC : W3 : : : : B1L : +GXB_NC : W4 : : : : B1L : +GND : W5 : gnd : : : : +GND : W6 : : : : B0L : +VCCA_FPLL : W7 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : +GND : W9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : +VCCIO4A : W14 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A : +GND : W19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A : +VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : +VREFB5AN0 : W23 : power : : : 5A : +VCCIO5B : W24 : power : : 2.5V : 5B : +A[5] : W25 : input : 2.5 V : : 5B : N +C[0] : W26 : input : 2.5 V : : 5B : N +GND : Y1 : : : : B0L : +GND : Y2 : : : : B0L : +GND : Y3 : gnd : : : : +GND : Y4 : gnd : : : : +TCK : Y5 : input : : : 3A : +nCSO, DATA4 : Y6 : : : : 3A : +VCCIO3A : Y7 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : +VCCIO4A : Y17 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : +VCCA_FPLL : Y21 : power : : 2.5V : : +GND : Y22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : +A[6] : Y25 : input : 2.5 V : : 5B : N +A[4] : Y26 : input : 2.5 V : : 5B : N diff --git a/Quartus/A1_Q5/output_files/shifter.sld b/Quartus/A1_Q5/output_files/shifter.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.sld @@ -0,0 +1 @@ + diff --git a/Quartus/A1_Q5/output_files/shifter.sof b/Quartus/A1_Q5/output_files/shifter.sof new file mode 100644 index 0000000..bfcdd4d Binary files /dev/null and b/Quartus/A1_Q5/output_files/shifter.sof differ diff --git a/Quartus/A1_Q5/output_files/shifter.sta.rpt b/Quartus/A1_Q5/output_files/shifter.sta.rpt new file mode 100644 index 0000000..acdc45e --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.sta.rpt @@ -0,0 +1,593 @@ +Timing Analyzer report for shifter +Tue Sep 15 10:06:55 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1100mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1100mV 85C Model Setup Summary + 8. Slow 1100mV 85C Model Hold Summary + 9. Slow 1100mV 85C Model Recovery Summary + 10. Slow 1100mV 85C Model Removal Summary + 11. Slow 1100mV 85C Model Minimum Pulse Width Summary + 12. Slow 1100mV 85C Model Metastability Summary + 13. Slow 1100mV 0C Model Fmax Summary + 14. Slow 1100mV 0C Model Setup Summary + 15. Slow 1100mV 0C Model Hold Summary + 16. Slow 1100mV 0C Model Recovery Summary + 17. Slow 1100mV 0C Model Removal Summary + 18. Slow 1100mV 0C Model Minimum Pulse Width Summary + 19. Slow 1100mV 0C Model Metastability Summary + 20. Fast 1100mV 85C Model Setup Summary + 21. Fast 1100mV 85C Model Hold Summary + 22. Fast 1100mV 85C Model Recovery Summary + 23. Fast 1100mV 85C Model Removal Summary + 24. Fast 1100mV 85C Model Minimum Pulse Width Summary + 25. Fast 1100mV 85C Model Metastability Summary + 26. Fast 1100mV 0C Model Setup Summary + 27. Fast 1100mV 0C Model Hold Summary + 28. Fast 1100mV 0C Model Recovery Summary + 29. Fast 1100mV 0C Model Removal Summary + 30. Fast 1100mV 0C Model Minimum Pulse Width Summary + 31. Fast 1100mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1100mv 0c Model) + 36. Signal Integrity Metrics (Slow 1100mv 85c Model) + 37. Signal Integrity Metrics (Fast 1100mv 0c Model) + 38. Signal Integrity Metrics (Fast 1100mv 85c Model) + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Unconstrained Input Ports + 44. Unconstrained Output Ports + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; shifter ; +; Device Family ; Cyclone V ; +; Device Name ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.05 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 5.0% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1100mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +--------------------------------------- +; Fast 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Fast 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; OUT_1[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------+ +; Input Transition Times ; ++-------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------+--------------+-----------------+-----------------+ +; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; C[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------+--------------+-----------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; OUT_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; OUT_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; OUT_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; OUT_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 22 ; 22 ; +; Unconstrained Input Port Paths ; 176 ; 176 ; +; Unconstrained Output Ports ; 8 ; 8 ; +; Unconstrained Output Port Paths ; 176 ; 176 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; A[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; C[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; OUT_1[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:06:49 2026 +Info: Command: quartus_sta A1_Q5 -c shifter +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'shifter.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1100mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 750 megabytes + Info: Processing ended: Tue Sep 15 10:06:55 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/Quartus/A1_Q5/output_files/shifter.sta.summary b/Quartus/A1_Q5/output_files/shifter.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/Quartus/A1_Q5/output_files/shifter.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/Quartus/A1_Q5/shifter.qsf b/Quartus/A1_Q5/shifter.qsf index 789b93e..ce8183c 100644 --- a/Quartus/A1_Q5/shifter.qsf +++ b/Quartus/A1_Q5/shifter.qsf @@ -54,4 +54,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q5/simulation/questa/shifter.sft b/Quartus/A1_Q5/simulation/questa/shifter.sft new file mode 100644 index 0000000..dfcc4cf --- /dev/null +++ b/Quartus/A1_Q5/simulation/questa/shifter.sft @@ -0,0 +1 @@ +set tool_name "Questa Altera FPGA (SystemVerilog)" diff --git a/Quartus/A1_Q5/simulation/questa/shifter.svo b/Quartus/A1_Q5/simulation/questa/shifter.svo new file mode 100644 index 0000000..1e491dc --- /dev/null +++ b/Quartus/A1_Q5/simulation/questa/shifter.svo @@ -0,0 +1,2686 @@ +// Copyright (C) 2025 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, the Altera Quartus Prime License Agreement, +// the Altera IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Altera and sold by Altera or its authorized distributors. Please +// refer to the Altera Software License Subscription Agreements +// on the Quartus Prime software download page. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" + +// DATE "09/15/2026 10:06:57" + +// +// Device: Altera 5CGXFC5C6F27C7 Package FBGA672 +// + +// +// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only +// + +`timescale 1 ps/ 1 ps + +module shifter ( + op, + A, + C, + B, + OUT_1); +input logic [2:0] op ; +input logic [7:0] A ; +input logic [7:0] C ; +input logic [2:0] B ; +output logic [7:0] OUT_1 ; + +// Design Ports Information +// OUT_1[0] => Location: PIN_F26, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[1] => Location: PIN_N23, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[2] => Location: PIN_D26, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[3] => Location: PIN_U26, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[4] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[5] => Location: PIN_M25, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[6] => Location: PIN_T26, I/O Standard: 2.5 V, Current Strength: Default +// OUT_1[7] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// op[0] => Location: PIN_P26, I/O Standard: 2.5 V, Current Strength: Default +// A[0] => Location: PIN_N24, I/O Standard: 2.5 V, Current Strength: Default +// op[2] => Location: PIN_P22, I/O Standard: 2.5 V, Current Strength: Default +// op[1] => Location: PIN_J26, I/O Standard: 2.5 V, Current Strength: Default +// C[2] => Location: PIN_P21, I/O Standard: 2.5 V, Current Strength: Default +// C[3] => Location: PIN_G25, I/O Standard: 2.5 V, Current Strength: Default +// C[4] => Location: PIN_J25, I/O Standard: 2.5 V, Current Strength: Default +// C[5] => Location: PIN_G24, I/O Standard: 2.5 V, Current Strength: Default +// C[6] => Location: PIN_R20, I/O Standard: 2.5 V, Current Strength: Default +// C[7] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// A[7] => Location: PIN_N25, I/O Standard: 2.5 V, Current Strength: Default +// C[0] => Location: PIN_W26, I/O Standard: 2.5 V, Current Strength: Default +// C[1] => Location: PIN_G26, I/O Standard: 2.5 V, Current Strength: Default +// A[6] => Location: PIN_Y25, I/O Standard: 2.5 V, Current Strength: Default +// A[4] => Location: PIN_Y26, I/O Standard: 2.5 V, Current Strength: Default +// A[5] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default +// A[2] => Location: PIN_H25, I/O Standard: 2.5 V, Current Strength: Default +// A[1] => Location: PIN_R26, I/O Standard: 2.5 V, Current Strength: Default +// A[3] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default +// B[2] => Location: PIN_AA26, I/O Standard: 2.5 V, Current Strength: Default +// B[0] => Location: PIN_U25, I/O Standard: 2.5 V, Current Strength: Default +// B[1] => Location: PIN_M24, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \B[2]~input_o ; +wire \A[3]~input_o ; +wire \A[1]~input_o ; +wire \A[0]~input_o ; +wire \A[2]~input_o ; +wire \B[1]~input_o ; +wire \B[0]~input_o ; +wire \ShiftRight3~1_combout ; +wire \A[5]~input_o ; +wire \A[6]~input_o ; +wire \A[4]~input_o ; +wire \A[7]~input_o ; +wire \ShiftRight3~0_combout ; +wire \Mux7~1_combout ; +wire \C[1]~input_o ; +wire \C[0]~input_o ; +wire \ShiftRight1~1_combout ; +wire \C[2]~input_o ; +wire \C[4]~input_o ; +wire \C[5]~input_o ; +wire \C[6]~input_o ; +wire \C[7]~input_o ; +wire \C[3]~input_o ; +wire \ShiftLeft0~0_combout ; +wire \ShiftRight1~0_combout ; +wire \op[1]~input_o ; +wire \Mux7~0_combout ; +wire \ShiftRight1~2_combout ; +wire \op[2]~input_o ; +wire \ShiftRight0~0_combout ; +wire \Mux7~3_combout ; +wire \op[0]~input_o ; +wire \Mux7~2_combout ; +wire \Mux5~4_combout ; +wire \Mux5~0_combout ; +wire \Mux5~1_combout ; +wire \ShiftLeft1~0_combout ; +wire \ShiftRight2~0_combout ; +wire \Mux5~2_combout ; +wire \Mux5~3_combout ; +wire \ShiftRight0~1_combout ; +wire \Mux6~0_combout ; +wire \Mux5~5_combout ; +wire \Mux6~1_combout ; +wire \ShiftLeft0~1_combout ; +wire \Mux5~6_combout ; +wire \Mux5~7_combout ; +wire \Mux6~2_combout ; +wire \Mux6~3_combout ; +wire \ShiftRight1~3_combout ; +wire \Mux6~4_combout ; +wire \Mux6~5_combout ; +wire \Mux6~6_combout ; +wire \ShiftRight0~2_combout ; +wire \ShiftRight2~1_combout ; +wire \ShiftLeft1~1_combout ; +wire \Mux5~8_combout ; +wire \ShiftLeft0~2_combout ; +wire \ShiftRight1~4_combout ; +wire \Mux5~10_combout ; +wire \Mux5~11_combout ; +wire \Mux5~9_combout ; +wire \Mux5~12_combout ; +wire \Mux5~13_combout ; +wire \ShiftRight1~5_combout ; +wire \ShiftRight0~3_combout ; +wire \ShiftLeft0~3_combout ; +wire \ShiftLeft1~2_combout ; +wire \ShiftLeft1~3_combout ; +wire \ShiftRight3~2_combout ; +wire \ShiftRight2~2_combout ; +wire \Mux4~2_combout ; +wire \Mux4~0_combout ; +wire \Mux4~1_combout ; +wire \ShiftLeft0~4_combout ; +wire \ShiftLeft0~5_combout ; +wire \ShiftLeft1~4_combout ; +wire \ShiftLeft1~5_combout ; +wire \ShiftRight2~3_combout ; +wire \Mux3~2_combout ; +wire \Mux3~0_combout ; +wire \Mux3~1_combout ; +wire \Mux1~4_combout ; +wire \Mux1~0_combout ; +wire \Mux1~1_combout ; +wire \Mux1~6_combout ; +wire \Mux1~5_combout ; +wire \Mux2~2_combout ; +wire \Mux2~1_combout ; +wire \Mux2~3_combout ; +wire \Mux1~3_combout ; +wire \Mux1~2_combout ; +wire \Mux2~0_combout ; +wire \Mux2~4_combout ; +wire \Mux1~9_combout ; +wire \Mux1~8_combout ; +wire \Mux1~10_combout ; +wire \Mux1~7_combout ; +wire \Mux1~11_combout ; +wire \ShiftRight2~4_combout ; +wire \ShiftLeft1~6_combout ; +wire \ShiftLeft1~7_combout ; +wire \ShiftRight0~4_combout ; +wire \ShiftLeft0~6_combout ; +wire \ShiftLeft0~7_combout ; +wire \Mux0~0_combout ; +wire \Mux0~1_combout ; + + +// Location: IOOBUF_X68_Y33_N39 +cyclonev_io_obuf \OUT_1[0]~output ( + .i(\Mux7~2_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[0]), + .obar()); +// synopsys translate_off +defparam \OUT_1[0]~output .bus_hold = "false"; +defparam \OUT_1[0]~output .open_drain_output = "false"; +defparam \OUT_1[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y35_N5 +cyclonev_io_obuf \OUT_1[1]~output ( + .i(\Mux6~6_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[1]), + .obar()); +// synopsys translate_off +defparam \OUT_1[1]~output .bus_hold = "false"; +defparam \OUT_1[1]~output .open_drain_output = "false"; +defparam \OUT_1[1]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y37_N39 +cyclonev_io_obuf \OUT_1[2]~output ( + .i(\Mux5~13_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[2]), + .obar()); +// synopsys translate_off +defparam \OUT_1[2]~output .bus_hold = "false"; +defparam \OUT_1[2]~output .open_drain_output = "false"; +defparam \OUT_1[2]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y27_N56 +cyclonev_io_obuf \OUT_1[3]~output ( + .i(\Mux4~1_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[3]), + .obar()); +// synopsys translate_off +defparam \OUT_1[3]~output .bus_hold = "false"; +defparam \OUT_1[3]~output .open_drain_output = "false"; +defparam \OUT_1[3]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y32_N45 +cyclonev_io_obuf \OUT_1[4]~output ( + .i(\Mux3~1_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[4]), + .obar()); +// synopsys translate_off +defparam \OUT_1[4]~output .bus_hold = "false"; +defparam \OUT_1[4]~output .open_drain_output = "false"; +defparam \OUT_1[4]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y37_N5 +cyclonev_io_obuf \OUT_1[5]~output ( + .i(\Mux2~4_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[5]), + .obar()); +// synopsys translate_off +defparam \OUT_1[5]~output .bus_hold = "false"; +defparam \OUT_1[5]~output .open_drain_output = "false"; +defparam \OUT_1[5]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y24_N5 +cyclonev_io_obuf \OUT_1[6]~output ( + .i(\Mux1~11_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[6]), + .obar()); +// synopsys translate_off +defparam \OUT_1[6]~output .bus_hold = "false"; +defparam \OUT_1[6]~output .open_drain_output = "false"; +defparam \OUT_1[6]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X68_Y35_N22 +cyclonev_io_obuf \OUT_1[7]~output ( + .i(\Mux0~1_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(OUT_1[7]), + .obar()); +// synopsys translate_off +defparam \OUT_1[7]~output .bus_hold = "false"; +defparam \OUT_1[7]~output .open_drain_output = "false"; +defparam \OUT_1[7]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y22_N95 +cyclonev_io_ibuf \B[2]~input ( + .i(B[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[2]~input_o )); +// synopsys translate_off +defparam \B[2]~input .bus_hold = "false"; +defparam \B[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y22_N78 +cyclonev_io_ibuf \A[3]~input ( + .i(A[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[3]~input_o )); +// synopsys translate_off +defparam \A[3]~input .bus_hold = "false"; +defparam \A[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y24_N21 +cyclonev_io_ibuf \A[1]~input ( + .i(A[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[1]~input_o )); +// synopsys translate_off +defparam \A[1]~input .bus_hold = "false"; +defparam \A[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y33_N4 +cyclonev_io_ibuf \A[0]~input ( + .i(A[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[0]~input_o )); +// synopsys translate_off +defparam \A[0]~input .bus_hold = "false"; +defparam \A[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y35_N55 +cyclonev_io_ibuf \A[2]~input ( + .i(A[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[2]~input_o )); +// synopsys translate_off +defparam \A[2]~input .bus_hold = "false"; +defparam \A[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y33_N21 +cyclonev_io_ibuf \B[1]~input ( + .i(B[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[1]~input_o )); +// synopsys translate_off +defparam \B[1]~input .bus_hold = "false"; +defparam \B[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y27_N38 +cyclonev_io_ibuf \B[0]~input ( + .i(B[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\B[0]~input_o )); +// synopsys translate_off +defparam \B[0]~input .bus_hold = "false"; +defparam \B[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N33 +cyclonev_lcell_comb \ShiftRight3~1 ( +// Equation(s): +// \ShiftRight3~1_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o +// & ( \A[0]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\A[0]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\B[1]~input_o ), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight3~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight3~1 .extended_lut = "off"; +defparam \ShiftRight3~1 .lut_mask = 64'h0F0F00FF33335555; +defparam \ShiftRight3~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y26_N38 +cyclonev_io_ibuf \A[5]~input ( + .i(A[5]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[5]~input_o )); +// synopsys translate_off +defparam \A[5]~input .bus_hold = "false"; +defparam \A[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y24_N38 +cyclonev_io_ibuf \A[6]~input ( + .i(A[6]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[6]~input_o )); +// synopsys translate_off +defparam \A[6]~input .bus_hold = "false"; +defparam \A[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y24_N55 +cyclonev_io_ibuf \A[4]~input ( + .i(A[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[4]~input_o )); +// synopsys translate_off +defparam \A[4]~input .bus_hold = "false"; +defparam \A[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y27_N4 +cyclonev_io_ibuf \A[7]~input ( + .i(A[7]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\A[7]~input_o )); +// synopsys translate_off +defparam \A[7]~input .bus_hold = "false"; +defparam \A[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N15 +cyclonev_lcell_comb \ShiftRight3~0 ( +// Equation(s): +// \ShiftRight3~0_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[7]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[6]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[5]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o +// & ( \A[4]~input_o ) ) ) + + .dataa(!\A[5]~input_o ), + .datab(!\A[6]~input_o ), + .datac(!\A[4]~input_o ), + .datad(!\A[7]~input_o ), + .datae(!\B[0]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight3~0 .extended_lut = "off"; +defparam \ShiftRight3~0 .lut_mask = 64'h0F0F5555333300FF; +defparam \ShiftRight3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N51 +cyclonev_lcell_comb \Mux7~1 ( +// Equation(s): +// \Mux7~1_combout = ( \ShiftRight3~0_combout & ( (\ShiftRight3~1_combout ) # (\B[2]~input_o ) ) ) # ( !\ShiftRight3~0_combout & ( (!\B[2]~input_o & \ShiftRight3~1_combout ) ) ) + + .dataa(gnd), + .datab(!\B[2]~input_o ), + .datac(!\ShiftRight3~1_combout ), + .datad(gnd), + .datae(gnd), + .dataf(!\ShiftRight3~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux7~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux7~1 .extended_lut = "off"; +defparam \Mux7~1 .lut_mask = 64'h0C0C0C0C3F3F3F3F; +defparam \Mux7~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y33_N55 +cyclonev_io_ibuf \C[1]~input ( + .i(C[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[1]~input_o )); +// synopsys translate_off +defparam \C[1]~input .bus_hold = "false"; +defparam \C[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y26_N55 +cyclonev_io_ibuf \C[0]~input ( + .i(C[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[0]~input_o )); +// synopsys translate_off +defparam \C[0]~input .bus_hold = "false"; +defparam \C[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N30 +cyclonev_lcell_comb \ShiftRight1~1 ( +// Equation(s): +// \ShiftRight1~1_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o +// & ( \A[0]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\A[0]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~1 .extended_lut = "off"; +defparam \ShiftRight1~1 .lut_mask = 64'h00FF0F0F33335555; +defparam \ShiftRight1~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y26_N4 +cyclonev_io_ibuf \C[2]~input ( + .i(C[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[2]~input_o )); +// synopsys translate_off +defparam \C[2]~input .bus_hold = "false"; +defparam \C[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y32_N78 +cyclonev_io_ibuf \C[4]~input ( + .i(C[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[4]~input_o )); +// synopsys translate_off +defparam \C[4]~input .bus_hold = "false"; +defparam \C[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y41_N55 +cyclonev_io_ibuf \C[5]~input ( + .i(C[5]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[5]~input_o )); +// synopsys translate_off +defparam \C[5]~input .bus_hold = "false"; +defparam \C[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y22_N44 +cyclonev_io_ibuf \C[6]~input ( + .i(C[6]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[6]~input_o )); +// synopsys translate_off +defparam \C[6]~input .bus_hold = "false"; +defparam \C[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y32_N61 +cyclonev_io_ibuf \C[7]~input ( + .i(C[7]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[7]~input_o )); +// synopsys translate_off +defparam \C[7]~input .bus_hold = "false"; +defparam \C[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y35_N38 +cyclonev_io_ibuf \C[3]~input ( + .i(C[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\C[3]~input_o )); +// synopsys translate_off +defparam \C[3]~input .bus_hold = "false"; +defparam \C[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N36 +cyclonev_lcell_comb \ShiftLeft0~0 ( +// Equation(s): +// \ShiftLeft0~0_combout = ( !\C[7]~input_o & ( !\C[3]~input_o & ( (!\C[4]~input_o & (!\C[5]~input_o & !\C[6]~input_o )) ) ) ) + + .dataa(!\C[4]~input_o ), + .datab(!\C[5]~input_o ), + .datac(!\C[6]~input_o ), + .datad(gnd), + .datae(!\C[7]~input_o ), + .dataf(!\C[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~0 .extended_lut = "off"; +defparam \ShiftLeft0~0 .lut_mask = 64'h8080000000000000; +defparam \ShiftLeft0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N12 +cyclonev_lcell_comb \ShiftRight1~0 ( +// Equation(s): +// \ShiftRight1~0_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[7]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[6]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[5]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o +// & ( \A[4]~input_o ) ) ) + + .dataa(!\A[5]~input_o ), + .datab(!\A[6]~input_o ), + .datac(!\A[7]~input_o ), + .datad(!\A[4]~input_o ), + .datae(!\C[0]~input_o ), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~0 .extended_lut = "off"; +defparam \ShiftRight1~0 .lut_mask = 64'h00FF555533330F0F; +defparam \ShiftRight1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y32_N95 +cyclonev_io_ibuf \op[1]~input ( + .i(op[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[1]~input_o )); +// synopsys translate_off +defparam \op[1]~input .bus_hold = "false"; +defparam \op[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N42 +cyclonev_lcell_comb \Mux7~0 ( +// Equation(s): +// \Mux7~0_combout = ( \ShiftRight1~0_combout & ( \op[1]~input_o & ( (!\ShiftLeft0~0_combout & (((\A[7]~input_o )))) # (\ShiftLeft0~0_combout & (((\C[2]~input_o )) # (\ShiftRight1~1_combout ))) ) ) ) # ( !\ShiftRight1~0_combout & ( \op[1]~input_o & ( +// (!\ShiftLeft0~0_combout & (((\A[7]~input_o )))) # (\ShiftLeft0~0_combout & (\ShiftRight1~1_combout & (!\C[2]~input_o ))) ) ) ) # ( \ShiftRight1~0_combout & ( !\op[1]~input_o & ( (\ShiftLeft0~0_combout & ((\C[2]~input_o ) # (\ShiftRight1~1_combout +// ))) ) ) ) # ( !\ShiftRight1~0_combout & ( !\op[1]~input_o & ( (\ShiftRight1~1_combout & (!\C[2]~input_o & \ShiftLeft0~0_combout )) ) ) ) + + .dataa(!\ShiftRight1~1_combout ), + .datab(!\C[2]~input_o ), + .datac(!\ShiftLeft0~0_combout ), + .datad(!\A[7]~input_o ), + .datae(!\ShiftRight1~0_combout ), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux7~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux7~0 .extended_lut = "off"; +defparam \Mux7~0 .lut_mask = 64'h0404070704F407F7; +defparam \Mux7~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N27 +cyclonev_lcell_comb \ShiftRight1~2 ( +// Equation(s): +// \ShiftRight1~2_combout = ( !\C[0]~input_o & ( !\C[1]~input_o ) ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(!\C[0]~input_o ), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~2 .extended_lut = "off"; +defparam \ShiftRight1~2 .lut_mask = 64'hFFFF000000000000; +defparam \ShiftRight1~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y26_N21 +cyclonev_io_ibuf \op[2]~input ( + .i(op[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[2]~input_o )); +// synopsys translate_off +defparam \op[2]~input .bus_hold = "false"; +defparam \op[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N48 +cyclonev_lcell_comb \ShiftRight0~0 ( +// Equation(s): +// \ShiftRight0~0_combout = ( !\C[7]~input_o & ( !\C[3]~input_o & ( (!\C[2]~input_o & (!\C[5]~input_o & (!\C[4]~input_o & !\C[6]~input_o ))) ) ) ) + + .dataa(!\C[2]~input_o ), + .datab(!\C[5]~input_o ), + .datac(!\C[4]~input_o ), + .datad(!\C[6]~input_o ), + .datae(!\C[7]~input_o ), + .dataf(!\C[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~0 .extended_lut = "off"; +defparam \ShiftRight0~0 .lut_mask = 64'h8000000000000000; +defparam \ShiftRight0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N36 +cyclonev_lcell_comb \Mux7~3 ( +// Equation(s): +// \Mux7~3_combout = ( !\op[2]~input_o & ( (((\ShiftRight1~2_combout & (\ShiftRight0~0_combout ))) # (\op[1]~input_o )) ) ) # ( \op[2]~input_o & ( (((!\B[0]~input_o & (!\B[2]~input_o & !\B[1]~input_o ))) # (\op[1]~input_o )) ) ) + + .dataa(!\ShiftRight1~2_combout ), + .datab(!\B[0]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\op[1]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(!\ShiftRight0~0_combout ), + .cin(gnd), + .sharein(gnd), + .combout(\Mux7~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux7~3 .extended_lut = "on"; +defparam \Mux7~3 .lut_mask = 64'h05FFC0FF05FF00FF; +defparam \Mux7~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: IOIBUF_X68_Y27_N21 +cyclonev_io_ibuf \op[0]~input ( + .i(op[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[0]~input_o )); +// synopsys translate_off +defparam \op[0]~input .bus_hold = "false"; +defparam \op[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N54 +cyclonev_lcell_comb \Mux7~2 ( +// Equation(s): +// \Mux7~2_combout = ( \op[2]~input_o & ( \A[0]~input_o & ( (!\op[0]~input_o & ((\Mux7~3_combout ))) # (\op[0]~input_o & (\Mux7~1_combout )) ) ) ) # ( !\op[2]~input_o & ( \A[0]~input_o & ( (!\op[0]~input_o & ((\Mux7~3_combout ))) # (\op[0]~input_o & +// (\Mux7~0_combout )) ) ) ) # ( \op[2]~input_o & ( !\A[0]~input_o & ( (\Mux7~1_combout & \op[0]~input_o ) ) ) ) # ( !\op[2]~input_o & ( !\A[0]~input_o & ( (\Mux7~0_combout & \op[0]~input_o ) ) ) ) + + .dataa(!\Mux7~1_combout ), + .datab(!\Mux7~0_combout ), + .datac(!\Mux7~3_combout ), + .datad(!\op[0]~input_o ), + .datae(!\op[2]~input_o ), + .dataf(!\A[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux7~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux7~2 .extended_lut = "off"; +defparam \Mux7~2 .lut_mask = 64'h003300550F330F55; +defparam \Mux7~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N33 +cyclonev_lcell_comb \Mux5~4 ( +// Equation(s): +// \Mux5~4_combout = ( \ShiftRight0~0_combout & ( (!\op[1]~input_o & (\op[2]~input_o & ((!\op[0]~input_o ) # (\B[2]~input_o )))) ) ) # ( !\ShiftRight0~0_combout & ( (!\op[1]~input_o & ((!\op[0]~input_o ) # ((!\op[2]~input_o ) # (\B[2]~input_o )))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\ShiftRight0~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~4 .extended_lut = "off"; +defparam \Mux5~4 .lut_mask = 64'hCC8CCC8C008C008C; +defparam \Mux5~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N9 +cyclonev_lcell_comb \Mux5~0 ( +// Equation(s): +// \Mux5~0_combout = ( \B[1]~input_o & ( (!\op[2]~input_o & (!\C[0]~input_o & !\C[1]~input_o )) ) ) # ( !\B[1]~input_o & ( (!\op[2]~input_o & (((!\C[0]~input_o & !\C[1]~input_o )))) # (\op[2]~input_o & (!\B[0]~input_o )) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\B[0]~input_o ), + .datac(!\C[0]~input_o ), + .datad(!\C[1]~input_o ), + .datae(gnd), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~0 .extended_lut = "off"; +defparam \Mux5~0 .lut_mask = 64'hE444E444A000A000; +defparam \Mux5~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N42 +cyclonev_lcell_comb \Mux5~1 ( +// Equation(s): +// \Mux5~1_combout = ( \ShiftRight0~0_combout & ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((\Mux5~0_combout & ((!\op[2]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( !\ShiftRight0~0_combout & ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((\op[2]~input_o & +// (\Mux5~0_combout & !\B[2]~input_o ))) ) ) ) # ( \ShiftRight0~0_combout & ( !\op[1]~input_o & ( (\Mux5~0_combout & (\op[0]~input_o & ((!\op[2]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( !\ShiftRight0~0_combout & ( !\op[1]~input_o & ( (\op[2]~input_o +// & (\Mux5~0_combout & (!\B[2]~input_o & \op[0]~input_o ))) ) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\Mux5~0_combout ), + .datac(!\B[2]~input_o ), + .datad(!\op[0]~input_o ), + .datae(!\ShiftRight0~0_combout ), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~1 .extended_lut = "off"; +defparam \Mux5~1 .lut_mask = 64'h00100032FF10FF32; +defparam \Mux5~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N6 +cyclonev_lcell_comb \ShiftLeft1~0 ( +// Equation(s): +// \ShiftLeft1~0_combout = ( \A[0]~input_o & ( (!\B[1]~input_o & ((\A[1]~input_o ) # (\B[0]~input_o ))) ) ) # ( !\A[0]~input_o & ( (!\B[0]~input_o & (!\B[1]~input_o & \A[1]~input_o )) ) ) + + .dataa(gnd), + .datab(!\B[0]~input_o ), + .datac(!\B[1]~input_o ), + .datad(!\A[1]~input_o ), + .datae(gnd), + .dataf(!\A[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~0 .extended_lut = "off"; +defparam \ShiftLeft1~0 .lut_mask = 64'h00C000C030F030F0; +defparam \ShiftLeft1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N45 +cyclonev_lcell_comb \ShiftRight2~0 ( +// Equation(s): +// \ShiftRight2~0_combout = ( \A[5]~input_o & ( \B[1]~input_o & ( (!\B[0]~input_o & \A[7]~input_o ) ) ) ) # ( !\A[5]~input_o & ( \B[1]~input_o & ( (!\B[0]~input_o & \A[7]~input_o ) ) ) ) # ( \A[5]~input_o & ( !\B[1]~input_o & ( (!\B[0]~input_o ) # +// (\A[6]~input_o ) ) ) ) # ( !\A[5]~input_o & ( !\B[1]~input_o & ( (\A[6]~input_o & \B[0]~input_o ) ) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\B[0]~input_o ), + .datac(!\A[7]~input_o ), + .datad(gnd), + .datae(!\A[5]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~0 .extended_lut = "off"; +defparam \ShiftRight2~0 .lut_mask = 64'h1111DDDD0C0C0C0C; +defparam \ShiftRight2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N0 +cyclonev_lcell_comb \Mux5~2 ( +// Equation(s): +// \Mux5~2_combout = ( \C[2]~input_o & ( (\op[0]~input_o & ((\ShiftLeft0~0_combout ) # (\op[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & ((\ShiftLeft0~0_combout ))) # (\op[2]~input_o & (\op[0]~input_o )) ) ) + + .dataa(!\op[0]~input_o ), + .datab(gnd), + .datac(!\op[2]~input_o ), + .datad(!\ShiftLeft0~0_combout ), + .datae(gnd), + .dataf(!\C[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~2 .extended_lut = "off"; +defparam \Mux5~2 .lut_mask = 64'h05F505F505550555; +defparam \Mux5~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N3 +cyclonev_lcell_comb \Mux5~3 ( +// Equation(s): +// \Mux5~3_combout = ( \C[2]~input_o & ( (!\op[0]~input_o & (((\op[2]~input_o & !\B[2]~input_o )))) # (\op[0]~input_o & (\ShiftLeft0~0_combout & (!\op[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & (((\ShiftLeft0~0_combout )))) # +// (\op[2]~input_o & (!\op[0]~input_o & ((!\B[2]~input_o )))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\ShiftLeft0~0_combout ), + .datac(!\op[2]~input_o ), + .datad(!\B[2]~input_o ), + .datae(gnd), + .dataf(!\C[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~3 .extended_lut = "off"; +defparam \Mux5~3 .lut_mask = 64'h3A303A301A101A10; +defparam \Mux5~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N36 +cyclonev_lcell_comb \ShiftRight0~1 ( +// Equation(s): +// \ShiftRight0~1_combout = ( \C[1]~input_o & ( (\A[7]~input_o & !\C[0]~input_o ) ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & ((\A[5]~input_o ))) # (\C[0]~input_o & (\A[6]~input_o )) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\A[5]~input_o ), + .datad(!\C[0]~input_o ), + .datae(gnd), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~1 .extended_lut = "off"; +defparam \ShiftRight0~1 .lut_mask = 64'h0F550F5533003300; +defparam \ShiftRight0~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N18 +cyclonev_lcell_comb \Mux6~0 ( +// Equation(s): +// \Mux6~0_combout = ( \ShiftRight0~1_combout & ( (!\Mux5~2_combout & (\ShiftLeft1~0_combout & ((\Mux5~3_combout )))) # (\Mux5~2_combout & (((\Mux5~3_combout ) # (\ShiftRight2~0_combout )))) ) ) # ( !\ShiftRight0~1_combout & ( (!\Mux5~2_combout & +// (\ShiftLeft1~0_combout & ((\Mux5~3_combout )))) # (\Mux5~2_combout & (((\ShiftRight2~0_combout & !\Mux5~3_combout )))) ) ) + + .dataa(!\ShiftLeft1~0_combout ), + .datab(!\ShiftRight2~0_combout ), + .datac(!\Mux5~2_combout ), + .datad(!\Mux5~3_combout ), + .datae(gnd), + .dataf(!\ShiftRight0~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~0 .extended_lut = "off"; +defparam \Mux6~0 .lut_mask = 64'h03500350035F035F; +defparam \Mux6~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N30 +cyclonev_lcell_comb \Mux5~5 ( +// Equation(s): +// \Mux5~5_combout = ( \op[1]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\B[2]~input_o ))) ) ) # ( !\op[1]~input_o & ( (!\op[2]~input_o & (\ShiftRight0~0_combout & !\op[0]~input_o )) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\B[2]~input_o ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~5 .extended_lut = "off"; +defparam \Mux5~5 .lut_mask = 64'h0A000A00FFB1FFB1; +defparam \Mux5~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N33 +cyclonev_lcell_comb \Mux6~1 ( +// Equation(s): +// \Mux6~1_combout = ( !\op[1]~input_o & ( (!\op[0]~input_o ) # ((!\op[2]~input_o & ((!\ShiftRight0~0_combout ))) # (\op[2]~input_o & (\B[2]~input_o ))) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\B[2]~input_o ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~1 .extended_lut = "off"; +defparam \Mux6~1 .lut_mask = 64'hFFB1FFB100000000; +defparam \Mux6~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N51 +cyclonev_lcell_comb \ShiftLeft0~1 ( +// Equation(s): +// \ShiftLeft0~1_combout = ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) + + .dataa(gnd), + .datab(!\A[0]~input_o ), + .datac(!\A[1]~input_o ), + .datad(gnd), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~1 .extended_lut = "off"; +defparam \ShiftLeft0~1 .lut_mask = 64'h0F0F000033330000; +defparam \ShiftLeft0~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N24 +cyclonev_lcell_comb \Mux5~6 ( +// Equation(s): +// \Mux5~6_combout = ( \C[1]~input_o & ( (!\op[2]~input_o ) # (\B[1]~input_o ) ) ) # ( !\C[1]~input_o & ( (\B[1]~input_o & \op[2]~input_o ) ) ) + + .dataa(!\B[1]~input_o ), + .datab(gnd), + .datac(!\op[2]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~6_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~6 .extended_lut = "off"; +defparam \Mux5~6 .lut_mask = 64'h05050505F5F5F5F5; +defparam \Mux5~6 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N27 +cyclonev_lcell_comb \Mux5~7 ( +// Equation(s): +// \Mux5~7_combout = ( \B[0]~input_o & ( (\op[2]~input_o ) # (\C[0]~input_o ) ) ) # ( !\B[0]~input_o & ( (\C[0]~input_o & !\op[2]~input_o ) ) ) + + .dataa(gnd), + .datab(gnd), + .datac(!\C[0]~input_o ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~7_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~7 .extended_lut = "off"; +defparam \Mux5~7 .lut_mask = 64'h0F000F000FFF0FFF; +defparam \Mux5~7 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N36 +cyclonev_lcell_comb \Mux6~2 ( +// Equation(s): +// \Mux6~2_combout = ( \A[3]~input_o & ( (!\Mux5~7_combout ) # ((!\Mux5~6_combout & ((\A[2]~input_o ))) # (\Mux5~6_combout & (\A[4]~input_o ))) ) ) # ( !\A[3]~input_o & ( (\Mux5~7_combout & ((!\Mux5~6_combout & ((\A[2]~input_o ))) # (\Mux5~6_combout +// & (\A[4]~input_o )))) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\Mux5~6_combout ), + .datac(!\A[2]~input_o ), + .datad(!\Mux5~7_combout ), + .datae(gnd), + .dataf(!\A[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~2 .extended_lut = "off"; +defparam \Mux6~2 .lut_mask = 64'h001D001DFF1DFF1D; +defparam \Mux6~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N30 +cyclonev_lcell_comb \Mux6~3 ( +// Equation(s): +// \Mux6~3_combout = ( \A[7]~input_o & ( \B[1]~input_o & ( \op[2]~input_o ) ) ) # ( \A[7]~input_o & ( !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[5]~input_o )) # (\B[0]~input_o & ((\A[6]~input_o ))))) ) ) ) # ( !\A[7]~input_o & ( +// !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[5]~input_o )) # (\B[0]~input_o & ((\A[6]~input_o ))))) ) ) ) + + .dataa(!\A[5]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\A[6]~input_o ), + .datad(!\B[0]~input_o ), + .datae(!\A[7]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~3 .extended_lut = "off"; +defparam \Mux6~3 .lut_mask = 64'h1103110300003333; +defparam \Mux6~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N9 +cyclonev_lcell_comb \ShiftRight1~3 ( +// Equation(s): +// \ShiftRight1~3_combout = ( \C[1]~input_o & ( \A[7]~input_o ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & ((\A[5]~input_o ))) # (\C[0]~input_o & (\A[6]~input_o )) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\A[5]~input_o ), + .datad(!\C[0]~input_o ), + .datae(gnd), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~3 .extended_lut = "off"; +defparam \ShiftRight1~3 .lut_mask = 64'h0F550F5533333333; +defparam \ShiftRight1~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N12 +cyclonev_lcell_comb \Mux6~4 ( +// Equation(s): +// \Mux6~4_combout = ( \ShiftRight1~3_combout & ( (!\Mux6~3_combout & (((!\A[7]~input_o & !\ShiftLeft0~0_combout )) # (\op[2]~input_o ))) ) ) # ( !\ShiftRight1~3_combout & ( (!\Mux6~3_combout & (((!\A[7]~input_o ) # (\ShiftLeft0~0_combout )) # +// (\op[2]~input_o ))) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\ShiftLeft0~0_combout ), + .datad(!\Mux6~3_combout ), + .datae(gnd), + .dataf(!\ShiftRight1~3_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~4 .extended_lut = "off"; +defparam \Mux6~4 .lut_mask = 64'hDF00DF00D500D500; +defparam \Mux6~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N51 +cyclonev_lcell_comb \Mux6~5 ( +// Equation(s): +// \Mux6~5_combout = ( \Mux6~4_combout & ( (!\Mux6~1_combout & (!\Mux5~5_combout & ((\Mux6~2_combout )))) # (\Mux6~1_combout & (((\ShiftLeft0~1_combout )))) ) ) # ( !\Mux6~4_combout & ( (!\Mux6~1_combout & (((\Mux6~2_combout )) # (\Mux5~5_combout ))) +// # (\Mux6~1_combout & (((\ShiftLeft0~1_combout )))) ) ) + + .dataa(!\Mux5~5_combout ), + .datab(!\Mux6~1_combout ), + .datac(!\ShiftLeft0~1_combout ), + .datad(!\Mux6~2_combout ), + .datae(gnd), + .dataf(!\Mux6~4_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~5 .extended_lut = "off"; +defparam \Mux6~5 .lut_mask = 64'h47CF47CF038B038B; +defparam \Mux6~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N0 +cyclonev_lcell_comb \Mux6~6 ( +// Equation(s): +// \Mux6~6_combout = ( \Mux6~5_combout & ( (!\Mux5~1_combout & ((!\Mux5~4_combout ) # ((\Mux6~0_combout )))) # (\Mux5~1_combout & (((\A[1]~input_o )))) ) ) # ( !\Mux6~5_combout & ( (!\Mux5~1_combout & (\Mux5~4_combout & (\Mux6~0_combout ))) # +// (\Mux5~1_combout & (((\A[1]~input_o )))) ) ) + + .dataa(!\Mux5~4_combout ), + .datab(!\Mux5~1_combout ), + .datac(!\Mux6~0_combout ), + .datad(!\A[1]~input_o ), + .datae(gnd), + .dataf(!\Mux6~5_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux6~6_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux6~6 .extended_lut = "off"; +defparam \Mux6~6 .lut_mask = 64'h043704378CBF8CBF; +defparam \Mux6~6 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N6 +cyclonev_lcell_comb \ShiftRight0~2 ( +// Equation(s): +// \ShiftRight0~2_combout = ( !\C[1]~input_o & ( (!\C[0]~input_o & (\A[6]~input_o )) # (\C[0]~input_o & ((\A[7]~input_o ))) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(gnd), + .datad(!\C[0]~input_o ), + .datae(gnd), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~2 .extended_lut = "off"; +defparam \ShiftRight0~2 .lut_mask = 64'h5533553300000000; +defparam \ShiftRight0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N15 +cyclonev_lcell_comb \ShiftRight2~1 ( +// Equation(s): +// \ShiftRight2~1_combout = ( !\B[1]~input_o & ( (!\B[0]~input_o & (\A[6]~input_o )) # (\B[0]~input_o & ((\A[7]~input_o ))) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\B[0]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~1 .extended_lut = "off"; +defparam \ShiftRight2~1 .lut_mask = 64'h5353535300000000; +defparam \ShiftRight2~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N39 +cyclonev_lcell_comb \ShiftLeft1~1 ( +// Equation(s): +// \ShiftLeft1~1_combout = ( \B[0]~input_o & ( (!\B[1]~input_o & \A[1]~input_o ) ) ) # ( !\B[0]~input_o & ( (!\B[1]~input_o & ((\A[2]~input_o ))) # (\B[1]~input_o & (\A[0]~input_o )) ) ) + + .dataa(!\B[1]~input_o ), + .datab(!\A[0]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[2]~input_o ), + .datae(gnd), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~1 .extended_lut = "off"; +defparam \ShiftLeft1~1 .lut_mask = 64'h11BB11BB0A0A0A0A; +defparam \ShiftLeft1~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N48 +cyclonev_lcell_comb \Mux5~8 ( +// Equation(s): +// \Mux5~8_combout = ( \ShiftLeft1~1_combout & ( (!\Mux5~2_combout & (((\Mux5~3_combout )))) # (\Mux5~2_combout & ((!\Mux5~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux5~3_combout & (\ShiftRight0~2_combout )))) ) ) # ( !\ShiftLeft1~1_combout & ( +// (\Mux5~2_combout & ((!\Mux5~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux5~3_combout & (\ShiftRight0~2_combout )))) ) ) + + .dataa(!\ShiftRight0~2_combout ), + .datab(!\ShiftRight2~1_combout ), + .datac(!\Mux5~2_combout ), + .datad(!\Mux5~3_combout ), + .datae(gnd), + .dataf(!\ShiftLeft1~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~8_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~8 .extended_lut = "off"; +defparam \Mux5~8 .lut_mask = 64'h0305030503F503F5; +defparam \Mux5~8 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N12 +cyclonev_lcell_comb \ShiftLeft0~2 ( +// Equation(s): +// \ShiftLeft0~2_combout = ( \A[2]~input_o & ( \A[0]~input_o & ( (!\C[0]~input_o ) # ((\A[1]~input_o & !\C[1]~input_o )) ) ) ) # ( !\A[2]~input_o & ( \A[0]~input_o & ( (!\C[1]~input_o & (\A[1]~input_o & \C[0]~input_o )) # (\C[1]~input_o & +// ((!\C[0]~input_o ))) ) ) ) # ( \A[2]~input_o & ( !\A[0]~input_o & ( (!\C[1]~input_o & ((!\C[0]~input_o ) # (\A[1]~input_o ))) ) ) ) # ( !\A[2]~input_o & ( !\A[0]~input_o & ( (\A[1]~input_o & (!\C[1]~input_o & \C[0]~input_o )) ) ) ) + + .dataa(gnd), + .datab(!\A[1]~input_o ), + .datac(!\C[1]~input_o ), + .datad(!\C[0]~input_o ), + .datae(!\A[2]~input_o ), + .dataf(!\A[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~2 .extended_lut = "off"; +defparam \ShiftLeft0~2 .lut_mask = 64'h0030F0300F30FF30; +defparam \ShiftLeft0~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N12 +cyclonev_lcell_comb \ShiftRight1~4 ( +// Equation(s): +// \ShiftRight1~4_combout = ( \C[1]~input_o & ( \A[7]~input_o ) ) # ( !\C[1]~input_o & ( (!\C[0]~input_o & (\A[6]~input_o )) # (\C[0]~input_o & ((\A[7]~input_o ))) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(gnd), + .datad(!\C[0]~input_o ), + .datae(gnd), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~4 .extended_lut = "off"; +defparam \ShiftRight1~4 .lut_mask = 64'h5533553333333333; +defparam \ShiftRight1~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N39 +cyclonev_lcell_comb \Mux5~10 ( +// Equation(s): +// \Mux5~10_combout = ( \B[1]~input_o & ( (\A[7]~input_o & \op[2]~input_o ) ) ) # ( !\B[1]~input_o & ( (\op[2]~input_o & ((!\B[0]~input_o & (\A[6]~input_o )) # (\B[0]~input_o & ((\A[7]~input_o ))))) ) ) + + .dataa(!\A[6]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\B[0]~input_o ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~10_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~10 .extended_lut = "off"; +defparam \Mux5~10 .lut_mask = 64'h0053005300330033; +defparam \Mux5~10 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N15 +cyclonev_lcell_comb \Mux5~11 ( +// Equation(s): +// \Mux5~11_combout = ( \ShiftLeft0~0_combout & ( (!\Mux5~10_combout & ((!\ShiftRight1~4_combout ) # (\op[2]~input_o ))) ) ) # ( !\ShiftLeft0~0_combout & ( (!\Mux5~10_combout & ((!\A[7]~input_o ) # (\op[2]~input_o ))) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\A[7]~input_o ), + .datac(!\ShiftRight1~4_combout ), + .datad(!\Mux5~10_combout ), + .datae(gnd), + .dataf(!\ShiftLeft0~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~11_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~11 .extended_lut = "off"; +defparam \Mux5~11 .lut_mask = 64'hDD00DD00F500F500; +defparam \Mux5~11 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N39 +cyclonev_lcell_comb \Mux5~9 ( +// Equation(s): +// \Mux5~9_combout = ( \A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((\A[3]~input_o ) # (\Mux5~6_combout )))) ) ) # ( !\A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((!\Mux5~6_combout & +// \A[3]~input_o )))) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\Mux5~6_combout ), + .datac(!\A[3]~input_o ), + .datad(!\Mux5~7_combout ), + .datae(gnd), + .dataf(!\A[5]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~9_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~9 .extended_lut = "off"; +defparam \Mux5~9 .lut_mask = 64'h550C550C553F553F; +defparam \Mux5~9 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N48 +cyclonev_lcell_comb \Mux5~12 ( +// Equation(s): +// \Mux5~12_combout = ( \Mux5~9_combout & ( (!\Mux6~1_combout & ((!\Mux5~5_combout ) # ((!\Mux5~11_combout )))) # (\Mux6~1_combout & (((\ShiftLeft0~2_combout )))) ) ) # ( !\Mux5~9_combout & ( (!\Mux6~1_combout & (\Mux5~5_combout & ((!\Mux5~11_combout +// )))) # (\Mux6~1_combout & (((\ShiftLeft0~2_combout )))) ) ) + + .dataa(!\Mux5~5_combout ), + .datab(!\Mux6~1_combout ), + .datac(!\ShiftLeft0~2_combout ), + .datad(!\Mux5~11_combout ), + .datae(gnd), + .dataf(!\Mux5~9_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~12_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~12 .extended_lut = "off"; +defparam \Mux5~12 .lut_mask = 64'h47034703CF8BCF8B; +defparam \Mux5~12 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N3 +cyclonev_lcell_comb \Mux5~13 ( +// Equation(s): +// \Mux5~13_combout = ( \Mux5~12_combout & ( (!\Mux5~1_combout & ((!\Mux5~4_combout ) # ((\Mux5~8_combout )))) # (\Mux5~1_combout & (((\A[2]~input_o )))) ) ) # ( !\Mux5~12_combout & ( (!\Mux5~1_combout & (\Mux5~4_combout & (\Mux5~8_combout ))) # +// (\Mux5~1_combout & (((\A[2]~input_o )))) ) ) + + .dataa(!\Mux5~4_combout ), + .datab(!\Mux5~1_combout ), + .datac(!\Mux5~8_combout ), + .datad(!\A[2]~input_o ), + .datae(gnd), + .dataf(!\Mux5~12_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~13_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~13 .extended_lut = "off"; +defparam \Mux5~13 .lut_mask = 64'h043704378CBF8CBF; +defparam \Mux5~13 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N6 +cyclonev_lcell_comb \ShiftRight1~5 ( +// Equation(s): +// \ShiftRight1~5_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[5]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o +// & ( \A[3]~input_o ) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\A[3]~input_o ), + .datac(!\A[5]~input_o ), + .datad(!\A[6]~input_o ), + .datae(!\C[0]~input_o ), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight1~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight1~5 .extended_lut = "off"; +defparam \ShiftRight1~5 .lut_mask = 64'h333355550F0F00FF; +defparam \ShiftRight1~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N0 +cyclonev_lcell_comb \ShiftRight0~3 ( +// Equation(s): +// \ShiftRight0~3_combout = ( \A[7]~input_o & ( (\ShiftLeft0~0_combout & ((!\C[2]~input_o & (\ShiftRight1~5_combout )) # (\C[2]~input_o & ((\ShiftRight1~2_combout ))))) ) ) # ( !\A[7]~input_o & ( (\ShiftRight1~5_combout & (!\C[2]~input_o & +// \ShiftLeft0~0_combout )) ) ) + + .dataa(!\ShiftRight1~5_combout ), + .datab(!\C[2]~input_o ), + .datac(!\ShiftLeft0~0_combout ), + .datad(!\ShiftRight1~2_combout ), + .datae(gnd), + .dataf(!\A[7]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~3 .extended_lut = "off"; +defparam \ShiftRight0~3 .lut_mask = 64'h0404040404070407; +defparam \ShiftRight0~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N18 +cyclonev_lcell_comb \ShiftLeft0~3 ( +// Equation(s): +// \ShiftLeft0~3_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[2]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & +// ( \A[3]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\A[0]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~3 .extended_lut = "off"; +defparam \ShiftLeft0~3 .lut_mask = 64'h555533330F0F00FF; +defparam \ShiftLeft0~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N21 +cyclonev_lcell_comb \ShiftLeft1~2 ( +// Equation(s): +// \ShiftLeft1~2_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[0]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[2]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & +// ( \A[3]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[1]~input_o ), + .datac(!\A[0]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\B[1]~input_o ), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~2 .extended_lut = "off"; +defparam \ShiftLeft1~2 .lut_mask = 64'h5555333300FF0F0F; +defparam \ShiftLeft1~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N3 +cyclonev_lcell_comb \ShiftLeft1~3 ( +// Equation(s): +// \ShiftLeft1~3_combout = ( !\B[2]~input_o & ( \ShiftLeft1~2_combout ) ) + + .dataa(gnd), + .datab(gnd), + .datac(!\ShiftLeft1~2_combout ), + .datad(gnd), + .datae(gnd), + .dataf(!\B[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~3 .extended_lut = "off"; +defparam \ShiftLeft1~3 .lut_mask = 64'h0F0F0F0F00000000; +defparam \ShiftLeft1~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N9 +cyclonev_lcell_comb \ShiftRight3~2 ( +// Equation(s): +// \ShiftRight3~2_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[5]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o +// & ( \A[3]~input_o ) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\A[3]~input_o ), + .datac(!\A[6]~input_o ), + .datad(!\A[5]~input_o ), + .datae(!\B[0]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight3~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight3~2 .extended_lut = "off"; +defparam \ShiftRight3~2 .lut_mask = 64'h3333555500FF0F0F; +defparam \ShiftRight3~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X67_Y28_N33 +cyclonev_lcell_comb \ShiftRight2~2 ( +// Equation(s): +// \ShiftRight2~2_combout = ( \B[2]~input_o & ( (!\B[0]~input_o & (\A[7]~input_o & !\B[1]~input_o )) ) ) # ( !\B[2]~input_o & ( \ShiftRight3~2_combout ) ) + + .dataa(!\ShiftRight3~2_combout ), + .datab(!\B[0]~input_o ), + .datac(!\A[7]~input_o ), + .datad(!\B[1]~input_o ), + .datae(!\B[2]~input_o ), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~2 .extended_lut = "off"; +defparam \ShiftRight2~2 .lut_mask = 64'h55550C0055550C00; +defparam \ShiftRight2~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N30 +cyclonev_lcell_comb \Mux4~2 ( +// Equation(s): +// \Mux4~2_combout = ( !\op[2]~input_o & ( ((!\op[0]~input_o & (((\ShiftLeft0~3_combout & \ShiftRight0~0_combout )))) # (\op[0]~input_o & (\ShiftRight0~3_combout ))) ) ) # ( \op[2]~input_o & ( (((!\op[0]~input_o & (\ShiftLeft1~3_combout )) # +// (\op[0]~input_o & ((\ShiftRight2~2_combout ))))) ) ) + + .dataa(!\ShiftRight0~3_combout ), + .datab(!\ShiftLeft0~3_combout ), + .datac(!\ShiftLeft1~3_combout ), + .datad(!\ShiftRight2~2_combout ), + .datae(!\op[2]~input_o ), + .dataf(!\op[0]~input_o ), + .datag(!\ShiftRight0~0_combout ), + .cin(gnd), + .sharein(gnd), + .combout(\Mux4~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux4~2 .extended_lut = "on"; +defparam \Mux4~2 .lut_mask = 64'h03030F0F555500FF; +defparam \Mux4~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N45 +cyclonev_lcell_comb \Mux4~0 ( +// Equation(s): +// \Mux4~0_combout = ( \ShiftRight1~5_combout & ( \ShiftRight3~2_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\A[7]~input_o ) ) ) ) # ( !\ShiftRight1~5_combout & ( \ShiftRight3~2_combout & ( +// (!\op[2]~input_o & (!\ShiftRight0~0_combout & ((\A[7]~input_o )))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (\A[7]~input_o )))) ) ) ) # ( \ShiftRight1~5_combout & ( !\ShiftRight3~2_combout & ( (!\op[2]~input_o & (((\A[7]~input_o )) # +// (\ShiftRight0~0_combout ))) # (\op[2]~input_o & (((\B[2]~input_o & \A[7]~input_o )))) ) ) ) # ( !\ShiftRight1~5_combout & ( !\ShiftRight3~2_combout & ( (\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & +// ((\B[2]~input_o ))))) ) ) ) + + .dataa(!\ShiftRight0~0_combout ), + .datab(!\op[2]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\A[7]~input_o ), + .datae(!\ShiftRight1~5_combout ), + .dataf(!\ShiftRight3~2_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux4~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux4~0 .extended_lut = "off"; +defparam \Mux4~0 .lut_mask = 64'h008B44CF30BB74FF; +defparam \Mux4~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N24 +cyclonev_lcell_comb \Mux4~1 ( +// Equation(s): +// \Mux4~1_combout = ( \op[1]~input_o & ( (!\op[0]~input_o & (\A[3]~input_o )) # (\op[0]~input_o & ((\Mux4~0_combout ))) ) ) # ( !\op[1]~input_o & ( \Mux4~2_combout ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\Mux4~2_combout ), + .datac(!\Mux4~0_combout ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux4~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux4~1 .extended_lut = "off"; +defparam \Mux4~1 .lut_mask = 64'h33333333550F550F; +defparam \Mux4~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N54 +cyclonev_lcell_comb \ShiftLeft0~4 ( +// Equation(s): +// \ShiftLeft0~4_combout = ( \C[1]~input_o & ( \C[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\C[1]~input_o & ( \C[0]~input_o & ( \A[3]~input_o ) ) ) # ( \C[1]~input_o & ( !\C[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\C[1]~input_o & ( !\C[0]~input_o & +// ( \A[4]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[4]~input_o ), + .datac(!\A[2]~input_o ), + .datad(!\A[1]~input_o ), + .datae(!\C[1]~input_o ), + .dataf(!\C[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~4 .extended_lut = "off"; +defparam \ShiftLeft0~4 .lut_mask = 64'h33330F0F555500FF; +defparam \ShiftLeft0~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N18 +cyclonev_lcell_comb \ShiftLeft0~5 ( +// Equation(s): +// \ShiftLeft0~5_combout = ( \C[2]~input_o & ( (\ShiftLeft0~0_combout & (\A[0]~input_o & \ShiftRight1~2_combout )) ) ) # ( !\C[2]~input_o & ( (\ShiftLeft0~0_combout & \ShiftLeft0~4_combout ) ) ) + + .dataa(!\ShiftLeft0~0_combout ), + .datab(!\A[0]~input_o ), + .datac(!\ShiftLeft0~4_combout ), + .datad(!\ShiftRight1~2_combout ), + .datae(gnd), + .dataf(!\C[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~5 .extended_lut = "off"; +defparam \ShiftLeft0~5 .lut_mask = 64'h0505050500110011; +defparam \ShiftLeft0~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N57 +cyclonev_lcell_comb \ShiftLeft1~4 ( +// Equation(s): +// \ShiftLeft1~4_combout = ( \B[1]~input_o & ( \B[0]~input_o & ( \A[1]~input_o ) ) ) # ( !\B[1]~input_o & ( \B[0]~input_o & ( \A[3]~input_o ) ) ) # ( \B[1]~input_o & ( !\B[0]~input_o & ( \A[2]~input_o ) ) ) # ( !\B[1]~input_o & ( !\B[0]~input_o & +// ( \A[4]~input_o ) ) ) + + .dataa(!\A[3]~input_o ), + .datab(!\A[4]~input_o ), + .datac(!\A[1]~input_o ), + .datad(!\A[2]~input_o ), + .datae(!\B[1]~input_o ), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~4 .extended_lut = "off"; +defparam \ShiftLeft1~4 .lut_mask = 64'h333300FF55550F0F; +defparam \ShiftLeft1~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y27_N36 +cyclonev_lcell_comb \ShiftLeft1~5 ( +// Equation(s): +// \ShiftLeft1~5_combout = ( \B[0]~input_o & ( (!\B[2]~input_o & \ShiftLeft1~4_combout ) ) ) # ( !\B[0]~input_o & ( (!\B[2]~input_o & (((\ShiftLeft1~4_combout )))) # (\B[2]~input_o & (!\B[1]~input_o & (\A[0]~input_o ))) ) ) + + .dataa(!\B[1]~input_o ), + .datab(!\A[0]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\ShiftLeft1~4_combout ), + .datae(gnd), + .dataf(!\B[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~5 .extended_lut = "off"; +defparam \ShiftLeft1~5 .lut_mask = 64'h02F202F200F000F0; +defparam \ShiftLeft1~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N21 +cyclonev_lcell_comb \ShiftRight2~3 ( +// Equation(s): +// \ShiftRight2~3_combout = ( \ShiftRight3~0_combout & ( !\B[2]~input_o ) ) + + .dataa(gnd), + .datab(gnd), + .datac(!\B[2]~input_o ), + .datad(gnd), + .datae(gnd), + .dataf(!\ShiftRight3~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~3 .extended_lut = "off"; +defparam \ShiftRight2~3 .lut_mask = 64'h00000000F0F0F0F0; +defparam \ShiftRight2~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N0 +cyclonev_lcell_comb \Mux3~2 ( +// Equation(s): +// \Mux3~2_combout = ( !\op[2]~input_o & ( ((!\op[0]~input_o & (\ShiftLeft0~5_combout )) # (\op[0]~input_o & (((\ShiftRight1~0_combout & \ShiftRight0~0_combout ))))) ) ) # ( \op[2]~input_o & ( (((!\op[0]~input_o & (\ShiftLeft1~5_combout )) # +// (\op[0]~input_o & ((\ShiftRight2~3_combout ))))) ) ) + + .dataa(!\ShiftLeft0~5_combout ), + .datab(!\ShiftRight1~0_combout ), + .datac(!\ShiftLeft1~5_combout ), + .datad(!\ShiftRight2~3_combout ), + .datae(!\op[2]~input_o ), + .dataf(!\op[0]~input_o ), + .datag(!\ShiftRight0~0_combout ), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~2 .extended_lut = "on"; +defparam \Mux3~2 .lut_mask = 64'h55550F0F030300FF; +defparam \Mux3~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N42 +cyclonev_lcell_comb \Mux3~0 ( +// Equation(s): +// \Mux3~0_combout = ( \ShiftRight1~0_combout & ( \ShiftRight3~0_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\A[7]~input_o ) ) ) ) # ( !\ShiftRight1~0_combout & ( \ShiftRight3~0_combout & ( +// (!\op[2]~input_o & (!\ShiftRight0~0_combout & (\A[7]~input_o ))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (\A[7]~input_o )))) ) ) ) # ( \ShiftRight1~0_combout & ( !\ShiftRight3~0_combout & ( (!\op[2]~input_o & (((\A[7]~input_o )) # +// (\ShiftRight0~0_combout ))) # (\op[2]~input_o & (((\A[7]~input_o & \B[2]~input_o )))) ) ) ) # ( !\ShiftRight1~0_combout & ( !\ShiftRight3~0_combout & ( (\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & +// ((\B[2]~input_o ))))) ) ) ) + + .dataa(!\ShiftRight0~0_combout ), + .datab(!\op[2]~input_o ), + .datac(!\A[7]~input_o ), + .datad(!\B[2]~input_o ), + .datae(!\ShiftRight1~0_combout ), + .dataf(!\ShiftRight3~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~0 .extended_lut = "off"; +defparam \Mux3~0 .lut_mask = 64'h080B4C4F3B0B7F4F; +defparam \Mux3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N30 +cyclonev_lcell_comb \Mux3~1 ( +// Equation(s): +// \Mux3~1_combout = ( \Mux3~0_combout & ( (!\op[1]~input_o & (((\Mux3~2_combout )))) # (\op[1]~input_o & (((\A[4]~input_o )) # (\op[0]~input_o ))) ) ) # ( !\Mux3~0_combout & ( (!\op[1]~input_o & (((\Mux3~2_combout )))) # (\op[1]~input_o & +// (!\op[0]~input_o & ((\A[4]~input_o )))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\Mux3~2_combout ), + .datad(!\A[4]~input_o ), + .datae(gnd), + .dataf(!\Mux3~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~1 .extended_lut = "off"; +defparam \Mux3~1 .lut_mask = 64'h0C2E0C2E1D3F1D3F; +defparam \Mux3~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N3 +cyclonev_lcell_comb \Mux1~4 ( +// Equation(s): +// \Mux1~4_combout = ( \ShiftLeft0~0_combout & ( (!\op[1]~input_o & (((\op[2]~input_o & \B[2]~input_o )) # (\op[0]~input_o ))) ) ) # ( !\ShiftLeft0~0_combout & ( (!\op[1]~input_o & ((!\op[2]~input_o ) # ((\op[0]~input_o ) # (\B[2]~input_o )))) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\ShiftLeft0~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~4 .extended_lut = "off"; +defparam \Mux1~4 .lut_mask = 64'h8CCC8CCC04CC04CC; +defparam \Mux1~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N27 +cyclonev_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = ( !\op[0]~input_o & ( ((!\op[2]~input_o & ((!\C[1]~input_o ))) # (\op[2]~input_o & (!\B[1]~input_o ))) # (\op[1]~input_o ) ) ) + + .dataa(!\B[1]~input_o ), + .datab(!\C[1]~input_o ), + .datac(!\op[1]~input_o ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\op[0]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~0 .extended_lut = "off"; +defparam \Mux1~0 .lut_mask = 64'hCFAFCFAF00000000; +defparam \Mux1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N24 +cyclonev_lcell_comb \Mux1~1 ( +// Equation(s): +// \Mux1~1_combout = ( \Mux5~7_combout & ( \Mux1~0_combout & ( \op[1]~input_o ) ) ) # ( !\Mux5~7_combout & ( \Mux1~0_combout & ( ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) # (\op[1]~input_o ) ) ) ) + + .dataa(!\ShiftRight0~0_combout ), + .datab(!\B[2]~input_o ), + .datac(!\op[2]~input_o ), + .datad(!\op[1]~input_o ), + .datae(!\Mux5~7_combout ), + .dataf(!\Mux1~0_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~1 .extended_lut = "off"; +defparam \Mux1~1 .lut_mask = 64'h000000005CFF00FF; +defparam \Mux1~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N48 +cyclonev_lcell_comb \Mux1~6 ( +// Equation(s): +// \Mux1~6_combout = ( !\op[1]~input_o & ( (!\op[0]~input_o & ((!\op[2]~input_o & ((\ShiftLeft0~0_combout ))) # (\op[2]~input_o & (!\B[2]~input_o )))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\B[2]~input_o ), + .datac(!\ShiftLeft0~0_combout ), + .datad(!\op[2]~input_o ), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~6_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~6 .extended_lut = "off"; +defparam \Mux1~6 .lut_mask = 64'h0A880A8800000000; +defparam \Mux1~6 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N0 +cyclonev_lcell_comb \Mux1~5 ( +// Equation(s): +// \Mux1~5_combout = ( \B[2]~input_o & ( (!\op[1]~input_o & (((!\ShiftRight0~0_combout ) # (\op[0]~input_o )) # (\op[2]~input_o ))) ) ) # ( !\B[2]~input_o & ( (!\op[1]~input_o & (((!\op[2]~input_o & !\ShiftRight0~0_combout )) # (\op[0]~input_o ))) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\op[0]~input_o ), + .datae(gnd), + .dataf(!\B[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~5_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~5 .extended_lut = "off"; +defparam \Mux1~5 .lut_mask = 64'h80CC80CCC4CCC4CC; +defparam \Mux1~5 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N42 +cyclonev_lcell_comb \Mux2~2 ( +// Equation(s): +// \Mux2~2_combout = ( \Mux6~3_combout & ( \ShiftRight1~3_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux6~3_combout & ( \ShiftRight1~3_combout & ( +// (!\op[2]~input_o & (!\ShiftRight0~0_combout & (!\A[7]~input_o ))) # (\op[2]~input_o & (((!\A[7]~input_o ) # (!\B[2]~input_o )))) ) ) ) # ( \Mux6~3_combout & ( !\ShiftRight1~3_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & +// (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux6~3_combout & ( !\ShiftRight1~3_combout & ( (!\A[7]~input_o ) # ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) ) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\ShiftRight0~0_combout ), + .datac(!\A[7]~input_o ), + .datad(!\B[2]~input_o ), + .datae(!\Mux6~3_combout ), + .dataf(!\ShiftRight1~3_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~2 .extended_lut = "off"; +defparam \Mux2~2 .lut_mask = 64'hF7F280D0D5D080D0; +defparam \Mux2~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N6 +cyclonev_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = ( \A[3]~input_o & ( (!\Mux5~7_combout ) # ((!\Mux5~6_combout & (\A[4]~input_o )) # (\Mux5~6_combout & ((\A[2]~input_o )))) ) ) # ( !\A[3]~input_o & ( (\Mux5~7_combout & ((!\Mux5~6_combout & (\A[4]~input_o )) # (\Mux5~6_combout & +// ((\A[2]~input_o ))))) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\Mux5~6_combout ), + .datac(!\A[2]~input_o ), + .datad(!\Mux5~7_combout ), + .datae(gnd), + .dataf(!\A[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~1 .extended_lut = "off"; +defparam \Mux2~1 .lut_mask = 64'h00470047FF47FF47; +defparam \Mux2~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N18 +cyclonev_lcell_comb \Mux2~3 ( +// Equation(s): +// \Mux2~3_combout = ( \Mux2~1_combout & ( (!\Mux1~5_combout & (((!\Mux2~2_combout )) # (\Mux1~6_combout ))) # (\Mux1~5_combout & (((\ShiftLeft0~1_combout )))) ) ) # ( !\Mux2~1_combout & ( (!\Mux1~5_combout & (!\Mux1~6_combout & (!\Mux2~2_combout ))) +// # (\Mux1~5_combout & (((\ShiftLeft0~1_combout )))) ) ) + + .dataa(!\Mux1~6_combout ), + .datab(!\Mux1~5_combout ), + .datac(!\Mux2~2_combout ), + .datad(!\ShiftLeft0~1_combout ), + .datae(gnd), + .dataf(!\Mux2~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~3 .extended_lut = "off"; +defparam \Mux2~3 .lut_mask = 64'h80B380B3C4F7C4F7; +defparam \Mux2~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N57 +cyclonev_lcell_comb \Mux1~3 ( +// Equation(s): +// \Mux1~3_combout = (!\op[2]~input_o & (\ShiftLeft0~0_combout & ((!\op[0]~input_o ) # (!\C[2]~input_o )))) # (\op[2]~input_o & (!\op[0]~input_o )) + + .dataa(!\op[0]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\C[2]~input_o ), + .datad(!\ShiftLeft0~0_combout ), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~3_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~3 .extended_lut = "off"; +defparam \Mux1~3 .lut_mask = 64'h22EA22EA22EA22EA; +defparam \Mux1~3 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N54 +cyclonev_lcell_comb \Mux1~2 ( +// Equation(s): +// \Mux1~2_combout = ( \C[2]~input_o & ( (!\op[0]~input_o & (!\op[2]~input_o & ((\ShiftLeft0~0_combout )))) # (\op[0]~input_o & (\op[2]~input_o & (!\B[2]~input_o ))) ) ) # ( !\C[2]~input_o & ( (!\op[2]~input_o & (((\ShiftLeft0~0_combout )))) # +// (\op[2]~input_o & (\op[0]~input_o & (!\B[2]~input_o ))) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\op[2]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\ShiftLeft0~0_combout ), + .datae(gnd), + .dataf(!\C[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~2_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~2 .extended_lut = "off"; +defparam \Mux1~2 .lut_mask = 64'h10DC10DC10981098; +defparam \Mux1~2 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N21 +cyclonev_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = ( \ShiftRight0~1_combout & ( (!\Mux1~3_combout & (((\ShiftRight2~0_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (((\Mux1~2_combout )) # (\ShiftLeft1~0_combout ))) ) ) # ( !\ShiftRight0~1_combout & ( (!\Mux1~3_combout & +// (((\ShiftRight2~0_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (\ShiftLeft1~0_combout & ((!\Mux1~2_combout )))) ) ) + + .dataa(!\ShiftLeft1~0_combout ), + .datab(!\ShiftRight2~0_combout ), + .datac(!\Mux1~3_combout ), + .datad(!\Mux1~2_combout ), + .datae(gnd), + .dataf(!\ShiftRight0~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~0 .extended_lut = "off"; +defparam \Mux2~0 .lut_mask = 64'h05300530053F053F; +defparam \Mux2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N54 +cyclonev_lcell_comb \Mux2~4 ( +// Equation(s): +// \Mux2~4_combout = ( \A[5]~input_o & ( ((!\Mux1~4_combout & (\Mux2~3_combout )) # (\Mux1~4_combout & ((\Mux2~0_combout )))) # (\Mux1~1_combout ) ) ) # ( !\A[5]~input_o & ( (!\Mux1~1_combout & ((!\Mux1~4_combout & (\Mux2~3_combout )) # +// (\Mux1~4_combout & ((\Mux2~0_combout ))))) ) ) + + .dataa(!\Mux1~4_combout ), + .datab(!\Mux1~1_combout ), + .datac(!\Mux2~3_combout ), + .datad(!\Mux2~0_combout ), + .datae(gnd), + .dataf(!\A[5]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~4 .extended_lut = "off"; +defparam \Mux2~4 .lut_mask = 64'h084C084C3B7F3B7F; +defparam \Mux2~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N45 +cyclonev_lcell_comb \Mux1~9 ( +// Equation(s): +// \Mux1~9_combout = ( \Mux5~10_combout & ( \ShiftRight1~4_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux5~10_combout & ( \ShiftRight1~4_combout & ( +// (!\op[2]~input_o & (!\ShiftRight0~0_combout & ((!\A[7]~input_o )))) # (\op[2]~input_o & (((!\B[2]~input_o ) # (!\A[7]~input_o )))) ) ) ) # ( \Mux5~10_combout & ( !\ShiftRight1~4_combout & ( (!\A[7]~input_o & ((!\op[2]~input_o & +// (!\ShiftRight0~0_combout )) # (\op[2]~input_o & ((\B[2]~input_o ))))) ) ) ) # ( !\Mux5~10_combout & ( !\ShiftRight1~4_combout & ( (!\A[7]~input_o ) # ((!\op[2]~input_o & (\ShiftRight0~0_combout )) # (\op[2]~input_o & ((!\B[2]~input_o )))) ) ) ) + + .dataa(!\op[2]~input_o ), + .datab(!\ShiftRight0~0_combout ), + .datac(!\B[2]~input_o ), + .datad(!\A[7]~input_o ), + .datae(!\Mux5~10_combout ), + .dataf(!\ShiftRight1~4_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~9_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~9 .extended_lut = "off"; +defparam \Mux1~9 .lut_mask = 64'hFF728D00DD508D00; +defparam \Mux1~9 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N9 +cyclonev_lcell_comb \Mux1~8 ( +// Equation(s): +// \Mux1~8_combout = ( \A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((!\Mux5~6_combout ) # (\A[3]~input_o )))) ) ) # ( !\A[5]~input_o & ( (!\Mux5~7_combout & (\A[4]~input_o )) # (\Mux5~7_combout & (((\Mux5~6_combout & +// \A[3]~input_o )))) ) ) + + .dataa(!\A[4]~input_o ), + .datab(!\Mux5~6_combout ), + .datac(!\A[3]~input_o ), + .datad(!\Mux5~7_combout ), + .datae(gnd), + .dataf(!\A[5]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~8_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~8 .extended_lut = "off"; +defparam \Mux1~8 .lut_mask = 64'h5503550355CF55CF; +defparam \Mux1~8 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N21 +cyclonev_lcell_comb \Mux1~10 ( +// Equation(s): +// \Mux1~10_combout = ( \Mux1~8_combout & ( (!\Mux1~5_combout & (((!\Mux1~9_combout )) # (\Mux1~6_combout ))) # (\Mux1~5_combout & (((\ShiftLeft0~2_combout )))) ) ) # ( !\Mux1~8_combout & ( (!\Mux1~5_combout & (!\Mux1~6_combout & (!\Mux1~9_combout ))) +// # (\Mux1~5_combout & (((\ShiftLeft0~2_combout )))) ) ) + + .dataa(!\Mux1~6_combout ), + .datab(!\Mux1~5_combout ), + .datac(!\Mux1~9_combout ), + .datad(!\ShiftLeft0~2_combout ), + .datae(gnd), + .dataf(!\Mux1~8_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~10_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~10 .extended_lut = "off"; +defparam \Mux1~10 .lut_mask = 64'h80B380B3C4F7C4F7; +defparam \Mux1~10 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X63_Y27_N51 +cyclonev_lcell_comb \Mux1~7 ( +// Equation(s): +// \Mux1~7_combout = ( \ShiftLeft1~1_combout & ( (!\Mux1~3_combout & (((\ShiftRight2~1_combout & \Mux1~2_combout )))) # (\Mux1~3_combout & (((!\Mux1~2_combout )) # (\ShiftRight0~2_combout ))) ) ) # ( !\ShiftLeft1~1_combout & ( (\Mux1~2_combout & +// ((!\Mux1~3_combout & ((\ShiftRight2~1_combout ))) # (\Mux1~3_combout & (\ShiftRight0~2_combout )))) ) ) + + .dataa(!\ShiftRight0~2_combout ), + .datab(!\ShiftRight2~1_combout ), + .datac(!\Mux1~3_combout ), + .datad(!\Mux1~2_combout ), + .datae(gnd), + .dataf(!\ShiftLeft1~1_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~7_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~7 .extended_lut = "off"; +defparam \Mux1~7 .lut_mask = 64'h003500350F350F35; +defparam \Mux1~7 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y27_N57 +cyclonev_lcell_comb \Mux1~11 ( +// Equation(s): +// \Mux1~11_combout = ( \Mux1~7_combout & ( (!\Mux1~1_combout & (((\Mux1~10_combout )) # (\Mux1~4_combout ))) # (\Mux1~1_combout & (((\A[6]~input_o )))) ) ) # ( !\Mux1~7_combout & ( (!\Mux1~1_combout & (!\Mux1~4_combout & ((\Mux1~10_combout )))) # +// (\Mux1~1_combout & (((\A[6]~input_o )))) ) ) + + .dataa(!\Mux1~4_combout ), + .datab(!\Mux1~1_combout ), + .datac(!\A[6]~input_o ), + .datad(!\Mux1~10_combout ), + .datae(gnd), + .dataf(!\Mux1~7_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~11_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~11 .extended_lut = "off"; +defparam \Mux1~11 .lut_mask = 64'h038B038B47CF47CF; +defparam \Mux1~11 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N6 +cyclonev_lcell_comb \ShiftRight2~4 ( +// Equation(s): +// \ShiftRight2~4_combout = ( !\B[1]~input_o & ( (!\B[0]~input_o & (!\B[2]~input_o & \A[7]~input_o )) ) ) + + .dataa(gnd), + .datab(!\B[0]~input_o ), + .datac(!\B[2]~input_o ), + .datad(!\A[7]~input_o ), + .datae(gnd), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight2~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight2~4 .extended_lut = "off"; +defparam \ShiftRight2~4 .lut_mask = 64'h00C000C000000000; +defparam \ShiftRight2~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N57 +cyclonev_lcell_comb \ShiftLeft1~6 ( +// Equation(s): +// \ShiftLeft1~6_combout = ( \B[0]~input_o & ( \B[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\B[0]~input_o & ( \B[1]~input_o & ( \A[5]~input_o ) ) ) # ( \B[0]~input_o & ( !\B[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\B[0]~input_o & ( !\B[1]~input_o & +// ( \A[7]~input_o ) ) ) + + .dataa(!\A[5]~input_o ), + .datab(!\A[6]~input_o ), + .datac(!\A[4]~input_o ), + .datad(!\A[7]~input_o ), + .datae(!\B[0]~input_o ), + .dataf(!\B[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~6_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~6 .extended_lut = "off"; +defparam \ShiftLeft1~6 .lut_mask = 64'h00FF333355550F0F; +defparam \ShiftLeft1~6 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N18 +cyclonev_lcell_comb \ShiftLeft1~7 ( +// Equation(s): +// \ShiftLeft1~7_combout = ( \B[2]~input_o & ( \ShiftLeft1~2_combout ) ) # ( !\B[2]~input_o & ( \ShiftLeft1~6_combout ) ) + + .dataa(gnd), + .datab(!\ShiftLeft1~6_combout ), + .datac(!\ShiftLeft1~2_combout ), + .datad(gnd), + .datae(gnd), + .dataf(!\B[2]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft1~7_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft1~7 .extended_lut = "off"; +defparam \ShiftLeft1~7 .lut_mask = 64'h333333330F0F0F0F; +defparam \ShiftLeft1~7 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N15 +cyclonev_lcell_comb \ShiftRight0~4 ( +// Equation(s): +// \ShiftRight0~4_combout = (\A[7]~input_o & (\ShiftRight0~0_combout & \ShiftRight1~2_combout )) + + .dataa(gnd), + .datab(!\A[7]~input_o ), + .datac(!\ShiftRight0~0_combout ), + .datad(!\ShiftRight1~2_combout ), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftRight0~4_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftRight0~4 .extended_lut = "off"; +defparam \ShiftRight0~4 .lut_mask = 64'h0003000300030003; +defparam \ShiftRight0~4 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X64_Y28_N54 +cyclonev_lcell_comb \ShiftLeft0~6 ( +// Equation(s): +// \ShiftLeft0~6_combout = ( \C[0]~input_o & ( \C[1]~input_o & ( \A[4]~input_o ) ) ) # ( !\C[0]~input_o & ( \C[1]~input_o & ( \A[5]~input_o ) ) ) # ( \C[0]~input_o & ( !\C[1]~input_o & ( \A[6]~input_o ) ) ) # ( !\C[0]~input_o & ( !\C[1]~input_o & +// ( \A[7]~input_o ) ) ) + + .dataa(!\A[5]~input_o ), + .datab(!\A[6]~input_o ), + .datac(!\A[7]~input_o ), + .datad(!\A[4]~input_o ), + .datae(!\C[0]~input_o ), + .dataf(!\C[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~6_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~6 .extended_lut = "off"; +defparam \ShiftLeft0~6 .lut_mask = 64'h0F0F3333555500FF; +defparam \ShiftLeft0~6 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N9 +cyclonev_lcell_comb \ShiftLeft0~7 ( +// Equation(s): +// \ShiftLeft0~7_combout = ( \ShiftLeft0~6_combout & ( (\ShiftLeft0~0_combout & ((!\C[2]~input_o ) # (\ShiftLeft0~3_combout ))) ) ) # ( !\ShiftLeft0~6_combout & ( (\ShiftLeft0~0_combout & (\ShiftLeft0~3_combout & \C[2]~input_o )) ) ) + + .dataa(!\ShiftLeft0~0_combout ), + .datab(gnd), + .datac(!\ShiftLeft0~3_combout ), + .datad(!\C[2]~input_o ), + .datae(gnd), + .dataf(!\ShiftLeft0~6_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\ShiftLeft0~7_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \ShiftLeft0~7 .extended_lut = "off"; +defparam \ShiftLeft0~7 .lut_mask = 64'h0005000555055505; +defparam \ShiftLeft0~7 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N24 +cyclonev_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = ( \op[2]~input_o & ( \ShiftLeft0~7_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~7_combout ))) # (\op[0]~input_o & (\ShiftRight2~4_combout )) ) ) ) # ( !\op[2]~input_o & ( \ShiftLeft0~7_combout & ( (!\op[0]~input_o ) # +// (\ShiftRight0~4_combout ) ) ) ) # ( \op[2]~input_o & ( !\ShiftLeft0~7_combout & ( (!\op[0]~input_o & ((\ShiftLeft1~7_combout ))) # (\op[0]~input_o & (\ShiftRight2~4_combout )) ) ) ) # ( !\op[2]~input_o & ( !\ShiftLeft0~7_combout & ( (\op[0]~input_o +// & \ShiftRight0~4_combout ) ) ) ) + + .dataa(!\op[0]~input_o ), + .datab(!\ShiftRight2~4_combout ), + .datac(!\ShiftLeft1~7_combout ), + .datad(!\ShiftRight0~4_combout ), + .datae(!\op[2]~input_o ), + .dataf(!\ShiftLeft0~7_combout ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~0 .extended_lut = "off"; +defparam \Mux0~0 .lut_mask = 64'h00551B1BAAFF1B1B; +defparam \Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X65_Y28_N12 +cyclonev_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = ( \op[1]~input_o & ( \A[7]~input_o ) ) # ( !\op[1]~input_o & ( \Mux0~0_combout ) ) + + .dataa(gnd), + .datab(!\A[7]~input_o ), + .datac(!\Mux0~0_combout ), + .datad(gnd), + .datae(gnd), + .dataf(!\op[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~1_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~1 .extended_lut = "off"; +defparam \Mux0~1 .lut_mask = 64'h0F0F0F0F33333333; +defparam \Mux0~1 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X58_Y37_N0 +cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off"; +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000; +defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off"; +// synopsys translate_on + +endmodule diff --git a/Quartus/A1_Q6/c5_pin_model_dump.txt b/Quartus/A1_Q6/c5_pin_model_dump.txt new file mode 100644 index 0000000..3a3970c --- /dev/null +++ b/Quartus/A1_Q6/c5_pin_model_dump.txt @@ -0,0 +1,88 @@ +io_4iomodule_c5_index: 61gpio_index: 2 +io_4iomodule_c5_index: 62gpio_index: 348 +io_4iomodule_c5_index: 40gpio_index: 6 +io_4iomodule_c5_index: 59gpio_index: 344 +io_4iomodule_c5_index: 31gpio_index: 10 +io_4iomodule_c5_index: 35gpio_index: 340 +io_4iomodule_c5_index: 42gpio_index: 14 +io_4iomodule_c5_index: 19gpio_index: 336 +io_4iomodule_c5_index: 29gpio_index: 19 +io_4iomodule_c5_index: 9gpio_index: 332 +io_4iomodule_c5_index: 34gpio_index: 22 +io_4iomodule_c5_index: 25gpio_index: 328 +io_4iomodule_c5_index: 17gpio_index: 27 +io_4iomodule_c5_index: 44gpio_index: 324 +io_4iomodule_c5_index: 57gpio_index: 30 +io_4iomodule_c5_index: 13gpio_index: 320 +io_4iomodule_c5_index: 5gpio_index: 35 +io_4iomodule_c5_index: 39gpio_index: 316 +io_4iomodule_c5_index: 14gpio_index: 38 +io_4iomodule_c5_index: 27gpio_index: 312 +io_4iomodule_c5_index: 21gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 308 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 26gpio_index: 304 +io_4iomodule_c5_index: 1gpio_index: 51 +io_4iomodule_c5_index: 38gpio_index: 300 +io_4iomodule_c5_index: 50gpio_index: 54 +io_4iomodule_c5_index: 36gpio_index: 296 +io_4iomodule_c5_index: 11gpio_index: 59 +io_4iomodule_c5_index: 2gpio_index: 292 +io_4iomodule_c5_index: 4gpio_index: 62 +io_4iomodule_c5_index: 6gpio_index: 288 +io_4iomodule_c5_index: 48gpio_index: 67 +io_4iomodule_c5_index: 24gpio_index: 284 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 12gpio_index: 280 +io_4iomodule_c5_index: 49gpio_index: 75 +io_4iomodule_c5_index: 63gpio_index: 276 +io_4iomodule_c5_index: 41gpio_index: 78 +io_4iomodule_c5_index: 37gpio_index: 272 +io_4iomodule_c5_index: 3gpio_index: 83 +io_4iomodule_c5_index: 33gpio_index: 268 +io_4iomodule_c5_index: 22gpio_index: 86 +io_4iomodule_c5_index: 54gpio_index: 264 +io_4iomodule_c5_index: 56gpio_index: 91 +io_4iomodule_c5_index: 32gpio_index: 260 +io_4iomodule_c5_index: 53gpio_index: 94 +io_4iomodule_c5_index: 52gpio_index: 256 +io_4iomodule_c5_index: 28gpio_index: 99 +io_4iomodule_c5_index: 45gpio_index: 252 +io_4iomodule_c5_index: 10gpio_index: 102 +io_4iomodule_c5_index: 43gpio_index: 248 +io_4iomodule_c5_index: 15gpio_index: 107 +io_4iomodule_c5_index: 7gpio_index: 244 +io_4iomodule_c5_index: 55gpio_index: 110 +io_4iomodule_c5_index: 60gpio_index: 240 +io_4iomodule_c5_index: 18gpio_index: 115 +io_4iomodule_c5_index: 58gpio_index: 236 +io_4iomodule_c5_index: 46gpio_index: 118 +io_4iomodule_c5_index: 30gpio_index: 232 +io_4iomodule_c5_index: 16gpio_index: 123 +io_4iomodule_c5_index: 47gpio_index: 228 +io_4iomodule_c5_index: 51gpio_index: 126 +io_4iomodule_c5_index: 23gpio_index: 224 +io_4iomodule_h_c5_index: 0gpio_index: 129 +io_4iomodule_h_c5_index: 18gpio_index: 133 +io_4iomodule_h_c5_index: 15gpio_index: 137 +io_4iomodule_h_c5_index: 16gpio_index: 141 +io_4iomodule_h_c5_index: 20gpio_index: 144 +io_4iomodule_h_c5_index: 23gpio_index: 148 +io_4iomodule_h_c5_index: 12gpio_index: 152 +io_4iomodule_h_c5_index: 9gpio_index: 156 +io_4iomodule_h_c5_index: 1gpio_index: 160 +io_4iomodule_h_c5_index: 5gpio_index: 164 +io_4iomodule_h_c5_index: 21gpio_index: 168 +io_4iomodule_h_c5_index: 6gpio_index: 172 +io_4iomodule_h_c5_index: 17gpio_index: 176 +io_4iomodule_h_c5_index: 2gpio_index: 180 +io_4iomodule_h_c5_index: 4gpio_index: 184 +io_4iomodule_h_c5_index: 3gpio_index: 188 +io_4iomodule_h_c5_index: 14gpio_index: 192 +io_4iomodule_h_c5_index: 7gpio_index: 196 +io_4iomodule_h_c5_index: 19gpio_index: 200 +io_4iomodule_h_c5_index: 11gpio_index: 204 +io_4iomodule_h_c5_index: 8gpio_index: 208 +io_4iomodule_h_c5_index: 13gpio_index: 212 +io_4iomodule_h_c5_index: 22gpio_index: 216 +io_4iomodule_h_c5_index: 10gpio_index: 220 diff --git a/Quartus/A1_Q6/db/.cmp.kpt b/Quartus/A1_Q6/db/.cmp.kpt new file mode 100644 index 0000000..88753a4 Binary files /dev/null and b/Quartus/A1_Q6/db/.cmp.kpt differ diff --git a/Quartus/A1_Q6/db/A1_Q6.map_bb.logdb b/Quartus/A1_Q6/db/A1_Q6.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A1_Q6/db/A1_Q6.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.cdb b/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.cdb new file mode 100644 index 0000000..83b6831 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.hdb b/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.hdb new file mode 100644 index 0000000..6d63833 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.(0).cnf.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg b/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg new file mode 100644 index 0000000..9997d09 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431609040 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:08 2026 " "Processing started: Tue Sep 15 10:20:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431609041 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789431609041 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789431609707 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789431614462 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "517 " "Peak virtual memory: 517 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:14 2026 " "Processing ended: Tue Sep 15 10:20:14 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431614674 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789431614674 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.asm.rdb b/Quartus/A1_Q6/db/instruction_classifier.asm.rdb new file mode 100644 index 0000000..8d91463 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.asm.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cbx.xml b/Quartus/A1_Q6/db/instruction_classifier.cbx.xml new file mode 100644 index 0000000..24a80b8 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm b/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm new file mode 100644 index 0000000..b01b807 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp.bpm differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb new file mode 100644 index 0000000..1022264 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb new file mode 100644 index 0000000..12ac6ff Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.idb b/Quartus/A1_Q6/db/instruction_classifier.cmp.idb new file mode 100644 index 0000000..8a5f867 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp.idb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb new file mode 100644 index 0000000..91492ef --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.cmp.logdb @@ -0,0 +1,53 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;13;0;0;0;0;0;0;0;7;0;0;0;0;7;0;0;0;0;7;0;13;13;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,13;13;13;13;13;0;13;13;13;13;13;13;13;6;13;13;13;13;6;13;13;13;13;6;13;0;0;13, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,R[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,J[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,B2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,I[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,F[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,M[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,op[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,28, +IO_RULES_SUMMARY,Number of I/O Rules Passed,6, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22, diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb b/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb new file mode 100644 index 0000000..4105755 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cmp_merge.kpt b/Quartus/A1_Q6/db/instruction_classifier.cmp_merge.kpt new file mode 100644 index 0000000..58ca13e Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cmp_merge.kpt differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..b19b6d1 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_0c_fast.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_85c_fast.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_85c_fast.hsd new file mode 100644 index 0000000..b6ce56d Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ff_85c_fast.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_0c_slow.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_0c_slow.hsd new file mode 100644 index 0000000..9729dee Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_0c_slow.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..118df22 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.db_info b/Quartus/A1_Q6/db/instruction_classifier.db_info index fb20779..50b2afb 100644 --- a/Quartus/A1_Q6/db/instruction_classifier.db_info +++ b/Quartus/A1_Q6/db/instruction_classifier.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Fri Sep 4 13:11:24 2026 +Creation_Time = Tue Sep 15 10:09:43 2026 diff --git a/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg b/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg new file mode 100644 index 0000000..9ed811b --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431623036 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:22 2026 " "Processing started: Tue Sep 15 10:20:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431623037 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623037 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789431623815 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "instruction_classifier.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/ simulation " "Generated file instruction_classifier.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789431623880 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:23 2026 " "Processing ended: Tue Sep 15 10:20:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431623914 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789431623914 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg b/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg new file mode 100644 index 0000000..ec2f020 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.fit.qmsg @@ -0,0 +1,44 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789431575376 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789431575377 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "instruction_classifier 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"instruction_classifier\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789431575381 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789431575456 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789431575888 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789431575916 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789431575969 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "13 13 " "No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789431576256 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789431583219 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583296 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789431583298 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789431583299 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789431583300 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789431583300 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431583313 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789431589563 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789431589563 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789431589564 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789431589564 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789431589565 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789431589565 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789431589566 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789431589568 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789431589608 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431593856 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789431595048 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789431595350 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431595351 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789431596250 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789431601801 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789431601801 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789431602005 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789431602005 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431602007 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789431602821 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431602862 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603215 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789431603215 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789431603872 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789431606547 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1369 " "Peak virtual memory: 1369 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:07 2026 " "Processing ended: Tue Sep 15 10:20:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:33 " "Elapsed time: 00:00:33" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431607368 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789431607368 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.hier_info b/Quartus/A1_Q6/db/instruction_classifier.hier_info new file mode 100644 index 0000000..bb9d567 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.hier_info @@ -0,0 +1,37 @@ +|instruction_classifier +op[0] => Equal0.IN5 +op[0] => Equal1.IN0 +op[1] => Equal0.IN4 +op[1] => Equal1.IN5 +op[1] => Equal2.IN0 +op[2] => Equal0.IN3 +op[2] => Equal1.IN4 +op[2] => Equal2.IN4 +op[2] => Equal3.IN0 +op[3] => Equal0.IN2 +op[3] => Equal1.IN3 +op[3] => Equal2.IN3 +op[3] => Equal3.IN3 +op[3] => Equal4.IN0 +op[4] => Equal0.IN1 +op[4] => Equal1.IN2 +op[4] => Equal2.IN2 +op[4] => Equal3.IN2 +op[4] => Equal4.IN2 +op[4] => Equal5.IN0 +op[5] => M[0].DATAIN +op[5] => Equal0.IN0 +op[5] => Equal1.IN1 +op[5] => Equal2.IN1 +op[5] => Equal3.IN1 +op[5] => Equal4.IN1 +op[5] => Equal5.IN1 +R[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE +B1[0] <= Equal1.DB_MAX_OUTPUT_PORT_TYPE +J[0] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE +B2[0] <= Equal3.DB_MAX_OUTPUT_PORT_TYPE +I[0] <= Equal4.DB_MAX_OUTPUT_PORT_TYPE +F[0] <= Equal5.DB_MAX_OUTPUT_PORT_TYPE +M[0] <= op[5].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/Quartus/A1_Q6/db/instruction_classifier.hif b/Quartus/A1_Q6/db/instruction_classifier.hif new file mode 100644 index 0000000..9c0cb28 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.hif differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.lpc.html b/Quartus/A1_Q6/db/instruction_classifier.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/Quartus/A1_Q6/db/instruction_classifier.lpc.rdb b/Quartus/A1_Q6/db/instruction_classifier.lpc.rdb new file mode 100644 index 0000000..7be5d4c Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.lpc.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.lpc.txt b/Quartus/A1_Q6/db/instruction_classifier.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.ammdb b/Quartus/A1_Q6/db/instruction_classifier.map.ammdb new file mode 100644 index 0000000..25b1b34 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.ammdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.bpm b/Quartus/A1_Q6/db/instruction_classifier.map.bpm new file mode 100644 index 0000000..1c4ef86 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.bpm differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.cdb b/Quartus/A1_Q6/db/instruction_classifier.map.cdb new file mode 100644 index 0000000..4f16ef8 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.hdb b/Quartus/A1_Q6/db/instruction_classifier.map.hdb new file mode 100644 index 0000000..3fcbfd1 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.kpt b/Quartus/A1_Q6/db/instruction_classifier.map.kpt new file mode 100644 index 0000000..94b1af3 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.kpt differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.qmsg b/Quartus/A1_Q6/db/instruction_classifier.map.qmsg new file mode 100644 index 0000000..96ef6d7 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.map.qmsg @@ -0,0 +1,11 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431562372 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:19:22 2026 " "Processing started: Tue Sep 15 10:19:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431562373 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431562373 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789431562701 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" { { "Info" "ISGN_ENTITY_NAME" "1 instruction_classifier " "Found entity 1: instruction_classifier" { } { { "../../modules/instruction_classifier.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789431572260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431572260 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "instruction_classifier " "Elaborating entity \"instruction_classifier\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789431572408 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789431573138 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789431573508 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789431573508 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789431573553 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6 " "Implemented 6 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789431573553 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789431573553 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "430 " "Peak virtual memory: 430 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:19:33 2026 " "Processing ended: Tue Sep 15 10:19:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431573561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789431573561 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.map.rdb b/Quartus/A1_Q6/db/instruction_classifier.map.rdb new file mode 100644 index 0000000..ab91854 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb b/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb new file mode 100644 index 0000000..df60a63 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map_bb.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb b/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb new file mode 100644 index 0000000..1342f1b Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.map_bb.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb b/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb new file mode 100644 index 0000000..0f9207c Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.pre_map.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.root_partition.map.reg_db.cdb b/Quartus/A1_Q6/db/instruction_classifier.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..1db4c4f Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.root_partition.map.reg_db.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.routing.rdb b/Quartus/A1_Q6/db/instruction_classifier.routing.rdb new file mode 100644 index 0000000..9d5ad3d Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.routing.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb b/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb new file mode 100644 index 0000000..43e637e Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.rtlv.hdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb new file mode 100644 index 0000000..269ceb8 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg_swap.cdb b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg_swap.cdb new file mode 100644 index 0000000..5e9299c Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.rtlv_sg_swap.cdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry_dsc.sci b/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry_dsc.sci differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.smart_action.txt b/Quartus/A1_Q6/db/instruction_classifier.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg b/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg new file mode 100644 index 0000000..95a61a7 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.sta.qmsg @@ -0,0 +1,61 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789431616218 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:20:15 2026 " "Processing started: Tue Sep 15 10:20:15 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789431616218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616218 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q6 -c instruction_classifier " "Command: quartus_sta A1_Q6 -c instruction_classifier" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431616219 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789431616277 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789431616764 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789431616764 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431616842 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "instruction_classifier.sdc " "Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789431617439 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431617439 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431617440 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789431617441 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789431617448 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431617448 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617450 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617453 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617454 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617455 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617456 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431617457 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431617459 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431617506 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431618682 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431618767 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618768 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618769 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618770 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618771 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618772 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431618773 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789431618774 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789431619046 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789431619708 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619758 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619759 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619760 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619761 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619762 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619763 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789431619765 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789431619925 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789431619926 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789431619927 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619929 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619931 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619932 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619934 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789431619935 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621439 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789431621440 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "785 " "Peak virtual memory: 785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:20:21 2026 " "Processing ended: Tue Sep 15 10:20:21 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789431621463 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789431621463 ""} diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta.rdb b/Quartus/A1_Q6/db/instruction_classifier.sta.rdb new file mode 100644 index 0000000..9592128 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.sta.rdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb new file mode 100644 index 0000000..19e7a2f Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tis_db_list.ddb b/Quartus/A1_Q6/db/instruction_classifier.tis_db_list.ddb new file mode 100644 index 0000000..06ddd4e Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tis_db_list.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb new file mode 100644 index 0000000..f957e24 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb new file mode 100644 index 0000000..f1e526b Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb new file mode 100644 index 0000000..d410261 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb new file mode 100644 index 0000000..7f340aa Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb new file mode 100644 index 0000000..74619ac Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb new file mode 100644 index 0000000..a6d3fc6 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier.tmw_info b/Quartus/A1_Q6/db/instruction_classifier.tmw_info new file mode 100644 index 0000000..9930155 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:03 +start_analysis_synthesis:s:00:00:13-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:34-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation +start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb b/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb new file mode 100644 index 0000000..96bf786 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.vpr.ammdb differ diff --git a/Quartus/A1_Q6/db/instruction_classifier_partition_pins.json b/Quartus/A1_Q6/db/instruction_classifier_partition_pins.json new file mode 100644 index 0000000..db93c97 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier_partition_pins.json @@ -0,0 +1,61 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "R[0]", + "strict" : false + }, + { + "name" : "B1[0]", + "strict" : false + }, + { + "name" : "J[0]", + "strict" : false + }, + { + "name" : "B2[0]", + "strict" : false + }, + { + "name" : "I[0]", + "strict" : false + }, + { + "name" : "F[0]", + "strict" : false + }, + { + "name" : "M[0]", + "strict" : false + }, + { + "name" : "op[0]", + "strict" : false + }, + { + "name" : "op[1]", + "strict" : false + }, + { + "name" : "op[2]", + "strict" : false + }, + { + "name" : "op[3]", + "strict" : false + }, + { + "name" : "op[4]", + "strict" : false + }, + { + "name" : "op[5]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/Quartus/A1_Q6/incremental_db/README b/Quartus/A1_Q6/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/Quartus/A1_Q6/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.db_info b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.db_info new file mode 100644 index 0000000..7bf4bc1 --- /dev/null +++ b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Tue Sep 15 10:19:32 2026 diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb new file mode 100644 index 0000000..39dcaf2 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.ammdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb new file mode 100644 index 0000000..48d808f Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.dfp b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.dfp differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb new file mode 100644 index 0000000..34ff019 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb new file mode 100644 index 0000000..d2a946b Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.sig b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb new file mode 100644 index 0000000..30525f0 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.logdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb new file mode 100644 index 0000000..c2df523 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb new file mode 100644 index 0000000..7cf41b5 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.dpi b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.dpi new file mode 100644 index 0000000..a204717 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.dpi differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..aa9528a Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hb_info b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hb_info differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..9254a92 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.sig b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb new file mode 100644 index 0000000..9a352eb Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.kpt b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.kpt new file mode 100644 index 0000000..19bdacb Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.root_partition.map.kpt differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb new file mode 100644 index 0000000..ca88107 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrp.hdb differ diff --git a/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrs.cdb b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrs.cdb new file mode 100644 index 0000000..968a0b8 Binary files /dev/null and b/Quartus/A1_Q6/incremental_db/compiled_partitions/instruction_classifier.rrs.cdb differ diff --git a/Quartus/A1_Q6/instruction_classifier.qsf b/Quartus/A1_Q6/instruction_classifier.qsf index 54d3982..109b697 100644 --- a/Quartus/A1_Q6/instruction_classifier.qsf +++ b/Quartus/A1_Q6/instruction_classifier.qsf @@ -54,4 +54,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt new file mode 100644 index 0000000..3ac2359 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for instruction_classifier +Tue Sep 15 10:20:14 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: instruction_classifier.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Sep 15 10:20:14 2026 ; +; Revision Name ; instruction_classifier ; +; Top-level Entity Name ; instruction_classifier ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++------------------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------------------------------------------------------+ +; File Name ; ++------------------------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/output_files/instruction_classifier.sof ; ++------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; Assembler Device Options: instruction_classifier.sof ; ++----------------+-------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------+ +; JTAG usercode ; 0x00780971 ; +; Checksum ; 0x00780971 ; ++----------------+-------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:20:08 2026 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 517 megabytes + Info: Processing ended: Tue Sep 15 10:20:14 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.done b/Quartus/A1_Q6/output_files/instruction_classifier.done new file mode 100644 index 0000000..551cca3 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.done @@ -0,0 +1 @@ +Tue Sep 15 10:20:24 2026 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt new file mode 100644 index 0000000..158052b --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for instruction_classifier +Tue Sep 15 10:20:23 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:20:23 2026 ; +; Revision Name ; instruction_classifier ; +; Top-level Entity Name ; instruction_classifier ; +; Family ; Cyclone V ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ +; Tool Name ; Questa Altera FPGA (SystemVerilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------------------------------+ +; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo ; ++-----------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:20:22 2026 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file instruction_classifier.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/simulation/questa/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 659 megabytes + Info: Processing ended: Tue Sep 15 10:20:23 2026 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt new file mode 100644 index 0000000..2574dc1 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.fit.rpt @@ -0,0 +1,1396 @@ +Fitter report for instruction_classifier +Tue Sep 15 10:20:06 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. I/O Assignment Warnings + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Routing Usage Summary + 20. I/O Rules Summary + 21. I/O Rules Details + 22. I/O Rules Matrix + 23. Fitter Device Options + 24. Operating Settings and Conditions + 25. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Tue Sep 15 10:20:06 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; instruction_classifier ; +; Top-level Entity Name ; instruction_classifier ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 364 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total RAM Blocks ; 0 / 446 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.1% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 33 ) ; 0.00 % ( 0 / 33 ) ; 0.00 % ( 0 / 33 ) ; +; -- Achieved ; 0.00 % ( 0 / 33 ) ; 0.00 % ( 0 / 33 ) ; 0.00 % ( 0 / 33 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 33 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q6/output_files/instruction_classifier.pin. + + ++------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+--------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+--------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 5 / 29,080 ; < 1 % ; +; ALMs needed [=A-B+C] ; 5 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 5 / 29,080 ; < 1 % ; +; [a] ALMs used for LUT logic and registers ; 0 ; ; +; [b] ALMs used for LUT logic ; 5 ; ; +; [c] ALMs used for registers ; 0 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 0 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 2,908 ; < 1 % ; +; -- Logic LABs ; 2 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 7 ; ; +; -- 7 input functions ; 0 ; ; +; -- 6 input functions ; 2 ; ; +; -- 5 input functions ; 1 ; ; +; -- 4 input functions ; 1 ; ; +; -- <=3 input functions ; 3 ; ; +; Combinational ALUT usage for route-throughs ; 0 ; ; +; ; ; ; +; Dedicated logic registers ; 0 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58,160 ; 0 % ; +; -- Secondary logic registers ; 0 / 58,160 ; 0 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; ; +; -- Routing optimization registers ; 0 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 13 / 364 ; 4 % ; +; -- Clock pins ; 1 / 14 ; 7 % ; +; -- Dedicated input pins ; 0 / 23 ; 0 % ; +; ; ; ; +; M10K blocks ; 0 / 446 ; 0 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 0 / 4,567,040 ; 0 % ; +; Total block memory implementation bits ; 0 / 4,567,040 ; 0 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 150 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 0 ; ; +; -- Global clocks ; 0 / 16 ; 0 % ; +; -- Quadrant clocks ; 0 / 88 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ; +; SERDES Transmitters ; 0 / 88 ; 0 % ; +; SERDES Receivers ; 0 / 88 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Hard IPs ; 0 / 2 ; 0 % ; +; Standard RX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA RX Deserializers ; 0 / 6 ; 0 % ; +; Standard TX PCSs ; 0 / 6 ; 0 % ; +; HSSI PMA TX Serializers ; 0 / 6 ; 0 % ; +; Channel PLLs ; 0 / 6 ; 0 % ; +; Impedance control blocks ; 0 / 3 ; 0 % ; +; Hard Memory Controllers ; 0 / 2 ; 0 % ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; ; +; Maximum fan-out ; 7 ; ; +; Highest non-global fan-out ; 7 ; ; +; Total fan-out ; 46 ; ; +; Average fan-out ; 1.39 ; ; ++-------------------------------------------------------------+--------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+---------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 5 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 5 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 5 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 0 ; 0 ; +; [b] ALMs used for LUT logic ; 5 ; 0 ; +; [c] ALMs used for registers ; 0 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 0 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ; +; -- Logic LABs ; 2 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 7 ; 0 ; +; -- 7 input functions ; 0 ; 0 ; +; -- 6 input functions ; 2 ; 0 ; +; -- 5 input functions ; 1 ; 0 ; +; -- 4 input functions ; 1 ; 0 ; +; -- <=3 input functions ; 3 ; 0 ; +; Combinational ALUT usage for route-throughs ; 0 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 0 ; 0 ; +; -- Routing optimization registers ; 0 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 13 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 0 ; 0 ; +; Total block memory implementation bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 46 ; 0 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 6 ; 0 ; +; -- Output Ports ; 7 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+---------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; op[0] ; AB12 ; 3B ; 14 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[1] ; AB11 ; 3B ; 14 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[4] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; +; op[5] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ; ++-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; B1[0] ; AC10 ; 3B ; 12 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; B2[0] ; T13 ; 3B ; 15 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; F[0] ; Y10 ; 3B ; 15 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; I[0] ; R11 ; 3B ; 12 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; J[0] ; T12 ; 3B ; 15 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; M[0] ; T11 ; 3B ; 12 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; +; R[0] ; W10 ; 3B ; 15 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ; ++-------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++----------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+------------------+---------------+--------------+---------------+ +; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 13 / 32 ( 41 % ) ; 2.5V ; -- ; 2.5V ; +; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ; ++----------+------------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; 396 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; A3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A5 ; 344 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 392 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A11 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 332 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 330 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 300 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A16 ; 294 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A21 ; 274 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; 270 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A23 ; 268 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; 269 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA14 ; 87 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA24 ; 187 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA26 ; 201 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; 21 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB2 ; 20 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB10 ; 61 ; 3B ; op[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB11 ; 63 ; 3B ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB12 ; 65 ; 3B ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB24 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB25 ; 189 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 199 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; 18 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC4 ; 19 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC8 ; 62 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AC9 ; 64 ; 3B ; op[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AC10 ; 59 ; 3B ; B1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC23 ; 168 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC25 ; 193 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD1 ; 25 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD2 ; 24 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE4 ; 23 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; AE5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF5 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AF6 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF8 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF11 ; 101 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B5 ; 394 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; B6 ; 346 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 350 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B9 ; 314 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 334 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 328 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B14 ; 302 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; 304 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B16 ; ; 7A ; VREFB7AN0 ; power ; ; ; -- ; ; -- ; -- ; +; B17 ; 298 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B19 ; 282 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C7 ; 358 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; C9 ; 312 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 318 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; 338 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 336 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 307 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 306 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 280 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C22 ; 266 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 264 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; C25 ; 253 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C26 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D5 ; 395 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; D6 ; 352 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 356 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 372 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 340 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 342 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 341 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D15 ; 309 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 293 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 291 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D19 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D20 ; 277 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 275 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D23 ; 262 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D25 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D26 ; 227 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 354 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E8 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; 315 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 299 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E19 ; 285 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E20 ; 283 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E21 ; 259 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E22 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E23 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E24 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E25 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E26 ; 229 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F16 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F17 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F18 ; 301 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F19 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F21 ; 260 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F22 ; 261 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F23 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F24 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F25 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F26 ; 219 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G6 ; 362 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G7 ; 364 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 329 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 331 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G15 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G16 ; 279 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G17 ; 281 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G18 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G19 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G20 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G22 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G24 ; 237 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G25 ; 223 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 221 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H5 ; 400 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 263 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H17 ; 273 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; 271 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H19 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H20 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H21 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H22 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H23 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H24 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 225 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J5 ; 399 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J7 ; 370 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J8 ; 365 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; 369 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; 289 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J12 ; 287 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J16 ; 265 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J20 ; 254 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 256 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J22 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J23 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J25 ; 215 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 217 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 2 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 3 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K5 ; 397 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 373 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 363 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 361 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 367 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 305 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K21 ; 248 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K23 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K24 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K25 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K26 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L6 ; 393 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L7 ; 371 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 359 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 353 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; 337 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 303 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; ; 6A ; VCCPD6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L22 ; 246 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L23 ; 238 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 240 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L26 ; ; 6A ; VREFB6AN0 ; power ; ; ; -- ; ; -- ; -- ; +; M1 ; 5 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M2 ; 4 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M7 ; 391 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; 351 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 345 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 335 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 321 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M20 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M21 ; 216 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M22 ; 224 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M23 ; ; 6A ; VCCIO6A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M24 ; 220 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M25 ; 226 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 228 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; 1 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; N8 ; 36 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; N9 ; 343 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; 76 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; 319 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N20 ; 214 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N22 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N23 ; 222 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 218 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 210 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P1 ; 6 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P2 ; 7 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P4 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 200 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P21 ; 206 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 208 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P23 ; 192 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; P26 ; 212 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 60 ; 3B ; I[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R17 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R19 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R20 ; 198 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R22 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R23 ; 190 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R24 ; 194 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; 196 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R26 ; 204 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; 9 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T2 ; 8 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T4 ; ; -- ; VCCH_GXBL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 56 ; 3B ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 58 ; 3B ; M[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T12 ; 66 ; 3B ; J[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T13 ; 68 ; 3B ; B2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T17 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T18 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T19 ; 179 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 182 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 184 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T23 ; 186 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T24 ; 188 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T26 ; 202 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; -- ; VCCL_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; 108 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U25 ; 211 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 213 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 13 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V2 ; 12 ; B1L ; GND ; ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; 26 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V18 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V19 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; 10 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W4 ; 11 ; B1L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ; +; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; 69 ; 3B ; R[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W18 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W25 ; 207 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W26 ; 209 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y10 ; 67 ; 3B ; F[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y18 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y20 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y24 ; 180 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; 203 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y26 ; 205 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; R[0] ; Incomplete set of assignments ; +; B1[0] ; Incomplete set of assignments ; +; J[0] ; Incomplete set of assignments ; +; B2[0] ; Incomplete set of assignments ; +; I[0] ; Incomplete set of assignments ; +; F[0] ; Incomplete set of assignments ; +; M[0] ; Incomplete set of assignments ; +; op[0] ; Incomplete set of assignments ; +; op[1] ; Incomplete set of assignments ; +; op[2] ; Incomplete set of assignments ; +; op[3] ; Incomplete set of assignments ; +; op[4] ; Incomplete set of assignments ; +; op[5] ; Incomplete set of assignments ; +; R[0] ; Missing location assignment ; +; B1[0] ; Missing location assignment ; +; J[0] ; Missing location assignment ; +; B2[0] ; Missing location assignment ; +; I[0] ; Missing location assignment ; +; F[0] ; Missing location assignment ; +; M[0] ; Missing location assignment ; +; op[0] ; Missing location assignment ; +; op[1] ; Missing location assignment ; +; op[2] ; Missing location assignment ; +; op[3] ; Missing location assignment ; +; op[4] ; Missing location assignment ; +; op[5] ; Missing location assignment ; ++----------+-------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ +; |instruction_classifier ; 5.0 (5.0) ; 5.0 (5.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ; ++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-------------------------+------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++-------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; R[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; B1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; J[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; B2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; I[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; F[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; M[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; op[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ++-------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; op[0] ; ; ; +; - Equal0~0 ; 0 ; 0 ; +; - Equal1~0 ; 0 ; 0 ; +; op[1] ; ; ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; +; - Equal2~0 ; 1 ; 0 ; +; op[2] ; ; ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; +; - Equal2~0 ; 1 ; 0 ; +; - Equal3~0 ; 1 ; 0 ; +; op[3] ; ; ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; +; - Equal2~0 ; 1 ; 0 ; +; - Equal3~0 ; 1 ; 0 ; +; - Equal4~0 ; 1 ; 0 ; +; op[4] ; ; ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; +; - Equal2~0 ; 1 ; 0 ; +; - Equal3~0 ; 1 ; 0 ; +; - Equal4~0 ; 1 ; 0 ; +; - Equal5~0 ; 1 ; 0 ; +; op[5] ; ; ; +; - Equal0~0 ; 1 ; 0 ; +; - Equal1~0 ; 1 ; 0 ; +; - Equal2~0 ; 1 ; 0 ; +; - Equal3~0 ; 1 ; 0 ; +; - Equal4~0 ; 1 ; 0 ; +; - Equal5~0 ; 1 ; 0 ; +; - M[0]~output ; 1 ; 0 ; ++---------------------+-------------------+---------+ + + ++-------------------------------------------------------+ +; Routing Usage Summary ; ++------------------------------+------------------------+ +; Routing Resource Type ; Usage ; ++------------------------------+------------------------+ +; Block interconnects ; 13 / 217,884 ( < 1 % ) ; +; C12 interconnects ; 0 / 10,080 ( 0 % ) ; +; C2 interconnects ; 9 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 4 / 41,360 ( < 1 % ) ; +; DQS bus muxes ; 0 / 21 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; +; Direct links ; 0 / 217,884 ( 0 % ) ; +; Global clocks ; 0 / 16 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; +; Local interconnects ; 0 / 58,160 ( 0 % ) ; +; Quadrant clocks ; 0 / 88 ( 0 % ) ; +; R14 interconnects ; 0 / 9,228 ( 0 % ) ; +; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ; +; R3 interconnects ; 6 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 2 / 194,640 ( < 1 % ) ; +; Spine clocks ; 0 / 180 ( 0 % ) ; +; Wire stub REs ; 0 / 11,606 ( 0 % ) ; ++------------------------------+------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 6 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 22 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 13 ; 13 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 13 ; 13 ; 13 ; 6 ; 13 ; 0 ; 0 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; R[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; J[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; B2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; I[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; F[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; M[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; op[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device 5CGXFC5C6F27C7 for design "instruction_classifier" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 13 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Info (184020): Starting Fitter periphery placement operations +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:08 +Critical Warning (332012): Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:04 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1369 megabytes + Info: Processing ended: Tue Sep 15 10:20:07 2026 + Info: Elapsed time: 00:00:33 + Info: Total CPU time (on all processors): 00:00:49 + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary b/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary new file mode 100644 index 0000000..85e8078 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Sep 15 10:20:06 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : instruction_classifier +Top-level Entity Name : instruction_classifier +Family : Cyclone V +Device : 5CGXFC5C6F27C7 +Timing Models : Final +Logic utilization (in ALMs) : 5 / 29,080 ( < 1 % ) +Total registers : 0 +Total pins : 13 / 364 ( 4 % ) +Total virtual pins : 0 +Total block memory bits : 0 / 4,567,040 ( 0 % ) +Total RAM Blocks : 0 / 446 ( 0 % ) +Total DSP Blocks : 0 / 150 ( 0 % ) +Total HSSI RX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) +Total HSSI TX PCSs : 0 / 6 ( 0 % ) +Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) +Total PLLs : 0 / 12 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt new file mode 100644 index 0000000..a324f39 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.flow.rpt @@ -0,0 +1,136 @@ +Flow report for instruction_classifier +Tue Sep 15 10:20:23 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Tue Sep 15 10:20:23 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; instruction_classifier ; +; Top-level Entity Name ; instruction_classifier ; +; Family ; Cyclone V ; +; Device ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ; +; Total registers ; 0 ; +; Total pins ; 13 / 364 ( 4 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ; +; Total DSP Blocks ; 0 / 150 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % ) ; +; Total HSSI TX PCSs ; 0 / 6 ( 0 % ) ; +; Total HSSI PMA TX Serializers ; 0 / 6 ( 0 % ) ; +; Total PLLs ; 0 / 12 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+-------------------------------------------------+ + + ++--------------------------------------------+ +; Flow Settings ; ++-------------------+------------------------+ +; Option ; Setting ; ++-------------------+------------------------+ +; Start date & time ; 09/15/2026 10:19:22 ; +; Main task ; Compilation ; +; Revision Name ; instruction_classifier ; ++-------------------+------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; COMPILER_SIGNATURE_ID ; 253029099468756.178943156207722 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; +; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 413 MB ; 00:00:26 ; +; Fitter ; 00:00:32 ; 1.0 ; 1369 MB ; 00:00:48 ; +; Assembler ; 00:00:06 ; 1.0 ; 517 MB ; 00:00:06 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 785 MB ; 00:00:05 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 659 MB ; 00:00:01 ; +; Total ; 00:00:56 ; -- ; -- ; 00:01:26 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+---------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+---------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Fitter ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Assembler ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; Timing Analyzer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; +; EDA Netlist Writer ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ; ++----------------------+---------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier +quartus_fit --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier +quartus_asm --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier +quartus_sta A1_Q6 -c instruction_classifier +quartus_eda --read_settings_files=off --write_settings_files=off A1_Q6 -c instruction_classifier + + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.jdi b/Quartus/A1_Q6/output_files/instruction_classifier.jdi new file mode 100644 index 0000000..0ce9470 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt new file mode 100644 index 0000000..a54d795 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.map.rpt @@ -0,0 +1,284 @@ +Analysis & Synthesis report for instruction_classifier +Tue Sep 15 10:19:33 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++---------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:19:33 2026 ; +; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Revision Name ; instruction_classifier ; +; Top-level Entity Name ; instruction_classifier ; +; Family ; Cyclone V ; +; Logic utilization (in ALMs) ; N/A ; +; Total registers ; 0 ; +; Total pins ; 13 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 0 ; +; Total DSP Blocks ; 0 ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++---------------------------------+-------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++---------------------------------------------------------------------------------+------------------------+------------------------+ +; Option ; Setting ; Default Value ; ++---------------------------------------------------------------------------------+------------------------+------------------------+ +; Device ; 5CGXFC5C6F27C7 ; ; +; Top-level entity name ; instruction_classifier ; instruction_classifier ; +; Family name ; Cyclone V ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 3 ; 3 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Automatic Parallel Synthesis ; On ; On ; +; Partial Reconfiguration Bitstream ID ; Off ; Off ; ++---------------------------------------------------------------------------------+------------------------+------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++-----------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++-----------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------+---------+ +; ../../modules/instruction_classifier.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv ; ; ++-----------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimate of Logic utilization (ALMs needed) ; 4 ; +; ; ; +; Combinational ALUT usage for logic ; 6 ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 2 ; +; -- 5 input functions ; 1 ; +; -- 4 input functions ; 1 ; +; -- <=3 input functions ; 2 ; +; ; ; +; Dedicated logic registers ; 0 ; +; ; ; +; I/O pins ; 13 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; op[5]~input ; +; Maximum fan-out ; 7 ; +; Total fan-out ; 46 ; +; Average fan-out ; 1.44 ; ++---------------------------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------+------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------+------------------------+--------------+ +; |instruction_classifier ; 6 (6) ; 0 (0) ; 0 ; 0 ; 13 ; 0 ; |instruction_classifier ; instruction_classifier ; work ; ++----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------+------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; arriav_lcell_comb ; 6 ; +; normal ; 6 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 1 ; +; 5 data inputs ; 1 ; +; 6 data inputs ; 2 ; +; boundary_port ; 13 ; +; ; ; +; Max LUT depth ; 1.00 ; +; Average LUT depth ; 1.00 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:19:22 2026 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q6 -c instruction_classifier +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv + Info (12023): Found entity 1: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3 +Info (12127): Elaborating entity "instruction_classifier" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 19 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 6 input pins + Info (21059): Implemented 7 output pins + Info (21061): Implemented 6 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 430 megabytes + Info: Processing ended: Tue Sep 15 10:19:33 2026 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:26 + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.map.summary b/Quartus/A1_Q6/output_files/instruction_classifier.map.summary new file mode 100644 index 0000000..7748422 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.map.summary @@ -0,0 +1,17 @@ +Analysis & Synthesis Status : Successful - Tue Sep 15 10:19:33 2026 +Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Revision Name : instruction_classifier +Top-level Entity Name : instruction_classifier +Family : Cyclone V +Logic utilization (in ALMs) : N/A +Total registers : 0 +Total pins : 13 +Total virtual pins : 0 +Total block memory bits : 0 +Total DSP Blocks : 0 +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 +Total DLLs : 0 diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.pin b/Quartus/A1_Q6/output_files/instruction_classifier.pin new file mode 100644 index 0000000..b25b01e --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.pin @@ -0,0 +1,750 @@ + -- Copyright (C) 2025 Altera Corporation. All rights reserved. + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, the Altera Quartus Prime License Agreement, + -- the Altera IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Altera and sold by Altera or its authorized distributors. Please + -- refer to the Altera Software License Subscription Agreements + -- on the Quartus Prime software download page. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 3A: 2.5V + -- Bank 3B: 2.5V + -- Bank 4A: 2.5V + -- Bank 5A: 2.5V + -- Bank 5B: 2.5V + -- Bank 6A: 2.5V + -- Bank 7A: 2.5V + -- Bank 8A: 2.5V + -- Bank 9A: Dedicated configuration pins only, no VCCIO required. + -- RREF : External reference resistor for the quad, MUST be connected to + -- GND via a 2k Ohm resistor. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin + -- must not be connected. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +CHIP "instruction_classifier" ASSIGNED TO AN: 5CGXFC5C6F27C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +MSEL2 : A2 : : : : 9A : +DNU : A3 : : : : : +DNU : A4 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A : +CONF_DONE : A6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A : +VCCIO7A : A10 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A : +GND : A15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : +VCCIO7A : A20 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A : +GND : A25 : gnd : : : : +GND : AA1 : gnd : : : : +GND : AA2 : gnd : : : : +GXB_NC : AA3 : : : : B0L : +GXB_NC : AA4 : : : : B0L : +GND : AA5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A : +VCC_AUX : AA8 : power : : 2.5V : : +VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCCIO3B : AA10 : power : : 2.5V : 3B : +VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A : +NC : AA12 : : : : : +VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4A : +GND : AA15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A : +VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A : +VCCIO4A : AA20 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5B : +GND : AA25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : +GND : AB1 : : : : B0L : +GND : AB2 : : : : B0L : +GND : AB3 : gnd : : : : +GND : AB4 : gnd : : : : +AS_DATA2, DATA2 : AB5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A : +NC : AB7 : : : : : +GND : AB8 : gnd : : : : +VCCPD3A : AB9 : power : : 2.5V : 3A : +op[5] : AB10 : input : 2.5 V : : 3B : N +op[1] : AB11 : input : 2.5 V : : 3B : N +op[0] : AB12 : input : 2.5 V : : 3B : N +VCCIO4A : AB13 : power : : 2.5V : 4A : +VCC_AUX : AB14 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A : +GND : AB18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A : +VCC_AUX : AB20 : power : : 2.5V : : +VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A : +VCCIO5A : AB23 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B : +GND : AC1 : gnd : : : : +GND : AC2 : gnd : : : : +GXB_NC : AC3 : : : : B0L : +GXB_NC : AC4 : : : : B0L : +GND : AC5 : gnd : : : : +VCCIO3A : AC6 : power : : 2.5V : 3A : +VREFB3AN0 : AC7 : power : : : 3A : +op[3] : AC8 : input : 2.5 V : : 3B : N +op[4] : AC9 : input : 2.5 V : : 3B : N +B1[0] : AC10 : output : 2.5 V : : 3B : N +GND : AC11 : gnd : : : : +VREFB3BN0 : AC12 : power : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A : +VCCIO4A : AC16 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A : +GND : AC21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5B : +GND : AC26 : gnd : : : : +GND : AD1 : : : : B0L : +GND : AD2 : : : : B0L : +GND : AD3 : gnd : : : : +GND : AD4 : gnd : : : : +AS_DATA1, DATA1 : AD5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B : +VCCIO3B : AD9 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD13 : : : : 4A : +GND : AD14 : gnd : : : : +VREFB4AN0 : AD15 : power : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A : +VCCIO4A : AD19 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : +GND : AD24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A : +GND : AE1 : gnd : : : : +GND : AE2 : gnd : : : : +GXB_NC : AE3 : : : : B0L : +GXB_NC : AE4 : : : : B0L : +GND : AE5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3B : +GND : AE7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A : +VCCIO4A : AE12 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A : +GND : AE17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A : +VCCIO4A : AE22 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A : +GND : AF2 : gnd : : : : +GND : AF3 : gnd : : : : +GND : AF4 : gnd : : : : +AS_DATA0, ASDO, DATA0 : AF5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : +GND : AF10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A : +VCCIO4A : AF15 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A : +GND : AF20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A : +GND : AF25 : gnd : : : : +RREF : B1 : : : : : +GND : B2 : gnd : : : : +GND : B3 : gnd : : : : +GND : B4 : gnd : : : : +nSTATUS : B5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8A : +GND : B8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A : +VCCIO7A : B13 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A : +VREFB7AN0 : B16 : power : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A : +GND : B18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A : +VCCIO7A : B23 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : +GND : C1 : gnd : : : : +GND : C2 : gnd : : : : +NC : C3 : : : : : +NC : C4 : : : : : +GND : C5 : gnd : : : : +VCCIO8A : C6 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A : +VREFB8AN0 : C8 : power : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7A : +GND : C11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A : +VCCIO7A : C16 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A : +GND : C21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A : +DNU : C24 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 6A : +VCCIO6A : C26 : power : : 2.5V : 6A : +NC : D1 : : : : : +NC : D2 : : : : : +GND : D3 : gnd : : : : +GND : D4 : gnd : : : : +nCE : D5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A : +VCCIO8A : D9 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A : +GND : D14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A : +VCCIO7A : D19 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A : +GND : D23 : : : : 7A : +GND : D24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A : +GND : E1 : gnd : : : : +GND : E2 : gnd : : : : +NC : E3 : : : : : +NC : E4 : : : : : +GND : E5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8A : +GND : E7 : gnd : : : : +VCCBAT : E8 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A : +VCCIO7A : E12 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A : +VCC_AUX : E14 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7A : +GND : E17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6A : +VCCIO6A : E22 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A : +NC : F1 : : : : : +NC : F2 : : : : : +GND : F3 : gnd : : : : +GND : F4 : gnd : : : : +nCONFIG : F5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A : +VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : : +VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A : +GND : F10 : gnd : : : : +VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A : +VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A : +DNU : F14 : : : : : +VCCIO7A : F15 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A : +VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A : +VCCPD7A8A : F19 : power : : 2.5V : 7A, 8A : +GND : F20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A : +VCCIO6A : F25 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A : +GND : G1 : gnd : : : : +GND : G2 : gnd : : : : +NC : G3 : : : : : +NC : G4 : : : : : +GND : G5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A : +VCCIO8A : G8 : power : : 2.5V : 8A : +VCC_AUX : G9 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7A : +GND : G13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A : +VCCIO7A : G18 : power : : 2.5V : 7A : +VCC_AUX : G19 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A : +VCCA_FPLL : G21 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6A : +GND : G23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A : +NC : H1 : : : : : +NC : H2 : : : : : +GND : H3 : gnd : : : : +GND : H4 : gnd : : : : +GND : H5 : : : : 9A : +GND : H6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A : +VCCIO7A : H11 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A : +GND : H16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6A : +VCCIO6A : H21 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A : +GND : H26 : gnd : : : : +GND : J1 : gnd : : : : +GND : J2 : gnd : : : : +VCCL_GXBL : J3 : power : : 1.1V : : +GND : J4 : gnd : : : : +MSEL4 : J5 : : : : 9A : +VCCA_FPLL : J6 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 8A : +GND : J9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7A : +VCC : J13 : power : : 1.1V : : +GND : J14 : gnd : : : : +VCC : J15 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7A : +VCC : J17 : power : : 1.1V : : +GND : J18 : gnd : : : : +VCC : J19 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A : +VCCPD6A : J22 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A : +VCCIO6A : J24 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : +GXB_NC : K1 : : : : B1L : +GXB_NC : K2 : : : : B1L : +GND : K3 : gnd : : : : +VCCE_GXBL : K4 : power : : 1.1V : : +MSEL3 : K5 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 8A : +VCCIO8A : K7 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 7A : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCC : K14 : power : : 1.1V : : +GND : K15 : gnd : : : : +VCC : K16 : power : : 1.1V : : +GND : K17 : gnd : : : : +VCC : K18 : power : : 1.1V : : +GND : K19 : gnd : : : : +VCC : K20 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A : +GND : K22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : +GND : L1 : gnd : : : : +GND : L2 : gnd : : : : +VCCH_GXBL : L3 : power : : 2.5V : : +GND : L4 : gnd : : : : +NC : L5 : : : : : +MSEL1 : L6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 8A : +GND : L10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 7A : +VCC : L13 : power : : 1.1V : : +GND : L14 : gnd : : : : +VCC : L15 : power : : 1.1V : : +GND : L16 : gnd : : : : +VCC : L17 : power : : 1.1V : : +GND : L18 : gnd : : : : +VCC : L19 : power : : 1.1V : : +GND : L20 : gnd : : : : +VCCPD6A : L21 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A : +GND : L25 : gnd : : : : +VREFB6AN0 : L26 : power : : : 6A : +GND : M1 : : : : B1L : +GND : M2 : : : : B1L : +GND : M3 : gnd : : : : +VCCE_GXBL : M4 : power : : 1.1V : : +GND : M5 : gnd : : : : +NC : M6 : : : : : +MSEL0 : M7 : : : : 9A : +GND : M8 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 7A : +GND : M13 : gnd : : : : +VCC : M14 : power : : 1.1V : : +GND : M15 : gnd : : : : +VCC : M16 : power : : 1.1V : : +GND : M17 : gnd : : : : +VCC : M18 : power : : 1.1V : : +GND : M19 : gnd : : : : +VCC : M20 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A : +VCCIO6A : M23 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : +GND : N1 : gnd : : : : +GND : N2 : gnd : : : : +VCCL_GXBL : N3 : power : : 1.1V : : +GND : N4 : gnd : : : : +VCCE_GXBL : N5 : power : : 1.1V : : +GND : N6 : gnd : : : : +GND : N7 : : : : B1L : +DCLK : N8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N10 : : : : 3B : +GND : N11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 7A : +VCC : N13 : power : : 1.1V : : +GND : N14 : gnd : : : : +VCC : N15 : power : : 1.1V : : +GND : N16 : gnd : : : : +VCC : N17 : power : : 1.1V : : +GND : N18 : gnd : : : : +VCC : N19 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A : +GND : N21 : gnd : : : : +VCCPD5B : N22 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 5B : +VCCIO5B : N26 : power : : 2.5V : 5B : +GXB_NC : P1 : : : : B1L : +GXB_NC : P2 : : : : B1L : +GND : P3 : gnd : : : : +VCCE_GXBL : P4 : power : : 1.1V : : +GND : P5 : gnd : : : : +GND : P6 : : : : B1L : +GND : P7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A : +GND : P9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3B : +GND : P13 : gnd : : : : +VCC : P14 : power : : 1.1V : : +GND : P15 : gnd : : : : +VCC : P16 : power : : 1.1V : : +GND : P17 : gnd : : : : +VCC : P18 : power : : 1.1V : : +GND : P19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P23 : : : : 5B : +GND : P24 : gnd : : : : +VREFB5BN0 : P25 : power : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 5B : +GND : R1 : gnd : : : : +GND : R2 : gnd : : : : +VCCH_GXBL : R3 : power : : 2.5V : : +GND : R4 : gnd : : : : +VCCE_GXBL : R5 : power : : 1.1V : : +TMS : R6 : input : : : 3A : +GND : R7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A : +I[0] : R11 : output : 2.5 V : : 3B : N +GND : R12 : gnd : : : : +VCC : R13 : power : : 1.1V : : +GND : R14 : gnd : : : : +VCC : R15 : power : : 1.1V : : +GND : R16 : gnd : : : : +VCC : R17 : power : : 1.1V : : +GND : R18 : gnd : : : : +VCC : R19 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5B : +VCCPD5B : R21 : power : : 2.5V : 5B : +VCCIO5B : R22 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5B : +GND : T1 : : : : B1L : +GND : T2 : : : : B1L : +GND : T3 : gnd : : : : +VCCH_GXBL : T4 : power : : 2.5V : : +GND : T5 : gnd : : : : +TDI : T6 : input : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : +op[2] : T9 : input : 2.5 V : : 3B : N +GND : T10 : gnd : : : : +M[0] : T11 : output : 2.5 V : : 3B : N +J[0] : T12 : output : 2.5 V : : 3B : N +B2[0] : T13 : output : 2.5 V : : 3B : N +VCC : T14 : power : : 1.1V : : +GND : T15 : gnd : : : : +VCC : T16 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 4A : +VCC : T18 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5A : +GND : T20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 5B : +VCCIO5B : T25 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5B : +GND : U1 : gnd : : : : +GND : U2 : gnd : : : : +VCCL_GXBL : U3 : power : : 1.1V : : +GND : U4 : gnd : : : : +VCCE_GXBL : U5 : power : : 1.1V : : +AS_DATA3, DATA3 : U6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A : +VCCIO3B : U8 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A : +GND : U13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A : +VCCIO4A : U18 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A : +VCCPD5A : U21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A : +GND : U23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5B : +GND : V1 : : : : B1L : +GND : V2 : : : : B1L : +GND : V3 : gnd : : : : +GND : V4 : gnd : : : : +GND : V5 : gnd : : : : +GND : V6 : : : : B0L : +TDO : V7 : output : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B : +VCCIO3B : V11 : power : : 2.5V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A : +GND : V16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A : +VCCIO5A : V21 : power : : 2.5V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B : +GND : V26 : gnd : : : : +GND : W1 : gnd : : : : +GND : W2 : gnd : : : : +GXB_NC : W3 : : : : B1L : +GXB_NC : W4 : : : : B1L : +GND : W5 : gnd : : : : +GND : W6 : : : : B0L : +VCCA_FPLL : W7 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : +GND : W9 : gnd : : : : +R[0] : W10 : output : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A : +VCCIO4A : W14 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4A : +GND : W19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A : +VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : : +VREFB5AN0 : W23 : power : : : 5A : +VCCIO5B : W24 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B : +GND : Y1 : : : : B0L : +GND : Y2 : : : : B0L : +GND : Y3 : gnd : : : : +GND : Y4 : gnd : : : : +TCK : Y5 : input : : : 3A : +nCSO, DATA4 : Y6 : : : : 3A : +VCCIO3A : Y7 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A : +F[0] : Y10 : output : 2.5 V : : 3B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A : +VCCIO4A : Y17 : power : : 2.5V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 4A : +VCCA_FPLL : Y21 : power : : 2.5V : : +GND : Y22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B : diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sld b/Quartus/A1_Q6/output_files/instruction_classifier.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.sld @@ -0,0 +1 @@ + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sof b/Quartus/A1_Q6/output_files/instruction_classifier.sof new file mode 100644 index 0000000..bc6b1a2 Binary files /dev/null and b/Quartus/A1_Q6/output_files/instruction_classifier.sof differ diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt b/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt new file mode 100644 index 0000000..7a956ca --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.sta.rpt @@ -0,0 +1,538 @@ +Timing Analyzer report for instruction_classifier +Tue Sep 15 10:20:21 2026 +Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1100mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1100mV 85C Model Setup Summary + 8. Slow 1100mV 85C Model Hold Summary + 9. Slow 1100mV 85C Model Recovery Summary + 10. Slow 1100mV 85C Model Removal Summary + 11. Slow 1100mV 85C Model Minimum Pulse Width Summary + 12. Slow 1100mV 85C Model Metastability Summary + 13. Slow 1100mV 0C Model Fmax Summary + 14. Slow 1100mV 0C Model Setup Summary + 15. Slow 1100mV 0C Model Hold Summary + 16. Slow 1100mV 0C Model Recovery Summary + 17. Slow 1100mV 0C Model Removal Summary + 18. Slow 1100mV 0C Model Minimum Pulse Width Summary + 19. Slow 1100mV 0C Model Metastability Summary + 20. Fast 1100mV 85C Model Setup Summary + 21. Fast 1100mV 85C Model Hold Summary + 22. Fast 1100mV 85C Model Recovery Summary + 23. Fast 1100mV 85C Model Removal Summary + 24. Fast 1100mV 85C Model Minimum Pulse Width Summary + 25. Fast 1100mV 85C Model Metastability Summary + 26. Fast 1100mV 0C Model Setup Summary + 27. Fast 1100mV 0C Model Hold Summary + 28. Fast 1100mV 0C Model Recovery Summary + 29. Fast 1100mV 0C Model Removal Summary + 30. Fast 1100mV 0C Model Minimum Pulse Width Summary + 31. Fast 1100mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1100mv 0c Model) + 36. Signal Integrity Metrics (Slow 1100mv 85c Model) + 37. Signal Integrity Metrics (Fast 1100mv 0c Model) + 38. Signal Integrity Metrics (Fast 1100mv 85c Model) + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Unconstrained Input Ports + 44. Unconstrained Output Ports + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2025 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Altera and sold by Altera or its authorized distributors. Please +refer to the Altera Software License Subscription Agreements +on the Quartus Prime software download page. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; instruction_classifier ; +; Device Family ; Cyclone V ; +; Device Name ; 5CGXFC5C6F27C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.0% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1100mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +--------------------------------------- +; Fast 1100mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Fast 1100mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Fast 1100mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Fast 1100mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Fast 1100mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1100mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1100mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1100mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1100mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1100mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1100mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++-------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++-------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; R[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; B1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; J[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; B2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; I[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; F[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; M[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++-------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------+ +; Input Transition Times ; ++-------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------+--------------+-----------------+-----------------+ +; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; op[5] ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------+--------------+-----------------+-----------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 0c Model) ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 85c Model) ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 0c Model) ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 85c Model) ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; +; B1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; J[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; +; B2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; I[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; +; F[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; +; M[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; ++-------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 6 ; 6 ; +; Unconstrained Input Port Paths ; 27 ; 27 ; +; Unconstrained Output Ports ; 7 ; 7 ; +; Unconstrained Output Port Paths ; 27 ; 27 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; B1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; F[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; I[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; J[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; M[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; R[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; op[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; B1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; B2[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; F[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; I[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; J[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; M[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; R[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition + Info: Processing started: Tue Sep 15 10:20:15 2026 +Info: Command: quartus_sta A1_Q6 -c instruction_classifier +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'instruction_classifier.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1100mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1100mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 85C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1100mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 785 megabytes + Info: Processing ended: Tue Sep 15 10:20:21 2026 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/Quartus/A1_Q6/output_files/instruction_classifier.sta.summary b/Quartus/A1_Q6/output_files/instruction_classifier.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/Quartus/A1_Q6/output_files/instruction_classifier.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/Quartus/A1_Q6/simulation/questa/instruction_classifier.sft b/Quartus/A1_Q6/simulation/questa/instruction_classifier.sft new file mode 100644 index 0000000..dfcc4cf --- /dev/null +++ b/Quartus/A1_Q6/simulation/questa/instruction_classifier.sft @@ -0,0 +1 @@ +set tool_name "Questa Altera FPGA (SystemVerilog)" diff --git a/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo b/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo new file mode 100644 index 0000000..3cdb032 --- /dev/null +++ b/Quartus/A1_Q6/simulation/questa/instruction_classifier.svo @@ -0,0 +1,437 @@ +// Copyright (C) 2025 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, the Altera Quartus Prime License Agreement, +// the Altera IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Altera and sold by Altera or its authorized distributors. Please +// refer to the Altera Software License Subscription Agreements +// on the Quartus Prime software download page. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" + +// DATE "09/15/2026 10:20:23" + +// +// Device: Altera 5CGXFC5C6F27C7 Package FBGA672 +// + +// +// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only +// + +`timescale 1 ps/ 1 ps + +module instruction_classifier ( + op, + R, + B1, + J, + B2, + I, + F, + M); +input logic [5:0] op ; +output logic [0:0] R ; +output logic [0:0] B1 ; +output logic [0:0] J ; +output logic [0:0] B2 ; +output logic [0:0] I ; +output logic [0:0] F ; +output logic [0:0] M ; + +// Design Ports Information +// R[0] => Location: PIN_W10, I/O Standard: 2.5 V, Current Strength: Default +// B1[0] => Location: PIN_AC10, I/O Standard: 2.5 V, Current Strength: Default +// J[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default +// B2[0] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default +// I[0] => Location: PIN_R11, I/O Standard: 2.5 V, Current Strength: Default +// F[0] => Location: PIN_Y10, I/O Standard: 2.5 V, Current Strength: Default +// M[0] => Location: PIN_T11, I/O Standard: 2.5 V, Current Strength: Default +// op[0] => Location: PIN_AB12, I/O Standard: 2.5 V, Current Strength: Default +// op[1] => Location: PIN_AB11, I/O Standard: 2.5 V, Current Strength: Default +// op[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// op[3] => Location: PIN_AC8, I/O Standard: 2.5 V, Current Strength: Default +// op[4] => Location: PIN_AC9, I/O Standard: 2.5 V, Current Strength: Default +// op[5] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \~QUARTUS_CREATED_GND~I_combout ; +wire \op[5]~input_o ; +wire \op[0]~input_o ; +wire \op[2]~input_o ; +wire \op[1]~input_o ; +wire \op[4]~input_o ; +wire \op[3]~input_o ; +wire \Equal0~0_combout ; +wire \Equal1~0_combout ; +wire \Equal2~0_combout ; +wire \Equal3~0_combout ; +wire \Equal4~0_combout ; +wire \Equal5~0_combout ; + + +// Location: IOOBUF_X15_Y0_N36 +cyclonev_io_obuf \R[0]~output ( + .i(\Equal0~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(R[0]), + .obar()); +// synopsys translate_off +defparam \R[0]~output .bus_hold = "false"; +defparam \R[0]~output .open_drain_output = "false"; +defparam \R[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X12_Y0_N53 +cyclonev_io_obuf \B1[0]~output ( + .i(\Equal1~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(B1[0]), + .obar()); +// synopsys translate_off +defparam \B1[0]~output .bus_hold = "false"; +defparam \B1[0]~output .open_drain_output = "false"; +defparam \B1[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X15_Y0_N19 +cyclonev_io_obuf \J[0]~output ( + .i(\Equal2~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(J[0]), + .obar()); +// synopsys translate_off +defparam \J[0]~output .bus_hold = "false"; +defparam \J[0]~output .open_drain_output = "false"; +defparam \J[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X15_Y0_N2 +cyclonev_io_obuf \B2[0]~output ( + .i(\Equal3~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(B2[0]), + .obar()); +// synopsys translate_off +defparam \B2[0]~output .bus_hold = "false"; +defparam \B2[0]~output .open_drain_output = "false"; +defparam \B2[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X12_Y0_N2 +cyclonev_io_obuf \I[0]~output ( + .i(\Equal4~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(I[0]), + .obar()); +// synopsys translate_off +defparam \I[0]~output .bus_hold = "false"; +defparam \I[0]~output .open_drain_output = "false"; +defparam \I[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X15_Y0_N53 +cyclonev_io_obuf \F[0]~output ( + .i(\Equal5~0_combout ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(F[0]), + .obar()); +// synopsys translate_off +defparam \F[0]~output .bus_hold = "false"; +defparam \F[0]~output .open_drain_output = "false"; +defparam \F[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOOBUF_X12_Y0_N19 +cyclonev_io_obuf \M[0]~output ( + .i(\op[5]~input_o ), + .oe(vcc), + .dynamicterminationcontrol(gnd), + .seriesterminationcontrol(16'b0000000000000000), + .parallelterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(M[0]), + .obar()); +// synopsys translate_off +defparam \M[0]~output .bus_hold = "false"; +defparam \M[0]~output .open_drain_output = "false"; +defparam \M[0]~output .shift_series_termination_control = "false"; +// synopsys translate_on + +// Location: IOIBUF_X12_Y0_N35 +cyclonev_io_ibuf \op[5]~input ( + .i(op[5]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[5]~input_o )); +// synopsys translate_off +defparam \op[5]~input .bus_hold = "false"; +defparam \op[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N1 +cyclonev_io_ibuf \op[0]~input ( + .i(op[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[0]~input_o )); +// synopsys translate_off +defparam \op[0]~input .bus_hold = "false"; +defparam \op[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X10_Y0_N75 +cyclonev_io_ibuf \op[2]~input ( + .i(op[2]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[2]~input_o )); +// synopsys translate_off +defparam \op[2]~input .bus_hold = "false"; +defparam \op[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N18 +cyclonev_io_ibuf \op[1]~input ( + .i(op[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[1]~input_o )); +// synopsys translate_off +defparam \op[1]~input .bus_hold = "false"; +defparam \op[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N35 +cyclonev_io_ibuf \op[4]~input ( + .i(op[4]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[4]~input_o )); +// synopsys translate_off +defparam \op[4]~input .bus_hold = "false"; +defparam \op[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y0_N52 +cyclonev_io_ibuf \op[3]~input ( + .i(op[3]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\op[3]~input_o )); +// synopsys translate_off +defparam \op[3]~input .bus_hold = "false"; +defparam \op[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N30 +cyclonev_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (!\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) ) + + .dataa(!\op[5]~input_o ), + .datab(!\op[0]~input_o ), + .datac(!\op[2]~input_o ), + .datad(!\op[1]~input_o ), + .datae(!\op[4]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal0~0 .extended_lut = "off"; +defparam \Equal0~0 .lut_mask = 64'h8000000000000000; +defparam \Equal0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N6 +cyclonev_lcell_comb \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[0]~input_o & (!\op[2]~input_o & !\op[1]~input_o ))) ) ) ) + + .dataa(!\op[5]~input_o ), + .datab(!\op[0]~input_o ), + .datac(!\op[2]~input_o ), + .datad(!\op[1]~input_o ), + .datae(!\op[4]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal1~0 .extended_lut = "off"; +defparam \Equal1~0 .lut_mask = 64'h2000000000000000; +defparam \Equal1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N42 +cyclonev_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (!\op[5]~input_o & (\op[1]~input_o & !\op[2]~input_o )) ) ) ) + + .dataa(!\op[5]~input_o ), + .datab(!\op[1]~input_o ), + .datac(!\op[2]~input_o ), + .datad(gnd), + .datae(!\op[4]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal2~0 .extended_lut = "off"; +defparam \Equal2~0 .lut_mask = 64'h2020000000000000; +defparam \Equal2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N51 +cyclonev_lcell_comb \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = ( !\op[4]~input_o & ( !\op[3]~input_o & ( (\op[2]~input_o & !\op[5]~input_o ) ) ) ) + + .dataa(!\op[2]~input_o ), + .datab(gnd), + .datac(gnd), + .datad(!\op[5]~input_o ), + .datae(!\op[4]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal3~0 .extended_lut = "off"; +defparam \Equal3~0 .lut_mask = 64'h5500000000000000; +defparam \Equal3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N24 +cyclonev_lcell_comb \Equal4~0 ( +// Equation(s): +// \Equal4~0_combout = ( !\op[4]~input_o & ( \op[3]~input_o & ( !\op[5]~input_o ) ) ) + + .dataa(gnd), + .datab(gnd), + .datac(!\op[5]~input_o ), + .datad(gnd), + .datae(!\op[4]~input_o ), + .dataf(!\op[3]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal4~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal4~0 .extended_lut = "off"; +defparam \Equal4~0 .lut_mask = 64'h00000000F0F00000; +defparam \Equal4~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X14_Y1_N3 +cyclonev_lcell_comb \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = ( \op[4]~input_o & ( !\op[5]~input_o ) ) + + .dataa(!\op[5]~input_o ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(!\op[4]~input_o ), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Equal5~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Equal5~0 .extended_lut = "off"; +defparam \Equal5~0 .lut_mask = 64'h0000AAAA0000AAAA; +defparam \Equal5~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: MLABCELL_X55_Y25_N3 +cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( +// Equation(s): + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .datae(gnd), + .dataf(gnd), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\~QUARTUS_CREATED_GND~I_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off"; +defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000; +defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off"; +// synopsys translate_on + +endmodule