TroubleElectrical/FPGA_Uni
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Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
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commit 05361dcf70
349 files changed
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Quartus/A1_Q5/db/shifter.hier_info
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|shifter
op[0] => Mux0.IN8
op[0] => Mux1.IN8
op[0] => Mux2.IN8
op[0] => Mux3.IN8
op[0] => Mux4.IN8
op[0] => Mux5.IN8
op[0] => Mux6.IN8
op[0] => Mux7.IN8
op[1] => Mux0.IN7
op[1] => Mux1.IN7
op[1] => Mux2.IN7
op[1] => Mux3.IN7
op[1] => Mux4.IN7
op[1] => Mux5.IN7
op[1] => Mux6.IN7
op[1] => Mux7.IN7
op[2] => Mux0.IN6
op[2] => Mux1.IN6
op[2] => Mux2.IN6
op[2] => Mux3.IN6
op[2] => Mux4.IN6
op[2] => Mux5.IN6
op[2] => Mux6.IN6
op[2] => Mux7.IN6
A[0] => ShiftLeft0.IN8
A[0] => ShiftRight0.IN8
A[0] => ShiftRight1.IN8
A[0] => ShiftLeft1.IN8
A[0] => ShiftRight2.IN8
A[0] => ShiftRight3.IN8
A[0] => Mux7.IN9
A[0] => Mux7.IN10
A[1] => ShiftLeft0.IN7
A[1] => ShiftRight0.IN7
A[1] => ShiftRight1.IN7
A[1] => ShiftLeft1.IN7
A[1] => ShiftRight2.IN7
A[1] => ShiftRight3.IN7
A[1] => Mux6.IN9
A[1] => Mux6.IN10
A[2] => ShiftLeft0.IN6
A[2] => ShiftRight0.IN6
A[2] => ShiftRight1.IN6
A[2] => ShiftLeft1.IN6
A[2] => ShiftRight2.IN6
A[2] => ShiftRight3.IN6
A[2] => Mux5.IN9
A[2] => Mux5.IN10
A[3] => ShiftLeft0.IN5
A[3] => ShiftRight0.IN5
A[3] => ShiftRight1.IN5
A[3] => ShiftLeft1.IN5
A[3] => ShiftRight2.IN5
A[3] => ShiftRight3.IN5
A[3] => Mux4.IN9
A[3] => Mux4.IN10
A[4] => ShiftLeft0.IN4
A[4] => ShiftRight0.IN4
A[4] => ShiftRight1.IN4
A[4] => ShiftLeft1.IN4
A[4] => ShiftRight2.IN4
A[4] => ShiftRight3.IN4
A[4] => Mux3.IN9
A[4] => Mux3.IN10
A[5] => ShiftLeft0.IN3
A[5] => ShiftRight0.IN3
A[5] => ShiftRight1.IN3
A[5] => ShiftLeft1.IN3
A[5] => ShiftRight2.IN3
A[5] => ShiftRight3.IN3
A[5] => Mux2.IN9
A[5] => Mux2.IN10
A[6] => ShiftLeft0.IN2
A[6] => ShiftRight0.IN2
A[6] => ShiftRight1.IN2
A[6] => ShiftLeft1.IN2
A[6] => ShiftRight2.IN2
A[6] => ShiftRight3.IN2
A[6] => Mux1.IN9
A[6] => Mux1.IN10
A[7] => ShiftLeft0.IN1
A[7] => ShiftRight0.IN1
A[7] => ShiftRight1.IN0
A[7] => ShiftRight1.IN1
A[7] => ShiftLeft1.IN1
A[7] => ShiftRight2.IN1
A[7] => ShiftRight3.IN0
A[7] => ShiftRight3.IN1
A[7] => Mux0.IN9
A[7] => Mux0.IN10
C[0] => ShiftLeft0.IN16
C[0] => ShiftRight0.IN16
C[0] => ShiftRight1.IN16
C[1] => ShiftLeft0.IN15
C[1] => ShiftRight0.IN15
C[1] => ShiftRight1.IN15
C[2] => ShiftLeft0.IN14
C[2] => ShiftRight0.IN14
C[2] => ShiftRight1.IN14
C[3] => ShiftLeft0.IN13
C[3] => ShiftRight0.IN13
C[3] => ShiftRight1.IN13
C[4] => ShiftLeft0.IN12
C[4] => ShiftRight0.IN12
C[4] => ShiftRight1.IN12
C[5] => ShiftLeft0.IN11
C[5] => ShiftRight0.IN11
C[5] => ShiftRight1.IN11
C[6] => ShiftLeft0.IN10
C[6] => ShiftRight0.IN10
C[6] => ShiftRight1.IN10
C[7] => ShiftLeft0.IN9
C[7] => ShiftRight0.IN9
C[7] => ShiftRight1.IN9
B[0] => ShiftLeft1.IN11
B[0] => ShiftRight2.IN11
B[0] => ShiftRight3.IN11
B[1] => ShiftLeft1.IN10
B[1] => ShiftRight2.IN10
B[1] => ShiftRight3.IN10
B[2] => ShiftLeft1.IN9
B[2] => ShiftRight2.IN9
B[2] => ShiftRight3.IN9
OUT_1[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
OUT_1[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE