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Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
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Quartus/A1_Q4/output_files/alu.map.rpt
+80 -105
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for alu
Wed Sep 9 14:22:23 2026
Tue Sep 15 10:03:28 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -14,14 +14,13 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Parameter Settings for User Entity Instance: Top-level Entity: |alu
10. Parameter Settings for User Entity Instance: asu:adder_unit
11. Parameter Settings for User Entity Instance: lu:logic_unit
12. Port Connectivity Checks: "lu:logic_unit"
13. Port Connectivity Checks: "asu:adder_unit"
14. Post-Synthesis Netlist Statistics for Top Partition
15. Elapsed Time Per Partition
16. Analysis & Synthesis Messages
9. Multiplexer Restructuring Statistics (Restructuring Performed)
10. Parameter Settings for User Entity Instance: Top-level Entity: |alu
11. Parameter Settings for User Entity Instance: asu:adder_unit
12. Parameter Settings for User Entity Instance: lu:logic_unit
13. Post-Synthesis Netlist Statistics for Top Partition
14. Elapsed Time Per Partition
15. Analysis & Synthesis Messages
@@ -48,7 +47,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Sep 9 14:22:23 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:03:28 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
@@ -171,42 +170,42 @@ on the Quartus Prime software download page.
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
; asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv ; ;
; lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimate of Logic utilization (ALMs needed) ; 0 ;
; ; ;
; Combinational ALUT usage for logic ; 0 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 0 ;
; -- <=3 input functions ; 0 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 18 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[0] ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 18 ;
; Average fan-out ; 0.50 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimate of Logic utilization (ALMs needed) ; 10 ;
; ; ;
; Combinational ALUT usage for logic ; 14 ;
; -- 7 input functions ; 3 ;
; -- 6 input functions ; 3 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 1 ;
; -- <=3 input functions ; 7 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 18 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; op[2]~input ;
; Maximum fan-out ; 7 ;
; Total fan-out ; 84 ;
; Average fan-out ; 1.68 ;
+---------------------------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -214,7 +213,8 @@ on the Quartus Prime software download page.
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |alu ; 0 (0) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
; |alu ; 14 (8) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
; |asu:adder_unit| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -234,6 +234,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 7:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |alu|Mux2 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |alu ;
+----------------+-------+--------------------------------------------+
@@ -264,39 +273,26 @@ Note: In order to hide this table in the UI and the text report file, please set
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "lu:logic_unit" ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
; Y ; Output ; Warning ; Output or bidir port (4 bits) is wider than the port expression (2 bits) it drives; bit(s) "Y[3..2]" have no fanouts ;
; Y ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "asu:adder_unit" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; COUT ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; OUT_CIN ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 1 ;
; normal ; 1 ;
; arriav_lcell_comb ; 14 ;
; extend ; 3 ;
; 7 data inputs ; 3 ;
; normal ; 6 ;
; 2 data inputs ; 1 ;
; 3 data inputs ; 1 ;
; 4 data inputs ; 1 ;
; 6 data inputs ; 3 ;
; shared ; 5 ;
; 0 data inputs ; 1 ;
; 2 data inputs ; 4 ;
; boundary_port ; 18 ;
; ; ;
; Max LUT depth ; 0.00 ;
; Average LUT depth ; 0.00 ;
; Max LUT depth ; 2.40 ;
; Average LUT depth ; 2.20 ;
+-----------------------+-----------------------------+
@@ -315,49 +311,28 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Wed Sep 9 14:22:13 2026
Info: Processing started: Tue Sep 15 10:03:17 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1
Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 1
Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv Line: 4
Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv Line: 3
Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
Info (12127): Elaborating entity "alu" for the top level hierarchy
Warning (10034): Output port "OUT_1" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (10034): Output port "flags" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 13
Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "OUT_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (13410): Pin "OUT_1[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (13410): Pin "OUT_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (13410): Pin "OUT_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (13410): Pin "flags[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Warning (13410): Pin "flags[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16
Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 19
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 12 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "op[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
Warning (15610): No output dependent on input pin "op[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
Warning (15610): No output dependent on input pin "op[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
Warning (15610): No output dependent on input pin "op[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
Warning (15610): No output dependent on input pin "A[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "A[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "A[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "A[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "B[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "B[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "B[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Warning (15610): No output dependent on input pin "B[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 32 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 12 input pins
Info (21059): Implemented 6 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 24 warnings
Info: Peak virtual memory: 425 megabytes
Info: Processing ended: Wed Sep 9 14:22:23 2026
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:24
Info (21061): Implemented 14 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 436 megabytes
Info: Processing ended: Tue Sep 15 10:03:28 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:27