TroubleElectrical/FPGA_Uni
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Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
1 parent c4ebde7692
commit 05361dcf70
349 files changed
+15719 -1096
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Quartus/A1_Q4/output_files/alu.flow.rpt
+11 -11
View File
@@ -1,5 +1,5 @@
Flow report for alu
Wed Sep 9 14:23:06 2026
Tue Sep 15 10:04:15 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,14 +41,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Wed Sep 9 14:23:06 2026 ;
; Flow Status ; Successful - Tue Sep 15 10:04:15 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 18 / 364 ( 5 % ) ;
; Total virtual pins ; 0 ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/09/2026 14:22:13 ;
; Start date & time ; 09/15/2026 10:03:17 ;
; Main task ; Compilation ;
; Revision Name ; alu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.178892773303605 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 253029099468756.178943059705529 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:23 ;
; Fitter ; 00:00:27 ; 1.0 ; 1342 MB ; 00:00:38 ;
; Assembler ; 00:00:05 ; 1.0 ; 516 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 760 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:48 ; -- ; -- ; 00:01:12 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
; Fitter ; 00:00:30 ; 1.0 ; 1388 MB ; 00:00:43 ;
; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 793 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:53 ; -- ; -- ; 00:01:21 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+