Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
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`ifndef LU_H_SV
`define LU_H_SV
module lu #(parameter width = 2) (
input logic [1:0] op,
input logic [2**width-1:0] A,
input logic [2**width-1:0] B,
output logic [2**width-1:0] Y);
always_comb begin
case (op)
2'b00: Y = A & B;
2'b01: Y = A | B;
2'b10: Y = A ^ B;
2'b11: Y = ~(A | B);
default:Y = '0;
endcase
end
endmodule
`endif