Added all Testbenches to Modelsim and confirmed working operation

Quartus/A1_Q4/db/alu.hier_info

@@ -1,8 +1,14 @@
 |alu
 op[0] => op[0].IN1
 op[1] => op[1].IN1
-op[2] => ~NO_FANOUT~
-op[3] => ~NO_FANOUT~
+op[2] => Mux0.IN3
+op[2] => Mux1.IN3
+op[2] => Mux2.IN3
+op[2] => Mux3.IN9
+op[3] => Mux0.IN2
+op[3] => Mux1.IN2
+op[3] => Mux2.IN2
+op[3] => Mux3.IN8
 A[0] => A[0].IN2
 A[1] => A[1].IN2
 A[2] => A[2].IN2
@@ -11,29 +17,33 @@ B[0] => B[0].IN2
 B[1] => B[1].IN2
 B[2] => B[2].IN2
 B[3] => B[3].IN2
-OUT_1[0] <= <GND>
-OUT_1[1] <= <GND>
-OUT_1[2] <= <GND>
-OUT_1[3] <= <GND>
-flags[0] <= <GND>
-flags[1] <= <GND>
+OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
+OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
+flags[0] <= asu:adder_unit.port4
+flags[1] <= asu:adder_unit.port5
 
 
 |alu|asu:adder_unit
-op[0] => operand[0].IN0
-op[0] => operand[1].IN0
-op[0] => operand[2].IN0
-op[0] => operand[3].IN0
+op[0] => operand[3].OUTPUTSELECT
+op[0] => operand[2].OUTPUTSELECT
+op[0] => operand[1].OUTPUTSELECT
+op[0] => operand[0].OUTPUTSELECT
 op[0] => _.DATAB
 A[0] => _.DATAD
 A[1] => _.DATAD
 A[2] => _.DATAD
 A[3] => OUT_CIN.IN1
 A[3] => _.DATAD
-B[0] => operand[0].IN1
-B[1] => operand[1].IN1
-B[2] => operand[2].IN1
-B[3] => operand[3].IN1
+B[0] => operand[0].DATAB
+B[0] => operand[0].DATAA
+B[1] => operand[1].DATAB
+B[1] => operand[1].DATAA
+B[2] => operand[2].DATAB
+B[2] => operand[2].DATAA
+B[3] => operand[3].DATAB
+B[3] => operand[3].DATAA
 OUT_1[0] <= _.SUM_OUT
 OUT_1[1] <= _.SUM_OUT
 OUT_1[2] <= _.SUM_OUT