Added all Testbenches to Modelsim and confirmed working operation
This commit is contained in:
TroubleElectrical committed
1 parent
c4ebde7692
commit
05361dcf70
349 files changed
+15719
-1096
No files matched your search
@@ -0,0 +1,22 @@
|
||||
`ifndef ASU_H_SV
|
||||
`define ASU_H_SV
|
||||
|
||||
module asu #(parameter width = 2)(
|
||||
input logic [0:0] op,
|
||||
input logic[2**width-1:0] A, input logic[2**width-1:0] B,
|
||||
output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
|
||||
|
||||
logic [2**width-1:0] operand;
|
||||
always_comb begin
|
||||
// A + (sub) ? B : -B
|
||||
// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
|
||||
//operand = (B ^ {(2**width){op}});
|
||||
operand = op == 1'b0 ? B : ~B;
|
||||
{COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
|
||||
end
|
||||
|
||||
// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
|
||||
// Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
|
||||
assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
|
||||
endmodule
|
||||
`endif
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,6 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927773356 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927773357 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:53 2026 " "Processing started: Wed Sep 9 14:22:53 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927773357 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788927773357 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788927773357 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788927774010 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788927778263 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "516 " "Peak virtual memory: 516 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:58 2026 " "Processing ended: Wed Sep 9 14:22:58 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927778461 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788927778461 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430641404 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:01 2026 " "Processing started: Tue Sep 15 10:04:01 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430641405 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789430641405 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789430642068 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789430646380 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:06 2026 " "Processing ended: Tue Sep 15 10:04:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430646577 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789430646577 ""}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -33,24 +33,24 @@ IO_RULES_MATRIX,Total Pass,0;0;0;0;0;18;0;0;0;0;0;0;0;6;0;0;0;0;6;0;0;0;0;6;0;18
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,18;18;18;18;18;0;18;18;18;18;18;18;18;12;18;18;18;18;12;18;18;18;18;12;18;0;0;18,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,OUT_1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,OUT_1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,OUT_1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,OUT_1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,flags[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,flags[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,op[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,A[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,28,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,3 +1,3 @@
|
||||
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Version_Index = 604268800
|
||||
Creation_Time = Thu Sep 10 14:53:57 2026
|
||||
Creation_Time = Tue Sep 15 10:02:02 2026
|
||||
@@ -1,6 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927786173 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927786174 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:23:05 2026 " "Processing started: Wed Sep 9 14:23:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927786174 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786174 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786174 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788927786909 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788927786950 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:23:06 2026 " "Processing ended: Wed Sep 9 14:23:06 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927786981 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788927786981 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430654884 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:14 2026 " "Processing started: Tue Sep 15 10:04:14 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430654884 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu " "Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430654884 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789430655640 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "alu.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/ simulation " "Generated file alu.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789430655696 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:15 2026 " "Processing ended: Tue Sep 15 10:04:15 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430655731 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789430655731 ""}
|
||||
@@ -1,44 +1,44 @@
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788927745146 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788927745146 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788927745151 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927745220 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788927745220 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788927745630 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788927745657 ""}
|
||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788927745702 ""}
|
||||
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1788927745949 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788927752374 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927752460 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788927752462 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788927752463 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788927752464 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788927752464 ""}
|
||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927752477 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788927758260 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788927758261 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788927758261 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788927758262 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788927758262 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788927758262 ""}
|
||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788927758263 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788927758265 ""}
|
||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788927758304 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927758698 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788927758958 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788927759227 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927759228 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788927759766 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y24 X10_Y36 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36"} { { 12 { 0 ""} 0 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788927765042 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788927765042 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788927765181 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788927765181 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788927765181 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927765183 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.06 " "Total time spent on timing analysis during the Fitter is 0.06 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788927767056 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927767089 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927767455 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788927767455 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788927767964 ""}
|
||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788927771013 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1342 " "Peak virtual memory: 1342 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:51 2026 " "Processing ended: Wed Sep 9 14:22:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927771810 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788927771810 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789430610558 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789430610558 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "alu 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"alu\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789430610563 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789430610632 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789430611045 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789430611073 ""}
|
||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789430611121 ""}
|
||||
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "No exact pin location assignment(s) for 18 pins of 18 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789430611389 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789430617956 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618032 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789430618036 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618036 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789430618037 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789430618037 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789430618038 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789430618038 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789430618038 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789430618038 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789430618038 ""}
|
||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430618057 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789430623909 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789430623909 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789430623910 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789430623910 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789430623911 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789430623911 ""}
|
||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789430623912 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789430623914 ""}
|
||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789430623985 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430626215 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789430627179 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789430627539 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430627539 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789430628497 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789430634025 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789430634025 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789430634284 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789430634284 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430634286 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789430635157 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635194 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430635550 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789430635550 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789430636274 ""}
|
||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789430638928 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1388 " "Peak virtual memory: 1388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:59 2026 " "Processing ended: Tue Sep 15 10:03:59 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430639787 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789430639787 ""}
|
||||
@@ -1,8 +1,14 @@
|
||||
|alu
|
||||
op[0] => op[0].IN1
|
||||
op[1] => op[1].IN1
|
||||
op[2] => ~NO_FANOUT~
|
||||
op[3] => ~NO_FANOUT~
|
||||
op[2] => Mux0.IN3
|
||||
op[2] => Mux1.IN3
|
||||
op[2] => Mux2.IN3
|
||||
op[2] => Mux3.IN9
|
||||
op[3] => Mux0.IN2
|
||||
op[3] => Mux1.IN2
|
||||
op[3] => Mux2.IN2
|
||||
op[3] => Mux3.IN8
|
||||
A[0] => A[0].IN2
|
||||
A[1] => A[1].IN2
|
||||
A[2] => A[2].IN2
|
||||
@@ -11,29 +17,33 @@ B[0] => B[0].IN2
|
||||
B[1] => B[1].IN2
|
||||
B[2] => B[2].IN2
|
||||
B[3] => B[3].IN2
|
||||
OUT_1[0] <= <GND>
|
||||
OUT_1[1] <= <GND>
|
||||
OUT_1[2] <= <GND>
|
||||
OUT_1[3] <= <GND>
|
||||
flags[0] <= <GND>
|
||||
flags[1] <= <GND>
|
||||
OUT_1[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
||||
OUT_1[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
||||
OUT_1[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
||||
OUT_1[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
flags[0] <= asu:adder_unit.port4
|
||||
flags[1] <= asu:adder_unit.port5
|
||||
|
||||
|
||||
|alu|asu:adder_unit
|
||||
op[0] => operand[0].IN0
|
||||
op[0] => operand[1].IN0
|
||||
op[0] => operand[2].IN0
|
||||
op[0] => operand[3].IN0
|
||||
op[0] => operand[3].OUTPUTSELECT
|
||||
op[0] => operand[2].OUTPUTSELECT
|
||||
op[0] => operand[1].OUTPUTSELECT
|
||||
op[0] => operand[0].OUTPUTSELECT
|
||||
op[0] => _.DATAB
|
||||
A[0] => _.DATAD
|
||||
A[1] => _.DATAD
|
||||
A[2] => _.DATAD
|
||||
A[3] => OUT_CIN.IN1
|
||||
A[3] => _.DATAD
|
||||
B[0] => operand[0].IN1
|
||||
B[1] => operand[1].IN1
|
||||
B[2] => operand[2].IN1
|
||||
B[3] => operand[3].IN1
|
||||
B[0] => operand[0].DATAB
|
||||
B[0] => operand[0].DATAA
|
||||
B[1] => operand[1].DATAB
|
||||
B[1] => operand[1].DATAA
|
||||
B[2] => operand[2].DATAB
|
||||
B[2] => operand[2].DATAA
|
||||
B[3] => operand[3].DATAB
|
||||
B[3] => operand[3].DATAA
|
||||
OUT_1[0] <= _.SUM_OUT
|
||||
OUT_1[1] <= _.SUM_OUT
|
||||
OUT_1[2] <= _.SUM_OUT
|
||||
|
||||
Binary file not shown.
@@ -18,13 +18,13 @@
|
||||
<TR >
|
||||
<TD >logic_unit</TD>
|
||||
<TD >10</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >4</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
|
||||
Binary file not shown.
@@ -3,6 +3,6 @@
|
||||
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; logic_unit ; 10 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; logic_unit ; 10 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; adder_unit ; 9 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,17 +1,13 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927733469 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927733470 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:13 2026 " "Processing started: Wed Sep 9 14:22:13 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927733470 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927733470 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927733470 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788927733775 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788927733775 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 3 3 " "Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "../../modules/asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "../../modules/lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} { "Info" "ISGN_ENTITY_NAME" "3 alu " "Found entity 3: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788927742589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927742589 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788927742728 ""}
|
||||
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "OUT_1 alu.sv(8) " "Output port \"OUT_1\" at alu.sv(8) has no driver" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1788927742729 "|alu"}
|
||||
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "flags alu.sv(8) " "Output port \"flags\" at alu.sv(8) has no driver" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1788927742729 "|alu"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927742734 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927742738 ""}
|
||||
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1788927743236 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[0\] GND " "Pin \"OUT_1\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[1\] GND " "Pin \"OUT_1\[1\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[2\] GND " "Pin \"OUT_1\[2\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "OUT_1\[3\] GND " "Pin \"OUT_1\[3\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|OUT_1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "flags\[0\] GND " "Pin \"flags\[0\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|flags[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "flags\[1\] GND " "Pin \"flags\[1\]\" is stuck at GND" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1788927743252 "|alu|flags[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1788927743252 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788927743358 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788927743358 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "12 " "Design contains 12 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[0\] " "No output dependent on input pin \"op\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[1\] " "No output dependent on input pin \"op\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[2\] " "No output dependent on input pin \"op\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "op\[3\] " "No output dependent on input pin \"op\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|op[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[0\] " "No output dependent on input pin \"A\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[1\] " "No output dependent on input pin \"A\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[2\] " "No output dependent on input pin \"A\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[3\] " "No output dependent on input pin \"A\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|A[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[0\] " "No output dependent on input pin \"B\[0\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[1\] " "No output dependent on input pin \"B\[1\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[2\] " "No output dependent on input pin \"B\[2\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "B\[3\] " "No output dependent on input pin \"B\[3\]\"" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1788927743394 "|alu|B[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1788927743394 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788927743395 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788927743395 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788927743395 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "425 " "Peak virtual memory: 425 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:22:23 2026 " "Processing ended: Wed Sep 9 14:22:23 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927743401 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788927743401 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430597214 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:03:17 2026 " "Processing started: Tue Sep 15 10:03:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430597215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu " "Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430597215 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789430597568 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv 3 3 " "Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 asu " "Found entity 1: asu" { } { { "asu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "2 lu " "Found entity 2: lu" { } { { "lu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} { "Info" "ISGN_ENTITY_NAME" "3 alu " "Found entity 3: alu" { } { { "../../modules/alu.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789430607470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430607470 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Elaborating entity \"alu\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789430607626 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asu asu:adder_unit " "Elaborating entity \"asu\" for hierarchy \"asu:adder_unit\"" { } { { "../../modules/alu.sv" "adder_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 16 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607634 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lu lu:logic_unit " "Elaborating entity \"lu\" for hierarchy \"lu:logic_unit\"" { } { { "../../modules/alu.sv" "logic_unit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430607639 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789430608371 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789430608734 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789430608734 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789430608768 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789430608768 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789430608768 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:03:28 2026 " "Processing ended: Tue Sep 15 10:03:28 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430608774 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789430608774 ""}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,61 +1,61 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788927780035 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788927780035 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 9 14:22:59 2026 " "Processing started: Wed Sep 9 14:22:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788927780035 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927780035 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927780036 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788927780089 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788927780570 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788927780570 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927780648 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927780648 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788927781220 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927781221 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927781221 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927781222 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788927781222 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927781222 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788927781223 ""}
|
||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788927781228 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927781228 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781230 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781233 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781234 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781235 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781236 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927781236 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927781239 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927781277 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927782133 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927782214 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927782214 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782215 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782216 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782218 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782219 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782221 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927782222 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788927782226 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788927782475 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788927782976 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927783014 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927783014 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783016 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783017 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783018 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783020 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783022 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788927783025 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788927783164 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788927783164 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788927783164 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788927783165 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783166 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783167 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783167 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783168 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788927783169 ""}
|
||||
{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927784565 ""}
|
||||
{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788927784565 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "760 " "Peak virtual memory: 760 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 9 14:23:04 2026 " "Processing ended: Wed Sep 9 14:23:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788927784588 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788927784588 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789430648073 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 10:04:07 2026 " "Processing started: Tue Sep 15 10:04:07 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789430648073 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta A1_Q4 -c alu " "Command: quartus_sta A1_Q4 -c alu" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430648073 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789430648128 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789430648621 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789430648622 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430648694 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "alu.sdc " "Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789430649270 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430649271 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430649271 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430649272 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789430649273 ""}
|
||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789430649277 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430649278 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649279 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649282 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649283 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649284 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430649285 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430649287 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430649326 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430650655 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430650741 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430650742 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650743 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650745 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650746 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650747 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430650748 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789430650750 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789430651010 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789430651713 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651764 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651765 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651766 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651767 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651768 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651769 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789430651771 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789430651921 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789430651921 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789430651922 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651923 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651924 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651925 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789430651926 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789430653319 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "793 " "Peak virtual memory: 793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 10:04:13 2026 " "Processing ended: Tue Sep 15 10:04:13 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789430653351 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789430653351 ""}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,4 +1,7 @@
|
||||
start_full_compilation:s
|
||||
start_assembler:s-start_full_compilation
|
||||
start_timing_analyzer:s-start_full_compilation
|
||||
start_eda_netlist_writer:s-start_full_compilation
|
||||
start_full_compilation:s:00:01:00
|
||||
start_analysis_synthesis:s:00:00:13-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:31-start_full_compilation
|
||||
start_assembler:s:00:00:07-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:07-start_full_compilation
|
||||
start_eda_netlist_writer:s:00:00:02-start_full_compilation
|
||||
Binary file not shown.
@@ -2,7 +2,80 @@
|
||||
"partitions" : [
|
||||
{
|
||||
"name" : "Top",
|
||||
"pins" : []
|
||||
"pins" : [
|
||||
{
|
||||
"name" : "OUT_1[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "OUT_1[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "OUT_1[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "OUT_1[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "flags[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "flags[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "op[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "op[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "B[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "A[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "op[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "op[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "B[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "A[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "B[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "A[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "B[2]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "A[2]",
|
||||
"strict" : false
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,19 @@
|
||||
`ifndef LU_H_SV
|
||||
`define LU_H_SV
|
||||
module lu #(parameter width = 2) (
|
||||
input logic [1:0] op,
|
||||
input logic [2**width-1:0] A,
|
||||
input logic [2**width-1:0] B,
|
||||
output logic [2**width-1:0] Y);
|
||||
|
||||
always_comb begin
|
||||
case (op)
|
||||
2'b00: Y = A & B;
|
||||
2'b01: Y = A | B;
|
||||
2'b10: Y = A ^ B;
|
||||
2'b11: Y = ~(A | B);
|
||||
default:Y = '0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
`endif
|
||||
@@ -1,5 +1,5 @@
|
||||
Assembler report for alu
|
||||
Wed Sep 9 14:22:58 2026
|
||||
Tue Sep 15 10:04:06 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -38,7 +38,7 @@ on the Quartus Prime software download page.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Wed Sep 9 14:22:58 2026 ;
|
||||
; Assembler Status ; Successful - Tue Sep 15 10:04:06 2026 ;
|
||||
; Revision Name ; alu ;
|
||||
; Top-level Entity Name ; alu ;
|
||||
; Family ; Cyclone V ;
|
||||
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
|
||||
+----------------+------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+------------------+
|
||||
; JTAG usercode ; 0x0077DC97 ;
|
||||
; Checksum ; 0x0077DC97 ;
|
||||
; JTAG usercode ; 0x0078346C ;
|
||||
; Checksum ; 0x0078346C ;
|
||||
+----------------+------------------+
|
||||
|
||||
|
||||
@@ -78,13 +78,13 @@ on the Quartus Prime software download page.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Sep 9 14:22:53 2026
|
||||
Info: Processing started: Tue Sep 15 10:04:01 2026
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off A1_Q4 -c alu
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 516 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:22:58 2026
|
||||
Info: Peak virtual memory: 525 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:04:06 2026
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
Wed Sep 9 14:23:07 2026
|
||||
Tue Sep 15 10:04:16 2026
|
||||
@@ -1,5 +1,5 @@
|
||||
EDA Netlist Writer report for alu
|
||||
Wed Sep 9 14:23:06 2026
|
||||
Tue Sep 15 10:04:15 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Wed Sep 9 14:23:06 2026 ;
|
||||
; EDA Netlist Writer Status ; Successful - Tue Sep 15 10:04:15 2026 ;
|
||||
; Revision Name ; alu ;
|
||||
; Top-level Entity Name ; alu ;
|
||||
; Family ; Cyclone V ;
|
||||
@@ -81,13 +81,13 @@ on the Quartus Prime software download page.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Sep 9 14:23:05 2026
|
||||
Info: Processing started: Tue Sep 15 10:04:14 2026
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off A1_Q4 -c alu
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file alu.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/simulation/questa/" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 670 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:23:06 2026
|
||||
Info: Peak virtual memory: 658 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:04:15 2026
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Fitter report for alu
|
||||
Wed Sep 9 14:22:51 2026
|
||||
Tue Sep 15 10:03:59 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -57,14 +57,14 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Fitter Status ; Successful - Wed Sep 9 14:22:51 2026 ;
|
||||
; Fitter Status ; Successful - Tue Sep 15 10:03:59 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; alu ;
|
||||
; Top-level Entity Name ; alu ;
|
||||
; Family ; Cyclone V ;
|
||||
; Device ; 5CGXFC5C6F27C7 ;
|
||||
; Timing Models ; Final ;
|
||||
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
|
||||
; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 18 / 364 ( 5 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
@@ -152,7 +152,7 @@ on the Quartus Prime software download page.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
; Processor 2 ; 0.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@@ -162,8 +162,8 @@ on the Quartus Prime software download page.
|
||||
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
||||
+---------------------+-------------------+----------------------------+--------------------------+
|
||||
; Placement (by node) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ; 0.00 % ( 0 / 37 ) ;
|
||||
; -- Requested ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ;
|
||||
; -- Achieved ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ; 0.00 % ( 0 / 51 ) ;
|
||||
; ; ; ; ;
|
||||
; Routing (by net) ; ; ; ;
|
||||
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||
@@ -186,7 +186,7 @@ on the Quartus Prime software download page.
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
; Top ; 0.00 % ( 0 / 37 ) ; N/A ; Source File ; N/A ; ;
|
||||
; Top ; 0.00 % ( 0 / 51 ) ; N/A ; Source File ; N/A ; ;
|
||||
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
|
||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||
|
||||
@@ -202,11 +202,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
+-------------------------------------------------------------+--------------------+-------+
|
||||
; Resource ; Usage ; % ;
|
||||
+-------------------------------------------------------------+--------------------+-------+
|
||||
; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29,080 ; < 1 % ;
|
||||
; ALMs needed [=A-B+C] ; 1 ; ;
|
||||
; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29,080 ; < 1 % ;
|
||||
; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29,080 ; < 1 % ;
|
||||
; ALMs needed [=A-B+C] ; 11 ; ;
|
||||
; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29,080 ; < 1 % ;
|
||||
; [a] ALMs used for LUT logic and registers ; 0 ; ;
|
||||
; [b] ALMs used for LUT logic ; 1 ; ;
|
||||
; [b] ALMs used for LUT logic ; 11 ; ;
|
||||
; [c] ALMs used for registers ; 0 ; ;
|
||||
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
||||
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ;
|
||||
@@ -218,16 +218,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; ; ; ;
|
||||
; Difficulty packing design ; Low ; ;
|
||||
; ; ; ;
|
||||
; Total LABs: partially or completely used ; 1 / 2,908 ; < 1 % ;
|
||||
; -- Logic LABs ; 1 ; ;
|
||||
; Total LABs: partially or completely used ; 3 / 2,908 ; < 1 % ;
|
||||
; -- Logic LABs ; 3 ; ;
|
||||
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
||||
; ; ; ;
|
||||
; Combinational ALUT usage for logic ; 1 ; ;
|
||||
; -- 7 input functions ; 0 ; ;
|
||||
; -- 6 input functions ; 0 ; ;
|
||||
; Combinational ALUT usage for logic ; 15 ; ;
|
||||
; -- 7 input functions ; 3 ; ;
|
||||
; -- 6 input functions ; 3 ; ;
|
||||
; -- 5 input functions ; 0 ; ;
|
||||
; -- 4 input functions ; 0 ; ;
|
||||
; -- <=3 input functions ; 1 ; ;
|
||||
; -- 4 input functions ; 1 ; ;
|
||||
; -- <=3 input functions ; 8 ; ;
|
||||
; Combinational ALUT usage for route-throughs ; 0 ; ;
|
||||
; ; ; ;
|
||||
; Dedicated logic registers ; 0 ; ;
|
||||
@@ -240,7 +240,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; ;
|
||||
; I/O pins ; 18 / 364 ; 5 % ;
|
||||
; -- Clock pins ; 1 / 14 ; 7 % ;
|
||||
; -- Clock pins ; 0 / 14 ; 0 % ;
|
||||
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
|
||||
; ; ; ;
|
||||
; M10K blocks ; 0 / 446 ; 0 % ;
|
||||
@@ -271,98 +271,98 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
||||
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
||||
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
|
||||
; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
|
||||
; Maximum fan-out ; 1 ; ;
|
||||
; Highest non-global fan-out ; 1 ; ;
|
||||
; Total fan-out ; 18 ; ;
|
||||
; Average fan-out ; 0.49 ; ;
|
||||
; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.2% ; ;
|
||||
; Maximum fan-out ; 7 ; ;
|
||||
; Highest non-global fan-out ; 7 ; ;
|
||||
; Total fan-out ; 84 ; ;
|
||||
; Average fan-out ; 1.65 ; ;
|
||||
+-------------------------------------------------------------+--------------------+-------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Partition Statistics ;
|
||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||
; Statistic ; Top ; hard_block:auto_generated_inst ;
|
||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||
; Logic utilization (ALMs needed / total ALMs on device) ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; ALMs needed [=A-B+C] ; 1 ; 0 ;
|
||||
; [A] ALMs used in final placement [=a+b+c+d] ; 1 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
|
||||
; [b] ALMs used for LUT logic ; 1 ; 0 ;
|
||||
; [c] ALMs used for registers ; 0 ; 0 ;
|
||||
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
|
||||
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [a] Due to location constrained logic ; 0 ; 0 ;
|
||||
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
|
||||
; [c] Due to LAB input limits ; 0 ; 0 ;
|
||||
; [d] Due to virtual I/Os ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Difficulty packing design ; Low ; Low ;
|
||||
; ; ; ;
|
||||
; Total LABs: partially or completely used ; 1 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
|
||||
; -- Logic LABs ; 1 ; 0 ;
|
||||
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Combinational ALUT usage for logic ; 1 ; 0 ;
|
||||
; -- 7 input functions ; 0 ; 0 ;
|
||||
; -- 6 input functions ; 0 ; 0 ;
|
||||
; -- 5 input functions ; 0 ; 0 ;
|
||||
; -- 4 input functions ; 0 ; 0 ;
|
||||
; -- <=3 input functions ; 1 ; 0 ;
|
||||
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
|
||||
; Memory ALUT usage ; 0 ; 0 ;
|
||||
; -- 64-address deep ; 0 ; 0 ;
|
||||
; -- 32-address deep ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Dedicated logic registers ; 0 ; 0 ;
|
||||
; -- By type: ; ; ;
|
||||
; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ;
|
||||
; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ;
|
||||
; -- By function: ; ; ;
|
||||
; -- Design implementation registers ; 0 ; 0 ;
|
||||
; -- Routing optimization registers ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; 0 ;
|
||||
; I/O pins ; 18 ; 0 ;
|
||||
; I/O registers ; 0 ; 0 ;
|
||||
; Total block memory bits ; 0 ; 0 ;
|
||||
; Total block memory implementation bits ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Connections ; ; ;
|
||||
; -- Input Connections ; 0 ; 0 ;
|
||||
; -- Registered Input Connections ; 0 ; 0 ;
|
||||
; -- Output Connections ; 0 ; 0 ;
|
||||
; -- Registered Output Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Internal Connections ; ; ;
|
||||
; -- Total Connections ; 18 ; 0 ;
|
||||
; -- Registered Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; External Connections ; ; ;
|
||||
; -- Top ; 0 ; 0 ;
|
||||
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Partition Interface ; ; ;
|
||||
; -- Input Ports ; 12 ; 0 ;
|
||||
; -- Output Ports ; 6 ; 0 ;
|
||||
; -- Bidir Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Registered Ports ; ; ;
|
||||
; -- Registered Input Ports ; 0 ; 0 ;
|
||||
; -- Registered Output Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Port Connectivity ; ; ;
|
||||
; -- Input Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Output Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Input Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Output Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Input Ports with no Source ; 0 ; 0 ;
|
||||
; -- Output Ports with no Source ; 0 ; 0 ;
|
||||
; -- Input Ports with no Fanout ; 0 ; 0 ;
|
||||
; -- Output Ports with no Fanout ; 0 ; 0 ;
|
||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Partition Statistics ;
|
||||
+-------------------------------------------------------------+----------------------+--------------------------------+
|
||||
; Statistic ; Top ; hard_block:auto_generated_inst ;
|
||||
+-------------------------------------------------------------+----------------------+--------------------------------+
|
||||
; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; ALMs needed [=A-B+C] ; 11 ; 0 ;
|
||||
; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
|
||||
; [b] ALMs used for LUT logic ; 11 ; 0 ;
|
||||
; [c] ALMs used for registers ; 0 ; 0 ;
|
||||
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
|
||||
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||
; [a] Due to location constrained logic ; 0 ; 0 ;
|
||||
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
|
||||
; [c] Due to LAB input limits ; 0 ; 0 ;
|
||||
; [d] Due to virtual I/Os ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Difficulty packing design ; Low ; Low ;
|
||||
; ; ; ;
|
||||
; Total LABs: partially or completely used ; 3 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
|
||||
; -- Logic LABs ; 3 ; 0 ;
|
||||
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Combinational ALUT usage for logic ; 15 ; 0 ;
|
||||
; -- 7 input functions ; 3 ; 0 ;
|
||||
; -- 6 input functions ; 3 ; 0 ;
|
||||
; -- 5 input functions ; 0 ; 0 ;
|
||||
; -- 4 input functions ; 1 ; 0 ;
|
||||
; -- <=3 input functions ; 8 ; 0 ;
|
||||
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
|
||||
; Memory ALUT usage ; 0 ; 0 ;
|
||||
; -- 64-address deep ; 0 ; 0 ;
|
||||
; -- 32-address deep ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Dedicated logic registers ; 0 ; 0 ;
|
||||
; -- By type: ; ; ;
|
||||
; -- Primary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ;
|
||||
; -- Secondary logic registers ; 0 / 58160 ( 0 % ) ; 0 / 58160 ( 0 % ) ;
|
||||
; -- By function: ; ; ;
|
||||
; -- Design implementation registers ; 0 ; 0 ;
|
||||
; -- Routing optimization registers ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; ; ; ;
|
||||
; Virtual pins ; 0 ; 0 ;
|
||||
; I/O pins ; 18 ; 0 ;
|
||||
; I/O registers ; 0 ; 0 ;
|
||||
; Total block memory bits ; 0 ; 0 ;
|
||||
; Total block memory implementation bits ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Connections ; ; ;
|
||||
; -- Input Connections ; 0 ; 0 ;
|
||||
; -- Registered Input Connections ; 0 ; 0 ;
|
||||
; -- Output Connections ; 0 ; 0 ;
|
||||
; -- Registered Output Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Internal Connections ; ; ;
|
||||
; -- Total Connections ; 88 ; 0 ;
|
||||
; -- Registered Connections ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; External Connections ; ; ;
|
||||
; -- Top ; 0 ; 0 ;
|
||||
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Partition Interface ; ; ;
|
||||
; -- Input Ports ; 12 ; 0 ;
|
||||
; -- Output Ports ; 6 ; 0 ;
|
||||
; -- Bidir Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Registered Ports ; ; ;
|
||||
; -- Registered Input Ports ; 0 ; 0 ;
|
||||
; -- Registered Output Ports ; 0 ; 0 ;
|
||||
; ; ; ;
|
||||
; Port Connectivity ; ; ;
|
||||
; -- Input Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Output Ports driven by GND ; 0 ; 0 ;
|
||||
; -- Input Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Output Ports driven by VCC ; 0 ; 0 ;
|
||||
; -- Input Ports with no Source ; 0 ; 0 ;
|
||||
; -- Output Ports with no Source ; 0 ; 0 ;
|
||||
; -- Input Ports with no Fanout ; 0 ; 0 ;
|
||||
; -- Output Ports with no Fanout ; 0 ; 0 ;
|
||||
+-------------------------------------------------------------+----------------------+--------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -370,18 +370,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
||||
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
; A[0] ; U22 ; 5A ; 68 ; 12 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[1] ; AF21 ; 4A ; 51 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[2] ; AB17 ; 4A ; 51 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[3] ; AA18 ; 4A ; 62 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[0] ; C19 ; 7A ; 59 ; 61 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[1] ; T13 ; 3B ; 15 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[2] ; B20 ; 7A ; 62 ; 61 ; 91 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[3] ; E26 ; 6A ; 68 ; 37 ; 54 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[0] ; H9 ; 8A ; 19 ; 61 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[1] ; B24 ; 7A ; 65 ; 61 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[2] ; K24 ; 6A ; 68 ; 41 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[3] ; V25 ; 5B ; 68 ; 19 ; 54 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[0] ; P8 ; 3A ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[1] ; Y11 ; 3B ; 10 ; 0 ; 57 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[2] ; R9 ; 3A ; 6 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; A[3] ; Y8 ; 3A ; 6 ; 0 ; 34 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[1] ; AB6 ; 3A ; 4 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[2] ; R8 ; 3A ; 7 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; B[3] ; R10 ; 3A ; 6 ; 0 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[0] ; AD6 ; 3A ; 7 ; 0 ; 51 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[1] ; U7 ; 3A ; 2 ; 0 ; 91 ; 6 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[2] ; AD7 ; 3A ; 7 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
; op[3] ; U9 ; 3B ; 10 ; 0 ; 91 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
|
||||
+-------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||
|
||||
|
||||
@@ -390,31 +390,31 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
||||
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
; OUT_1[0] ; A5 ; 8A ; 21 ; 61 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[1] ; AA7 ; 3A ; 6 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[2] ; AF16 ; 4A ; 59 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[3] ; E11 ; 7A ; 40 ; 61 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; flags[0] ; F12 ; 7A ; 36 ; 61 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; flags[1] ; W25 ; 5B ; 68 ; 26 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[0] ; AA6 ; 3A ; 4 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[1] ; Y9 ; 3A ; 4 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[2] ; T9 ; 3B ; 10 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; OUT_1[3] ; W8 ; 3A ; 4 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; flags[0] ; AB10 ; 3B ; 12 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
; flags[1] ; AA7 ; 3A ; 6 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------+
|
||||
; I/O Bank Usage ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; 3A ; 1 / 16 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 3B ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 4A ; 4 / 80 ( 5 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5A ; 1 / 16 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5B ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 6A ; 2 / 48 ( 4 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 7A ; 5 / 80 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 8A ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
+----------+----------------+---------------+--------------+---------------+
|
||||
+----------------------------------------------------------------------------+
|
||||
; I/O Bank Usage ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||
; 3A ; 13 / 16 ( 81 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 3B ; 5 / 32 ( 16 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 4A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||
+----------+------------------+---------------+--------------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -425,7 +425,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; A2 ; 396 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
|
||||
; A3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
||||
; A4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
||||
; A5 ; 344 ; 8A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; A5 ; 344 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A6 ; 392 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
|
||||
; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -451,8 +451,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AA3 ; 14 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; AA4 ; 15 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; AA5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AA6 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA7 ; 47 ; 3A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AA6 ; 45 ; 3A ; OUT_1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AA7 ; 47 ; 3A ; flags[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -463,7 +463,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA18 ; 151 ; 4A ; A[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -477,18 +477,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; AB6 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB6 ; 43 ; 3A ; B[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB10 ; 61 ; 3B ; flags[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB17 ; 129 ; 4A ; A[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -529,8 +529,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AD5 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD6 ; 51 ; 3A ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AD7 ; 53 ; 3A ; op[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -590,12 +590,12 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; AF16 ; 143 ; 4A ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF19 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; AF21 ; 128 ; 4A ; A[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -619,11 +619,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; B17 ; 298 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; B19 ; 282 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B20 ; 278 ; 7A ; B[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; B24 ; 267 ; 7A ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -644,7 +644,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C19 ; 284 ; 7A ; B[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C20 ; 280 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; C22 ; 266 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -688,7 +688,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; E8 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; E11 ; 326 ; 7A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -703,7 +703,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; E23 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; E24 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; E25 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; E26 ; 229 ; 6A ; B[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; E26 ; 229 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; F1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; F2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||
; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -715,7 +715,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; F11 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; F12 ; 333 ; 7A ; flags[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
||||
; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -764,7 +764,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; H7 ; 368 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H9 ; 349 ; 8A ; op[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -831,7 +831,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; K21 ; 248 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; K23 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K24 ; 234 ; 6A ; op[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; K24 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K25 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; K26 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -919,7 +919,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; P6 ; 0 ; B1L ; GND ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; P8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; P8 ; 52 ; 3A ; A[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; P10 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; P11 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -945,9 +945,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; R5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; R6 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; R7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; R8 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; R9 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; R10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; R8 ; 50 ; 3A ; B[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; R9 ; 48 ; 3A ; A[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; R10 ; 46 ; 3A ; B[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; R11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; R12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; R13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
@@ -972,11 +972,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; T6 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; T7 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T9 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T9 ; 56 ; 3B ; OUT_1[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; T11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T12 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T13 ; 68 ; 3B ; B[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; T13 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; T14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; T16 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
@@ -996,9 +996,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U7 ; 39 ; 3A ; op[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U9 ; 54 ; 3B ; op[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; U12 ; 100 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -1011,7 +1011,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; U22 ; 177 ; 5A ; A[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; U22 ; 177 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; U24 ; 195 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; U25 ; 211 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
@@ -1040,7 +1040,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V23 ; 183 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V24 ; 185 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V25 ; 197 ; 5B ; op[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; V25 ; 197 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -1049,10 +1049,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; W5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W6 ; 27 ; B0L ; GND ; ; ; ; Row I/O ; ; -- ; -- ;
|
||||
; W7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W8 ; 42 ; 3A ; OUT_1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W11 ; 57 ; 3B ; B[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
@@ -1066,7 +1066,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; W22 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||
; W23 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||
; W24 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; W25 ; 207 ; 5B ; flags[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
|
||||
; W25 ; 207 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; W26 ; 209 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||
; Y1 ; 17 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ;
|
||||
; Y2 ; 16 ; B0L ; GND ; ; ; ; -- ; ; -- ; -- ;
|
||||
@@ -1075,10 +1075,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
||||
; Y5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; Y6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||
; Y7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||
; Y8 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y8 ; 49 ; 3A ; A[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; Y9 ; 44 ; 3A ; OUT_1[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; Y10 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y11 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y11 ; 55 ; 3B ; A[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
|
||||
; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; Y13 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||
@@ -1103,42 +1103,42 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
||||
+----------+-------------------------------+
|
||||
; Pin Name ; Reason ;
|
||||
+----------+-------------------------------+
|
||||
; op[0] ; Incomplete set of assignments ;
|
||||
; op[1] ; Incomplete set of assignments ;
|
||||
; op[2] ; Incomplete set of assignments ;
|
||||
; op[3] ; Incomplete set of assignments ;
|
||||
; A[0] ; Incomplete set of assignments ;
|
||||
; A[1] ; Incomplete set of assignments ;
|
||||
; A[2] ; Incomplete set of assignments ;
|
||||
; A[3] ; Incomplete set of assignments ;
|
||||
; B[0] ; Incomplete set of assignments ;
|
||||
; B[1] ; Incomplete set of assignments ;
|
||||
; B[2] ; Incomplete set of assignments ;
|
||||
; B[3] ; Incomplete set of assignments ;
|
||||
; OUT_1[0] ; Incomplete set of assignments ;
|
||||
; OUT_1[1] ; Incomplete set of assignments ;
|
||||
; OUT_1[2] ; Incomplete set of assignments ;
|
||||
; OUT_1[3] ; Incomplete set of assignments ;
|
||||
; flags[0] ; Incomplete set of assignments ;
|
||||
; flags[1] ; Incomplete set of assignments ;
|
||||
; op[0] ; Missing location assignment ;
|
||||
; op[1] ; Missing location assignment ;
|
||||
; op[2] ; Missing location assignment ;
|
||||
; op[3] ; Missing location assignment ;
|
||||
; A[0] ; Missing location assignment ;
|
||||
; A[1] ; Missing location assignment ;
|
||||
; A[2] ; Missing location assignment ;
|
||||
; A[3] ; Missing location assignment ;
|
||||
; B[0] ; Missing location assignment ;
|
||||
; B[1] ; Missing location assignment ;
|
||||
; B[2] ; Missing location assignment ;
|
||||
; B[3] ; Missing location assignment ;
|
||||
; op[2] ; Incomplete set of assignments ;
|
||||
; op[3] ; Incomplete set of assignments ;
|
||||
; B[0] ; Incomplete set of assignments ;
|
||||
; A[0] ; Incomplete set of assignments ;
|
||||
; op[0] ; Incomplete set of assignments ;
|
||||
; op[1] ; Incomplete set of assignments ;
|
||||
; B[3] ; Incomplete set of assignments ;
|
||||
; A[3] ; Incomplete set of assignments ;
|
||||
; B[1] ; Incomplete set of assignments ;
|
||||
; A[1] ; Incomplete set of assignments ;
|
||||
; B[2] ; Incomplete set of assignments ;
|
||||
; A[2] ; Incomplete set of assignments ;
|
||||
; OUT_1[0] ; Missing location assignment ;
|
||||
; OUT_1[1] ; Missing location assignment ;
|
||||
; OUT_1[2] ; Missing location assignment ;
|
||||
; OUT_1[3] ; Missing location assignment ;
|
||||
; flags[0] ; Missing location assignment ;
|
||||
; flags[1] ; Missing location assignment ;
|
||||
; op[2] ; Missing location assignment ;
|
||||
; op[3] ; Missing location assignment ;
|
||||
; B[0] ; Missing location assignment ;
|
||||
; A[0] ; Missing location assignment ;
|
||||
; op[0] ; Missing location assignment ;
|
||||
; op[1] ; Missing location assignment ;
|
||||
; B[3] ; Missing location assignment ;
|
||||
; A[3] ; Missing location assignment ;
|
||||
; B[1] ; Missing location assignment ;
|
||||
; A[1] ; Missing location assignment ;
|
||||
; B[2] ; Missing location assignment ;
|
||||
; A[2] ; Missing location assignment ;
|
||||
+----------+-------------------------------+
|
||||
|
||||
|
||||
@@ -1147,7 +1147,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; |alu ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
|
||||
; |alu ; 10.5 (7.5) ; 10.5 (7.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 15 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
|
||||
; |asu:adder_unit| ; 3.0 (3.0) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ;
|
||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@@ -1157,71 +1158,117 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
; op[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; OUT_1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; OUT_1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; flags[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; flags[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||
; op[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; op[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; B[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
; A[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------+
|
||||
; Pad To Core Delay Chain Fanout ;
|
||||
+---------------------+-------------------+---------+
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+---------------------+-------------------+---------+
|
||||
; op[0] ; ; ;
|
||||
; op[1] ; ; ;
|
||||
; op[2] ; ; ;
|
||||
; op[3] ; ; ;
|
||||
; A[0] ; ; ;
|
||||
; A[1] ; ; ;
|
||||
; A[2] ; ; ;
|
||||
; A[3] ; ; ;
|
||||
; B[0] ; ; ;
|
||||
; B[1] ; ; ;
|
||||
; B[2] ; ; ;
|
||||
; B[3] ; ; ;
|
||||
+---------------------+-------------------+---------+
|
||||
+----------------------------------------------------------------+
|
||||
; Pad To Core Delay Chain Fanout ;
|
||||
+----------------------------------+-------------------+---------+
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+----------------------------------+-------------------+---------+
|
||||
; op[2] ; ; ;
|
||||
; - Mux0~0 ; 0 ; 0 ;
|
||||
; - Mux1~0 ; 0 ; 0 ;
|
||||
; - Mux2~0 ; 0 ; 0 ;
|
||||
; - Mux3~0 ; 0 ; 0 ;
|
||||
; - Mux3~1 ; 0 ; 0 ;
|
||||
; - Mux3~2 ; 0 ; 0 ;
|
||||
; - Mux3~3 ; 0 ; 0 ;
|
||||
; op[3] ; ; ;
|
||||
; - Mux0~0 ; 1 ; 0 ;
|
||||
; - Mux1~0 ; 1 ; 0 ;
|
||||
; - Mux2~0 ; 1 ; 0 ;
|
||||
; - Mux3~0 ; 1 ; 0 ;
|
||||
; - Mux3~1 ; 1 ; 0 ;
|
||||
; - Mux3~2 ; 1 ; 0 ;
|
||||
; - Mux3~3 ; 1 ; 0 ;
|
||||
; B[0] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[0] ; 1 ; 0 ;
|
||||
; - Mux3~1 ; 1 ; 0 ;
|
||||
; A[0] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[0] ; 0 ; 0 ;
|
||||
; - Mux3~1 ; 0 ; 0 ;
|
||||
; op[0] ; ; ;
|
||||
; - Mux0~0 ; 0 ; 0 ;
|
||||
; - Mux1~0 ; 0 ; 0 ;
|
||||
; - Mux2~0 ; 0 ; 0 ;
|
||||
; - Mux3~1 ; 0 ; 0 ;
|
||||
; - Mux3~2 ; 0 ; 0 ;
|
||||
; - Mux3~3 ; 0 ; 0 ;
|
||||
; op[1] ; ; ;
|
||||
; - Mux0~0 ; 1 ; 0 ;
|
||||
; - Mux1~0 ; 1 ; 0 ;
|
||||
; - Mux2~0 ; 1 ; 0 ;
|
||||
; - Mux3~1 ; 1 ; 0 ;
|
||||
; - Mux3~2 ; 1 ; 0 ;
|
||||
; - Mux3~3 ; 1 ; 0 ;
|
||||
; B[3] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ;
|
||||
; - Mux0~0 ; 1 ; 0 ;
|
||||
; - Mux3~3 ; 1 ; 0 ;
|
||||
; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ;
|
||||
; A[3] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[3] ; 1 ; 0 ;
|
||||
; - Mux3~3 ; 1 ; 0 ;
|
||||
; - asu:adder_unit|OUT_CIN[0] ; 1 ; 0 ;
|
||||
; - Mux0~0 ; 1 ; 0 ;
|
||||
; B[1] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[1] ; 0 ; 0 ;
|
||||
; - Mux2~0 ; 0 ; 0 ;
|
||||
; A[1] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[1] ; 1 ; 0 ;
|
||||
; - Mux2~0 ; 1 ; 0 ;
|
||||
; B[2] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[2] ; 0 ; 0 ;
|
||||
; - Mux1~0 ; 0 ; 0 ;
|
||||
; A[2] ; ; ;
|
||||
; - asu:adder_unit|OUT_1[2] ; 1 ; 0 ;
|
||||
; - Mux1~0 ; 1 ; 0 ;
|
||||
+----------------------------------+-------------------+---------+
|
||||
|
||||
|
||||
+----------------------------------------------------+
|
||||
; Routing Usage Summary ;
|
||||
+------------------------------+---------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+------------------------------+---------------------+
|
||||
; Block interconnects ; 0 / 217,884 ( 0 % ) ;
|
||||
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
|
||||
; C2 interconnects ; 0 / 87,208 ( 0 % ) ;
|
||||
; C4 interconnects ; 0 / 41,360 ( 0 % ) ;
|
||||
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; Direct links ; 0 / 217,884 ( 0 % ) ;
|
||||
; Global clocks ; 0 / 16 ( 0 % ) ;
|
||||
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
||||
; Local interconnects ; 0 / 58,160 ( 0 % ) ;
|
||||
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
||||
; R14 interconnects ; 0 / 9,228 ( 0 % ) ;
|
||||
; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ;
|
||||
; R3 interconnects ; 0 / 94,896 ( 0 % ) ;
|
||||
; R6 interconnects ; 0 / 194,640 ( 0 % ) ;
|
||||
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
||||
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
||||
+------------------------------+---------------------+
|
||||
+-------------------------------------------------------+
|
||||
; Routing Usage Summary ;
|
||||
+------------------------------+------------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+------------------------------+------------------------+
|
||||
; Block interconnects ; 25 / 217,884 ( < 1 % ) ;
|
||||
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
|
||||
; C2 interconnects ; 12 / 87,208 ( < 1 % ) ;
|
||||
; C4 interconnects ; 7 / 41,360 ( < 1 % ) ;
|
||||
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||
; Direct links ; 2 / 217,884 ( < 1 % ) ;
|
||||
; Global clocks ; 0 / 16 ( 0 % ) ;
|
||||
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
||||
; Local interconnects ; 6 / 58,160 ( < 1 % ) ;
|
||||
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
||||
; R14 interconnects ; 0 / 9,228 ( 0 % ) ;
|
||||
; R14/C12 interconnect drivers ; 0 / 15,096 ( 0 % ) ;
|
||||
; R3 interconnects ; 15 / 94,896 ( < 1 % ) ;
|
||||
; R6 interconnects ; 5 / 194,640 ( < 1 % ) ;
|
||||
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
||||
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
||||
+------------------------------+------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
@@ -1283,24 +1330,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; Total Inapplicable ; 18 ; 18 ; 18 ; 18 ; 18 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 18 ; 18 ; 18 ; 12 ; 18 ; 0 ; 0 ; 18 ;
|
||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; OUT_1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; flags[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; flags[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; op[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
; A[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||
|
||||
|
||||
@@ -1374,27 +1421,27 @@ Info (332154): The derive_clock_uncertainty command did not apply clock uncertai
|
||||
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (14951): The Fitter is using Advanced Physical Optimization.
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y24 to location X10_Y36
|
||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170200): Optimizations that may affect the design's timing were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.06 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 1342 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:22:51 2026
|
||||
Info: Elapsed time: 00:00:27
|
||||
Info: Total CPU time (on all processors): 00:00:39
|
||||
Info: Peak virtual memory: 1388 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:03:59 2026
|
||||
Info: Elapsed time: 00:00:30
|
||||
Info: Total CPU time (on all processors): 00:00:43
|
||||
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Wed Sep 9 14:22:51 2026
|
||||
Fitter Status : Successful - Tue Sep 15 10:03:59 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : alu
|
||||
Top-level Entity Name : alu
|
||||
Family : Cyclone V
|
||||
Device : 5CGXFC5C6F27C7
|
||||
Timing Models : Final
|
||||
Logic utilization (in ALMs) : 1 / 29,080 ( < 1 % )
|
||||
Logic utilization (in ALMs) : 11 / 29,080 ( < 1 % )
|
||||
Total registers : 0
|
||||
Total pins : 18 / 364 ( 5 % )
|
||||
Total virtual pins : 0
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Flow report for alu
|
||||
Wed Sep 9 14:23:06 2026
|
||||
Tue Sep 15 10:04:15 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -41,14 +41,14 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Flow Status ; Successful - Wed Sep 9 14:23:06 2026 ;
|
||||
; Flow Status ; Successful - Tue Sep 15 10:04:15 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; alu ;
|
||||
; Top-level Entity Name ; alu ;
|
||||
; Family ; Cyclone V ;
|
||||
; Device ; 5CGXFC5C6F27C7 ;
|
||||
; Timing Models ; Final ;
|
||||
; Logic utilization (in ALMs) ; 1 / 29,080 ( < 1 % ) ;
|
||||
; Logic utilization (in ALMs) ; 11 / 29,080 ( < 1 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 18 / 364 ( 5 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/09/2026 14:22:13 ;
|
||||
; Start date & time ; 09/15/2026 10:03:17 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; alu ;
|
||||
+-------------------+---------------------+
|
||||
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 268883478169649.178892773303605 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 253029099468756.178943059705529 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:23 ;
|
||||
; Fitter ; 00:00:27 ; 1.0 ; 1342 MB ; 00:00:38 ;
|
||||
; Assembler ; 00:00:05 ; 1.0 ; 516 MB ; 00:00:05 ;
|
||||
; Timing Analyzer ; 00:00:05 ; 1.0 ; 760 MB ; 00:00:05 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:48 ; -- ; -- ; 00:01:12 ;
|
||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ;
|
||||
; Fitter ; 00:00:30 ; 1.0 ; 1388 MB ; 00:00:43 ;
|
||||
; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ;
|
||||
; Timing Analyzer ; 00:00:06 ; 1.0 ; 793 MB ; 00:00:05 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:53 ; -- ; -- ; 00:01:21 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for alu
|
||||
Wed Sep 9 14:22:23 2026
|
||||
Tue Sep 15 10:03:28 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -14,14 +14,13 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. General Register Statistics
|
||||
9. Parameter Settings for User Entity Instance: Top-level Entity: |alu
|
||||
10. Parameter Settings for User Entity Instance: asu:adder_unit
|
||||
11. Parameter Settings for User Entity Instance: lu:logic_unit
|
||||
12. Port Connectivity Checks: "lu:logic_unit"
|
||||
13. Port Connectivity Checks: "asu:adder_unit"
|
||||
14. Post-Synthesis Netlist Statistics for Top Partition
|
||||
15. Elapsed Time Per Partition
|
||||
16. Analysis & Synthesis Messages
|
||||
9. Multiplexer Restructuring Statistics (Restructuring Performed)
|
||||
10. Parameter Settings for User Entity Instance: Top-level Entity: |alu
|
||||
11. Parameter Settings for User Entity Instance: asu:adder_unit
|
||||
12. Parameter Settings for User Entity Instance: lu:logic_unit
|
||||
13. Post-Synthesis Netlist Statistics for Top Partition
|
||||
14. Elapsed Time Per Partition
|
||||
15. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
@@ -48,7 +47,7 @@ on the Quartus Prime software download page.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+---------------------------------+-------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Wed Sep 9 14:22:23 2026 ;
|
||||
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:03:28 2026 ;
|
||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Revision Name ; alu ;
|
||||
; Top-level Entity Name ; alu ;
|
||||
@@ -171,42 +170,42 @@ on the Quartus Prime software download page.
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
|
||||
; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
|
||||
; ../../modules/asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv ; ;
|
||||
; ../../modules/lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv ; ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+---------+
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
|
||||
; ../../modules/alu.sv ; yes ; User SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv ; ;
|
||||
; asu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv ; ;
|
||||
; lu.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv ; ;
|
||||
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Estimate of Logic utilization (ALMs needed) ; 0 ;
|
||||
; ; ;
|
||||
; Combinational ALUT usage for logic ; 0 ;
|
||||
; -- 7 input functions ; 0 ;
|
||||
; -- 6 input functions ; 0 ;
|
||||
; -- 5 input functions ; 0 ;
|
||||
; -- 4 input functions ; 0 ;
|
||||
; -- <=3 input functions ; 0 ;
|
||||
; ; ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 18 ;
|
||||
; ; ;
|
||||
; Total DSP Blocks ; 0 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; op[0] ;
|
||||
; Maximum fan-out ; 1 ;
|
||||
; Total fan-out ; 18 ;
|
||||
; Average fan-out ; 0.50 ;
|
||||
+---------------------------------------------+-------+
|
||||
+-----------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+-------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------------+
|
||||
; Estimate of Logic utilization (ALMs needed) ; 10 ;
|
||||
; ; ;
|
||||
; Combinational ALUT usage for logic ; 14 ;
|
||||
; -- 7 input functions ; 3 ;
|
||||
; -- 6 input functions ; 3 ;
|
||||
; -- 5 input functions ; 0 ;
|
||||
; -- 4 input functions ; 1 ;
|
||||
; -- <=3 input functions ; 7 ;
|
||||
; ; ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 18 ;
|
||||
; ; ;
|
||||
; Total DSP Blocks ; 0 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; op[2]~input ;
|
||||
; Maximum fan-out ; 7 ;
|
||||
; Total fan-out ; 84 ;
|
||||
; Average fan-out ; 1.68 ;
|
||||
+---------------------------------------------+-------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@@ -214,7 +213,8 @@ on the Quartus Prime software download page.
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
; |alu ; 0 (0) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
|
||||
; |alu ; 14 (8) ; 0 (0) ; 0 ; 0 ; 18 ; 0 ; |alu ; alu ; work ;
|
||||
; |asu:adder_unit| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |alu|asu:adder_unit ; asu ; work ;
|
||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@@ -234,6 +234,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 7:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |alu|Mux2 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: Top-level Entity: |alu ;
|
||||
+----------------+-------+--------------------------------------------+
|
||||
@@ -264,39 +273,26 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "lu:logic_unit" ;
|
||||
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
|
||||
; Y ; Output ; Warning ; Output or bidir port (4 bits) is wider than the port expression (2 bits) it drives; bit(s) "Y[3..2]" have no fanouts ;
|
||||
; Y ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+------+--------+----------+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "asu:adder_unit" ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; OUT_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; COUT ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; OUT_CIN ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Post-Synthesis Netlist Statistics for Top Partition ;
|
||||
+-----------------------+-----------------------------+
|
||||
; Type ; Count ;
|
||||
+-----------------------+-----------------------------+
|
||||
; arriav_lcell_comb ; 1 ;
|
||||
; normal ; 1 ;
|
||||
; arriav_lcell_comb ; 14 ;
|
||||
; extend ; 3 ;
|
||||
; 7 data inputs ; 3 ;
|
||||
; normal ; 6 ;
|
||||
; 2 data inputs ; 1 ;
|
||||
; 3 data inputs ; 1 ;
|
||||
; 4 data inputs ; 1 ;
|
||||
; 6 data inputs ; 3 ;
|
||||
; shared ; 5 ;
|
||||
; 0 data inputs ; 1 ;
|
||||
; 2 data inputs ; 4 ;
|
||||
; boundary_port ; 18 ;
|
||||
; ; ;
|
||||
; Max LUT depth ; 0.00 ;
|
||||
; Average LUT depth ; 0.00 ;
|
||||
; Max LUT depth ; 2.40 ;
|
||||
; Average LUT depth ; 2.20 ;
|
||||
+-----------------------+-----------------------------+
|
||||
|
||||
|
||||
@@ -315,49 +311,28 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Sep 9 14:22:13 2026
|
||||
Info: Processing started: Tue Sep 15 10:03:17 2026
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q4 -c alu
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (12021): Found 3 design units, including 3 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv
|
||||
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1
|
||||
Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 1
|
||||
Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
|
||||
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/asu.sv Line: 4
|
||||
Info (12023): Found entity 2: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q4/lu.sv Line: 3
|
||||
Info (12023): Found entity 3: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
|
||||
Info (12127): Elaborating entity "alu" for the top level hierarchy
|
||||
Warning (10034): Output port "OUT_1" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (10034): Output port "flags" at alu.sv(8) has no driver File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 13
|
||||
Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16
|
||||
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "OUT_1[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (13410): Pin "OUT_1[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (13410): Pin "OUT_1[2]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (13410): Pin "OUT_1[3]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (13410): Pin "flags[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Warning (13410): Pin "flags[1]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 8
|
||||
Info (12128): Elaborating entity "asu" for hierarchy "asu:adder_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 16
|
||||
Info (12128): Elaborating entity "lu" for hierarchy "lu:logic_unit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 19
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 12 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "op[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
|
||||
Warning (15610): No output dependent on input pin "op[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
|
||||
Warning (15610): No output dependent on input pin "op[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
|
||||
Warning (15610): No output dependent on input pin "op[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 6
|
||||
Warning (15610): No output dependent on input pin "A[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "A[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "A[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "A[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "B[0]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "B[1]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "B[2]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Warning (15610): No output dependent on input pin "B[3]" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 7
|
||||
Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 32 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 12 input pins
|
||||
Info (21059): Implemented 6 output pins
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 24 warnings
|
||||
Info: Peak virtual memory: 425 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:22:23 2026
|
||||
Info: Elapsed time: 00:00:10
|
||||
Info: Total CPU time (on all processors): 00:00:24
|
||||
Info (21061): Implemented 14 logic cells
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 436 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:03:28 2026
|
||||
Info: Elapsed time: 00:00:11
|
||||
Info: Total CPU time (on all processors): 00:00:27
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
Analysis & Synthesis Status : Successful - Wed Sep 9 14:22:23 2026
|
||||
Analysis & Synthesis Status : Successful - Tue Sep 15 10:03:28 2026
|
||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Revision Name : alu
|
||||
Top-level Entity Name : alu
|
||||
|
||||
@@ -79,7 +79,7 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
|
||||
MSEL2 : A2 : : : : 9A :
|
||||
DNU : A3 : : : : :
|
||||
DNU : A4 : : : : :
|
||||
OUT_1[0] : A5 : output : 2.5 V : : 8A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
|
||||
CONF_DONE : A6 : : : : 9A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
|
||||
@@ -105,8 +105,8 @@ GND : AA2 : gnd : :
|
||||
GXB_NC : AA3 : : : : B0L :
|
||||
GXB_NC : AA4 : : : : B0L :
|
||||
GND : AA5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3A :
|
||||
OUT_1[1] : AA7 : output : 2.5 V : : 3A : N
|
||||
OUT_1[0] : AA6 : output : 2.5 V : : 3A : N
|
||||
flags[1] : AA7 : output : 2.5 V : : 3A : N
|
||||
VCC_AUX : AA8 : power : : 2.5V : :
|
||||
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||
VCCIO3B : AA10 : power : : 2.5V : 3B :
|
||||
@@ -117,7 +117,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : :
|
||||
GND : AA15 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
|
||||
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
|
||||
A[3] : AA18 : input : 2.5 V : : 4A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
|
||||
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
|
||||
VCCIO4A : AA20 : power : : 2.5V : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
|
||||
@@ -131,18 +131,18 @@ GND : AB2 : : :
|
||||
GND : AB3 : gnd : : : :
|
||||
GND : AB4 : gnd : : : :
|
||||
AS_DATA2, DATA2 : AB5 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3A :
|
||||
B[1] : AB6 : input : 2.5 V : : 3A : N
|
||||
NC : AB7 : : : : :
|
||||
GND : AB8 : gnd : : : :
|
||||
VCCPD3A : AB9 : power : : 2.5V : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
|
||||
flags[0] : AB10 : output : 2.5 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
|
||||
VCCIO4A : AB13 : power : : 2.5V : 4A :
|
||||
VCC_AUX : AB14 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
|
||||
A[2] : AB17 : input : 2.5 V : : 4A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
|
||||
GND : AB18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A :
|
||||
VCC_AUX : AB20 : power : : 2.5V : :
|
||||
@@ -183,8 +183,8 @@ GND : AD2 : : :
|
||||
GND : AD3 : gnd : : : :
|
||||
GND : AD4 : gnd : : : :
|
||||
AS_DATA1, DATA1 : AD5 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
|
||||
op[0] : AD6 : input : 2.5 V : : 3A : N
|
||||
op[2] : AD7 : input : 2.5 V : : 3A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
|
||||
VCCIO3B : AD9 : power : : 2.5V : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
|
||||
@@ -244,12 +244,12 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
|
||||
VCCIO4A : AF15 : power : : 2.5V : 4A :
|
||||
OUT_1[2] : AF16 : output : 2.5 V : : 4A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
|
||||
GND : AF20 : gnd : : : :
|
||||
A[1] : AF21 : input : 2.5 V : : 4A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
|
||||
@@ -273,11 +273,11 @@ VREFB7AN0 : B16 : power : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7A :
|
||||
GND : B18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A :
|
||||
B[2] : B20 : input : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
|
||||
VCCIO7A : B23 : power : : 2.5V : 7A :
|
||||
op[1] : B24 : input : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
|
||||
GND : C1 : gnd : : : :
|
||||
@@ -298,7 +298,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : :
|
||||
VCCIO7A : C16 : power : : 2.5V : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
|
||||
B[0] : C19 : input : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7A :
|
||||
GND : C21 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
|
||||
@@ -342,7 +342,7 @@ GND : E7 : gnd : :
|
||||
VCCBAT : E8 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A :
|
||||
OUT_1[3] : E11 : output : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A :
|
||||
VCCIO7A : E12 : power : : 2.5V : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
|
||||
VCC_AUX : E14 : power : : 2.5V : :
|
||||
@@ -357,7 +357,7 @@ VCCIO6A : E22 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A :
|
||||
B[3] : E26 : input : 2.5 V : : 6A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A :
|
||||
NC : F1 : : : : :
|
||||
NC : F2 : : : : :
|
||||
GND : F3 : gnd : : : :
|
||||
@@ -369,7 +369,7 @@ VCCPGM : F8 : power : : 1.8V/2.5
|
||||
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
|
||||
GND : F10 : gnd : : : :
|
||||
VCCPD7A8A : F11 : power : : 2.5V : 7A, 8A :
|
||||
flags[0] : F12 : output : 2.5 V : : 7A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
|
||||
VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A :
|
||||
DNU : F14 : : : : :
|
||||
VCCIO7A : F15 : power : : 2.5V : 7A :
|
||||
@@ -418,7 +418,7 @@ GND : H5 : : :
|
||||
GND : H6 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
|
||||
op[0] : H9 : input : 2.5 V : : 8A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
|
||||
VCCIO7A : H11 : power : : 2.5V : 7A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
|
||||
@@ -485,7 +485,7 @@ VCC : K20 : power : : 1.1V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
|
||||
GND : K22 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
|
||||
op[2] : K24 : input : 2.5 V : : 6A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K24 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
|
||||
GND : L1 : gnd : : : :
|
||||
@@ -573,7 +573,7 @@ VCCE_GXBL : P4 : power : : 1.1V
|
||||
GND : P5 : gnd : : : :
|
||||
GND : P6 : : : : B1L :
|
||||
GND : P7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3A :
|
||||
A[0] : P8 : input : 2.5 V : : 3A : N
|
||||
GND : P9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3B :
|
||||
@@ -599,9 +599,9 @@ GND : R4 : gnd : :
|
||||
VCCE_GXBL : R5 : power : : 1.1V : :
|
||||
TMS : R6 : input : : : 3A :
|
||||
GND : R7 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3A :
|
||||
B[2] : R8 : input : 2.5 V : : 3A : N
|
||||
A[2] : R9 : input : 2.5 V : : 3A : N
|
||||
B[3] : R10 : input : 2.5 V : : 3A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3B :
|
||||
GND : R12 : gnd : : : :
|
||||
VCC : R13 : power : : 1.1V : :
|
||||
@@ -626,11 +626,11 @@ GND : T5 : gnd : :
|
||||
TDI : T6 : input : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 3B :
|
||||
OUT_1[2] : T9 : output : 2.5 V : : 3B : N
|
||||
GND : T10 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
|
||||
B[1] : T13 : input : 2.5 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B :
|
||||
VCC : T14 : power : : 1.1V : :
|
||||
GND : T15 : gnd : : : :
|
||||
VCC : T16 : power : : 1.1V : :
|
||||
@@ -650,9 +650,9 @@ VCCL_GXBL : U3 : power : : 1.1V
|
||||
GND : U4 : gnd : : : :
|
||||
VCCE_GXBL : U5 : power : : 1.1V : :
|
||||
AS_DATA3, DATA3 : U6 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
|
||||
op[1] : U7 : input : 2.5 V : : 3A : N
|
||||
VCCIO3B : U8 : power : : 2.5V : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
|
||||
op[3] : U9 : input : 2.5 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U12 : : : : 4A :
|
||||
@@ -665,7 +665,7 @@ VCCIO4A : U18 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
|
||||
VCCPD5A : U21 : power : : 2.5V : 5A :
|
||||
A[0] : U22 : input : 2.5 V : : 5A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5A :
|
||||
GND : U23 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5B :
|
||||
@@ -694,7 +694,7 @@ VCCIO5A : V21 : power : : 2.5V
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5B :
|
||||
op[3] : V25 : input : 2.5 V : : 5B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
|
||||
GND : V26 : gnd : : : :
|
||||
GND : W1 : gnd : : : :
|
||||
GND : W2 : gnd : : : :
|
||||
@@ -703,10 +703,10 @@ GXB_NC : W4 : : :
|
||||
GND : W5 : gnd : : : :
|
||||
GND : W6 : : : : B0L :
|
||||
VCCA_FPLL : W7 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
|
||||
OUT_1[3] : W8 : output : 2.5 V : : 3A : N
|
||||
GND : W9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
|
||||
B[0] : W11 : input : 2.5 V : : 3B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
|
||||
VCCIO4A : W14 : power : : 2.5V : 4A :
|
||||
@@ -720,7 +720,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : :
|
||||
VCCPGM : W22 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||
VREFB5AN0 : W23 : power : : : 5A :
|
||||
VCCIO5B : W24 : power : : 2.5V : 5B :
|
||||
flags[1] : W25 : output : 2.5 V : : 5B : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5B :
|
||||
GND : Y1 : : : : B0L :
|
||||
GND : Y2 : : : : B0L :
|
||||
@@ -729,10 +729,10 @@ GND : Y4 : gnd : :
|
||||
TCK : Y5 : input : : : 3A :
|
||||
nCSO, DATA4 : Y6 : : : : 3A :
|
||||
VCCIO3A : Y7 : power : : 2.5V : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y9 : : : : 3A :
|
||||
A[3] : Y8 : input : 2.5 V : : 3A : N
|
||||
OUT_1[1] : Y9 : output : 2.5 V : : 3A : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3B :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3B :
|
||||
A[1] : Y11 : input : 2.5 V : : 3B : N
|
||||
GND : Y12 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
|
||||
|
||||
Binary file not shown.
@@ -1,5 +1,5 @@
|
||||
Timing Analyzer report for alu
|
||||
Wed Sep 9 14:23:04 2026
|
||||
Tue Sep 15 10:04:13 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
@@ -48,7 +48,11 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
40. Report TCCS
|
||||
41. Report RSKM
|
||||
42. Unconstrained Paths Summary
|
||||
43. Timing Analyzer Messages
|
||||
43. Unconstrained Input Ports
|
||||
44. Unconstrained Output Ports
|
||||
45. Unconstrained Input Ports
|
||||
46. Unconstrained Output Ports
|
||||
47. Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
@@ -94,12 +98,12 @@ on the Quartus Prime software download page.
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 2 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Average used ; 1.02 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
; Processor 2 ; 2.1% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@@ -300,18 +304,18 @@ No synchronizer chains to report.
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
|
||||
|
||||
@@ -321,11 +325,11 @@ No synchronizer chains to report.
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
@@ -335,11 +339,11 @@ No synchronizer chains to report.
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
@@ -349,11 +353,11 @@ No synchronizer chains to report.
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
@@ -363,11 +367,11 @@ No synchronizer chains to report.
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
@@ -396,20 +400,88 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 0 ; 0 ;
|
||||
; Unconstrained Input Port Paths ; 0 ; 0 ;
|
||||
; Unconstrained Output Ports ; 0 ; 0 ;
|
||||
; Unconstrained Output Port Paths ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 12 ; 12 ;
|
||||
; Unconstrained Input Port Paths ; 58 ; 58 ;
|
||||
; Unconstrained Output Ports ; 6 ; 6 ;
|
||||
; Unconstrained Output Port Paths ; 58 ; 58 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Input Ports ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; Input Port ; Comment ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Output Ports ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; Output Port ; Comment ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Input Ports ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; Input Port ; Comment ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; A[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; A[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; B[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; op[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Output Ports ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; Output Port ; Comment ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; OUT_1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; OUT_1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; flags[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; flags[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------+
|
||||
; Timing Analyzer Messages ;
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Sep 9 14:22:59 2026
|
||||
Info: Processing started: Tue Sep 15 10:04:07 2026
|
||||
Info: Command: quartus_sta A1_Q4 -c alu
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
@@ -466,12 +538,12 @@ Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info (332101): Design is fully constrained for setup requirements
|
||||
Info (332101): Design is fully constrained for hold requirements
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 760 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:23:04 2026
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Peak virtual memory: 793 megabytes
|
||||
Info: Processing ended: Tue Sep 15 10:04:13 2026
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
|
||||
|
||||
// DATE "09/09/2026 14:23:06"
|
||||
// DATE "09/15/2026 10:04:15"
|
||||
|
||||
//
|
||||
// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
|
||||
@@ -39,27 +39,27 @@ input logic [3:0] op ;
|
||||
input logic [3:0] A ;
|
||||
input logic [3:0] B ;
|
||||
output logic [3:0] OUT_1 ;
|
||||
output logic flags [1:0];
|
||||
output logic [1:0] flags ;
|
||||
|
||||
// Design Ports Information
|
||||
// op[0] => Location: PIN_H9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[1] => Location: PIN_B24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[2] => Location: PIN_K24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[3] => Location: PIN_V25, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[0] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[1] => Location: PIN_AF21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[2] => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[3] => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[0] => Location: PIN_C19, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[1] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[2] => Location: PIN_B20, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[3] => Location: PIN_E26, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[2] => Location: PIN_AF16, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// flags[0] => Location: PIN_F12, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// flags[1] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[0] => Location: PIN_AA6, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[1] => Location: PIN_Y9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[2] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// OUT_1[3] => Location: PIN_W8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// flags[0] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// flags[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[2] => Location: PIN_AD7, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[3] => Location: PIN_U9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[0] => Location: PIN_W11, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[0] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[0] => Location: PIN_AD6, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// op[1] => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[3] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[3] => Location: PIN_Y8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[1] => Location: PIN_AB6, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[1] => Location: PIN_Y11, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// B[2] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// A[2] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
|
||||
|
||||
wire gnd;
|
||||
@@ -73,24 +73,43 @@ assign unknown = 1'bx;
|
||||
tri1 devclrn;
|
||||
tri1 devpor;
|
||||
tri1 devoe;
|
||||
wire \op[0]~input_o ;
|
||||
wire \op[1]~input_o ;
|
||||
wire \op[2]~input_o ;
|
||||
wire \op[3]~input_o ;
|
||||
wire \A[0]~input_o ;
|
||||
wire \A[1]~input_o ;
|
||||
wire \A[2]~input_o ;
|
||||
wire \A[3]~input_o ;
|
||||
wire \B[0]~input_o ;
|
||||
wire \B[1]~input_o ;
|
||||
wire \B[2]~input_o ;
|
||||
wire \B[3]~input_o ;
|
||||
wire \~QUARTUS_CREATED_GND~I_combout ;
|
||||
wire \op[0]~input_o ;
|
||||
wire \B[3]~input_o ;
|
||||
wire \A[3]~input_o ;
|
||||
wire \op[2]~input_o ;
|
||||
wire \op[1]~input_o ;
|
||||
wire \op[3]~input_o ;
|
||||
wire \Mux3~3_combout ;
|
||||
wire \A[0]~input_o ;
|
||||
wire \B[0]~input_o ;
|
||||
wire \Mux3~0_combout ;
|
||||
wire \B[2]~input_o ;
|
||||
wire \A[2]~input_o ;
|
||||
wire \A[1]~input_o ;
|
||||
wire \B[1]~input_o ;
|
||||
wire \adder_unit|_~1 ;
|
||||
wire \adder_unit|_~2 ;
|
||||
wire \adder_unit|_~7 ;
|
||||
wire \adder_unit|_~8 ;
|
||||
wire \adder_unit|_~10 ;
|
||||
wire \adder_unit|_~11 ;
|
||||
wire \adder_unit|_~13 ;
|
||||
wire \adder_unit|_~14 ;
|
||||
wire \Mux3~2_combout ;
|
||||
wire \Mux3~1_combout ;
|
||||
wire \Mux3~4_combout ;
|
||||
wire \Mux2~0_combout ;
|
||||
wire \Mux1~0_combout ;
|
||||
wire \Mux0~0_combout ;
|
||||
wire [0:0] \adder_unit|OUT_CIN ;
|
||||
wire [3:0] \adder_unit|OUT_1 ;
|
||||
wire [0:0] \adder_unit|COUT ;
|
||||
|
||||
|
||||
// Location: IOOBUF_X21_Y61_N36
|
||||
// Location: IOOBUF_X4_Y0_N36
|
||||
cyclonev_io_obuf \OUT_1[0]~output (
|
||||
.i(gnd),
|
||||
.i(\Mux3~4_combout ),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -104,9 +123,9 @@ defparam \OUT_1[0]~output .open_drain_output = "false";
|
||||
defparam \OUT_1[0]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X6_Y0_N53
|
||||
// Location: IOOBUF_X4_Y0_N2
|
||||
cyclonev_io_obuf \OUT_1[1]~output (
|
||||
.i(gnd),
|
||||
.i(\Mux2~0_combout ),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -120,9 +139,9 @@ defparam \OUT_1[1]~output .open_drain_output = "false";
|
||||
defparam \OUT_1[1]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X59_Y0_N19
|
||||
// Location: IOOBUF_X10_Y0_N76
|
||||
cyclonev_io_obuf \OUT_1[2]~output (
|
||||
.i(gnd),
|
||||
.i(\Mux1~0_combout ),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -136,9 +155,9 @@ defparam \OUT_1[2]~output .open_drain_output = "false";
|
||||
defparam \OUT_1[2]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X40_Y61_N93
|
||||
// Location: IOOBUF_X4_Y0_N19
|
||||
cyclonev_io_obuf \OUT_1[3]~output (
|
||||
.i(gnd),
|
||||
.i(\Mux0~0_combout ),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -152,9 +171,9 @@ defparam \OUT_1[3]~output .open_drain_output = "false";
|
||||
defparam \OUT_1[3]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X36_Y61_N19
|
||||
// Location: IOOBUF_X12_Y0_N36
|
||||
cyclonev_io_obuf \flags[0]~output (
|
||||
.i(gnd),
|
||||
.i(\adder_unit|COUT [0]),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -168,9 +187,9 @@ defparam \flags[0]~output .open_drain_output = "false";
|
||||
defparam \flags[0]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X68_Y26_N39
|
||||
// Location: IOOBUF_X6_Y0_N53
|
||||
cyclonev_io_obuf \flags[1]~output (
|
||||
.i(gnd),
|
||||
.i(\adder_unit|OUT_CIN [0]),
|
||||
.oe(vcc),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
@@ -184,7 +203,7 @@ defparam \flags[1]~output .open_drain_output = "false";
|
||||
defparam \flags[1]~output .shift_series_termination_control = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X19_Y61_N18
|
||||
// Location: IOIBUF_X7_Y0_N52
|
||||
cyclonev_io_ibuf \op[0]~input (
|
||||
.i(op[0]),
|
||||
.ibar(gnd),
|
||||
@@ -195,117 +214,7 @@ defparam \op[0]~input .bus_hold = "false";
|
||||
defparam \op[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X65_Y61_N1
|
||||
cyclonev_io_ibuf \op[1]~input (
|
||||
.i(op[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[1]~input .bus_hold = "false";
|
||||
defparam \op[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X68_Y41_N4
|
||||
cyclonev_io_ibuf \op[2]~input (
|
||||
.i(op[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[2]~input .bus_hold = "false";
|
||||
defparam \op[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X68_Y19_N55
|
||||
cyclonev_io_ibuf \op[3]~input (
|
||||
.i(op[3]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[3]~input .bus_hold = "false";
|
||||
defparam \op[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X68_Y12_N21
|
||||
cyclonev_io_ibuf \A[0]~input (
|
||||
.i(A[0]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[0]~input .bus_hold = "false";
|
||||
defparam \A[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X51_Y0_N35
|
||||
cyclonev_io_ibuf \A[1]~input (
|
||||
.i(A[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[1]~input .bus_hold = "false";
|
||||
defparam \A[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X51_Y0_N1
|
||||
cyclonev_io_ibuf \A[2]~input (
|
||||
.i(A[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[2]~input .bus_hold = "false";
|
||||
defparam \A[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X62_Y0_N58
|
||||
cyclonev_io_ibuf \A[3]~input (
|
||||
.i(A[3]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[3]~input .bus_hold = "false";
|
||||
defparam \A[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X59_Y61_N35
|
||||
cyclonev_io_ibuf \B[0]~input (
|
||||
.i(B[0]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[0]~input .bus_hold = "false";
|
||||
defparam \B[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X15_Y0_N1
|
||||
cyclonev_io_ibuf \B[1]~input (
|
||||
.i(B[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[1]~input .bus_hold = "false";
|
||||
defparam \B[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X62_Y61_N92
|
||||
cyclonev_io_ibuf \B[2]~input (
|
||||
.i(B[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[2]~input .bus_hold = "false";
|
||||
defparam \B[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X68_Y37_N55
|
||||
// Location: IOIBUF_X6_Y0_N18
|
||||
cyclonev_io_ibuf \B[3]~input (
|
||||
.i(B[3]),
|
||||
.ibar(gnd),
|
||||
@@ -316,7 +225,467 @@ defparam \B[3]~input .bus_hold = "false";
|
||||
defparam \B[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X46_Y55_N0
|
||||
// Location: IOIBUF_X6_Y0_N35
|
||||
cyclonev_io_ibuf \A[3]~input (
|
||||
.i(A[3]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[3]~input .bus_hold = "false";
|
||||
defparam \A[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X7_Y0_N35
|
||||
cyclonev_io_ibuf \op[2]~input (
|
||||
.i(op[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[2]~input .bus_hold = "false";
|
||||
defparam \op[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X2_Y0_N92
|
||||
cyclonev_io_ibuf \op[1]~input (
|
||||
.i(op[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[1]~input .bus_hold = "false";
|
||||
defparam \op[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X10_Y0_N92
|
||||
cyclonev_io_ibuf \op[3]~input (
|
||||
.i(op[3]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\op[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \op[3]~input .bus_hold = "false";
|
||||
defparam \op[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N18
|
||||
cyclonev_lcell_comb \Mux3~3 (
|
||||
// Equation(s):
|
||||
// \Mux3~3_combout = ( \op[1]~input_o & ( \op[3]~input_o & ( (!\op[0]~input_o & (!\op[2]~input_o & (!\B[3]~input_o $ (!\A[3]~input_o )))) ) ) )
|
||||
|
||||
.dataa(!\op[0]~input_o ),
|
||||
.datab(!\B[3]~input_o ),
|
||||
.datac(!\A[3]~input_o ),
|
||||
.datad(!\op[2]~input_o ),
|
||||
.datae(!\op[1]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux3~3_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux3~3 .extended_lut = "off";
|
||||
defparam \Mux3~3 .lut_mask = 64'h0000000000002800;
|
||||
defparam \Mux3~3 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X7_Y0_N1
|
||||
cyclonev_io_ibuf \A[0]~input (
|
||||
.i(A[0]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[0]~input .bus_hold = "false";
|
||||
defparam \A[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X10_Y0_N41
|
||||
cyclonev_io_ibuf \B[0]~input (
|
||||
.i(B[0]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[0]~input .bus_hold = "false";
|
||||
defparam \B[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N30
|
||||
cyclonev_lcell_comb \adder_unit|OUT_1[0] (
|
||||
// Equation(s):
|
||||
// \adder_unit|OUT_1 [0] = SUM(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
|
||||
// \adder_unit|_~1 = CARRY(( !\A[0]~input_o $ (!\B[0]~input_o ) ) + ( !VCC ) + ( !VCC ))
|
||||
// \adder_unit|_~2 = SHARE((\A[0]~input_o & \B[0]~input_o ))
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(!\A[0]~input_o ),
|
||||
.datac(!\B[0]~input_o ),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(),
|
||||
.sumout(\adder_unit|OUT_1 [0]),
|
||||
.cout(\adder_unit|_~1 ),
|
||||
.shareout(\adder_unit|_~2 ));
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|OUT_1[0] .extended_lut = "off";
|
||||
defparam \adder_unit|OUT_1[0] .lut_mask = 64'h0000030300003C3C;
|
||||
defparam \adder_unit|OUT_1[0] .shared_arith = "on";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N51
|
||||
cyclonev_lcell_comb \Mux3~0 (
|
||||
// Equation(s):
|
||||
// \Mux3~0_combout = (!\op[3]~input_o & !\op[2]~input_o )
|
||||
|
||||
.dataa(!\op[3]~input_o ),
|
||||
.datab(!\op[2]~input_o ),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux3~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux3~0 .extended_lut = "off";
|
||||
defparam \Mux3~0 .lut_mask = 64'h8888888888888888;
|
||||
defparam \Mux3~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X7_Y0_N18
|
||||
cyclonev_io_ibuf \B[2]~input (
|
||||
.i(B[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[2]~input .bus_hold = "false";
|
||||
defparam \B[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X6_Y0_N1
|
||||
cyclonev_io_ibuf \A[2]~input (
|
||||
.i(A[2]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[2]~input .bus_hold = "false";
|
||||
defparam \A[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X10_Y0_N58
|
||||
cyclonev_io_ibuf \A[1]~input (
|
||||
.i(A[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\A[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \A[1]~input .bus_hold = "false";
|
||||
defparam \A[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X4_Y0_N52
|
||||
cyclonev_io_ibuf \B[1]~input (
|
||||
.i(B[1]),
|
||||
.ibar(gnd),
|
||||
.dynamicterminationcontrol(gnd),
|
||||
.o(\B[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \B[1]~input .bus_hold = "false";
|
||||
defparam \B[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N33
|
||||
cyclonev_lcell_comb \adder_unit|OUT_1[1] (
|
||||
// Equation(s):
|
||||
// \adder_unit|OUT_1 [1] = SUM(( !\A[1]~input_o $ (!\B[1]~input_o ) ) + ( \adder_unit|_~2 ) + ( \adder_unit|_~1 ))
|
||||
// \adder_unit|_~7 = CARRY(( !\A[1]~input_o $ (!\B[1]~input_o ) ) + ( \adder_unit|_~2 ) + ( \adder_unit|_~1 ))
|
||||
// \adder_unit|_~8 = SHARE((\A[1]~input_o & \B[1]~input_o ))
|
||||
|
||||
.dataa(!\A[1]~input_o ),
|
||||
.datab(gnd),
|
||||
.datac(!\B[1]~input_o ),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(\adder_unit|_~1 ),
|
||||
.sharein(\adder_unit|_~2 ),
|
||||
.combout(),
|
||||
.sumout(\adder_unit|OUT_1 [1]),
|
||||
.cout(\adder_unit|_~7 ),
|
||||
.shareout(\adder_unit|_~8 ));
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|OUT_1[1] .extended_lut = "off";
|
||||
defparam \adder_unit|OUT_1[1] .lut_mask = 64'h0000050500005A5A;
|
||||
defparam \adder_unit|OUT_1[1] .shared_arith = "on";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N36
|
||||
cyclonev_lcell_comb \adder_unit|OUT_1[2] (
|
||||
// Equation(s):
|
||||
// \adder_unit|OUT_1 [2] = SUM(( !\B[2]~input_o $ (!\A[2]~input_o ) ) + ( \adder_unit|_~8 ) + ( \adder_unit|_~7 ))
|
||||
// \adder_unit|_~10 = CARRY(( !\B[2]~input_o $ (!\A[2]~input_o ) ) + ( \adder_unit|_~8 ) + ( \adder_unit|_~7 ))
|
||||
// \adder_unit|_~11 = SHARE((\B[2]~input_o & \A[2]~input_o ))
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(!\B[2]~input_o ),
|
||||
.datad(!\A[2]~input_o ),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(\adder_unit|_~7 ),
|
||||
.sharein(\adder_unit|_~8 ),
|
||||
.combout(),
|
||||
.sumout(\adder_unit|OUT_1 [2]),
|
||||
.cout(\adder_unit|_~10 ),
|
||||
.shareout(\adder_unit|_~11 ));
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|OUT_1[2] .extended_lut = "off";
|
||||
defparam \adder_unit|OUT_1[2] .lut_mask = 64'h0000000F00000FF0;
|
||||
defparam \adder_unit|OUT_1[2] .shared_arith = "on";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N39
|
||||
cyclonev_lcell_comb \adder_unit|OUT_1[3] (
|
||||
// Equation(s):
|
||||
// \adder_unit|OUT_1 [3] = SUM(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
|
||||
// \adder_unit|_~13 = CARRY(( !\A[3]~input_o $ (!\B[3]~input_o ) ) + ( \adder_unit|_~11 ) + ( \adder_unit|_~10 ))
|
||||
// \adder_unit|_~14 = SHARE((\A[3]~input_o & \B[3]~input_o ))
|
||||
|
||||
.dataa(!\A[3]~input_o ),
|
||||
.datab(gnd),
|
||||
.datac(!\B[3]~input_o ),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(\adder_unit|_~10 ),
|
||||
.sharein(\adder_unit|_~11 ),
|
||||
.combout(),
|
||||
.sumout(\adder_unit|OUT_1 [3]),
|
||||
.cout(\adder_unit|_~13 ),
|
||||
.shareout(\adder_unit|_~14 ));
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|OUT_1[3] .extended_lut = "off";
|
||||
defparam \adder_unit|OUT_1[3] .lut_mask = 64'h0000050500005A5A;
|
||||
defparam \adder_unit|OUT_1[3] .shared_arith = "on";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N42
|
||||
cyclonev_lcell_comb \adder_unit|COUT[0] (
|
||||
// Equation(s):
|
||||
// \adder_unit|COUT [0] = SUM(( GND ) + ( \adder_unit|_~14 ) + ( \adder_unit|_~13 ))
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(\adder_unit|_~13 ),
|
||||
.sharein(\adder_unit|_~14 ),
|
||||
.combout(),
|
||||
.sumout(\adder_unit|COUT [0]),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|COUT[0] .extended_lut = "off";
|
||||
defparam \adder_unit|COUT[0] .lut_mask = 64'h0000000000000000;
|
||||
defparam \adder_unit|COUT[0] .shared_arith = "on";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N48
|
||||
cyclonev_lcell_comb \Mux3~2 (
|
||||
// Equation(s):
|
||||
// \Mux3~2_combout = (\op[3]~input_o & (!\op[2]~input_o & (\op[0]~input_o & \op[1]~input_o )))
|
||||
|
||||
.dataa(!\op[3]~input_o ),
|
||||
.datab(!\op[2]~input_o ),
|
||||
.datac(!\op[0]~input_o ),
|
||||
.datad(!\op[1]~input_o ),
|
||||
.datae(gnd),
|
||||
.dataf(gnd),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux3~2_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux3~2 .extended_lut = "off";
|
||||
defparam \Mux3~2 .lut_mask = 64'h0004000400040004;
|
||||
defparam \Mux3~2 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N24
|
||||
cyclonev_lcell_comb \Mux3~1 (
|
||||
// Equation(s):
|
||||
// \Mux3~1_combout = ( \op[2]~input_o & ( !\op[3]~input_o & ( (!\B[0]~input_o & ((!\op[1]~input_o & (\op[0]~input_o & \A[0]~input_o )) # (\op[1]~input_o & (!\op[0]~input_o $ (!\A[0]~input_o ))))) # (\B[0]~input_o & (!\op[1]~input_o $
|
||||
// (((!\op[0]~input_o & !\A[0]~input_o ))))) ) ) )
|
||||
|
||||
.dataa(!\B[0]~input_o ),
|
||||
.datab(!\op[1]~input_o ),
|
||||
.datac(!\op[0]~input_o ),
|
||||
.datad(!\A[0]~input_o ),
|
||||
.datae(!\op[2]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux3~1_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux3~1 .extended_lut = "off";
|
||||
defparam \Mux3~1 .lut_mask = 64'h0000166C00000000;
|
||||
defparam \Mux3~1 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N54
|
||||
cyclonev_lcell_comb \Mux3~4 (
|
||||
// Equation(s):
|
||||
// \Mux3~4_combout = ( \Mux3~2_combout & ( \Mux3~1_combout ) ) # ( !\Mux3~2_combout & ( \Mux3~1_combout ) ) # ( \Mux3~2_combout & ( !\Mux3~1_combout & ( ((!\adder_unit|COUT [0]) # ((\adder_unit|OUT_1 [0] & \Mux3~0_combout ))) # (\Mux3~3_combout ) ) )
|
||||
// ) # ( !\Mux3~2_combout & ( !\Mux3~1_combout & ( ((\adder_unit|OUT_1 [0] & \Mux3~0_combout )) # (\Mux3~3_combout ) ) ) )
|
||||
|
||||
.dataa(!\Mux3~3_combout ),
|
||||
.datab(!\adder_unit|OUT_1 [0]),
|
||||
.datac(!\Mux3~0_combout ),
|
||||
.datad(!\adder_unit|COUT [0]),
|
||||
.datae(!\Mux3~2_combout ),
|
||||
.dataf(!\Mux3~1_combout ),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux3~4_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux3~4 .extended_lut = "off";
|
||||
defparam \Mux3~4 .lut_mask = 64'h5757FF57FFFFFFFF;
|
||||
defparam \Mux3~4 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N12
|
||||
cyclonev_lcell_comb \Mux2~0 (
|
||||
// Equation(s):
|
||||
// \Mux2~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [1] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[1]~input_o & \B[1]~input_o )) # (\op[1]~input_o & (!\A[1]~input_o
|
||||
// $ (!\B[1]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[1]~input_o & !\B[1]~input_o ))))))) ) )
|
||||
|
||||
.dataa(!\op[0]~input_o ),
|
||||
.datab(!\op[1]~input_o ),
|
||||
.datac(!\A[1]~input_o ),
|
||||
.datad(!\B[1]~input_o ),
|
||||
.datae(!\op[2]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(!\adder_unit|OUT_1 [1]),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux2~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux2~0 .extended_lut = "on";
|
||||
defparam \Mux2~0 .lut_mask = 64'h0F0F166C00000000;
|
||||
defparam \Mux2~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N6
|
||||
cyclonev_lcell_comb \Mux1~0 (
|
||||
// Equation(s):
|
||||
// \Mux1~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [2] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[2]~input_o & \B[2]~input_o )) # (\op[1]~input_o & (!\A[2]~input_o
|
||||
// $ (!\B[2]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[2]~input_o & !\B[2]~input_o ))))))) ) )
|
||||
|
||||
.dataa(!\op[0]~input_o ),
|
||||
.datab(!\op[1]~input_o ),
|
||||
.datac(!\A[2]~input_o ),
|
||||
.datad(!\B[2]~input_o ),
|
||||
.datae(!\op[2]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(!\adder_unit|OUT_1 [2]),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux1~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux1~0 .extended_lut = "on";
|
||||
defparam \Mux1~0 .lut_mask = 64'h0F0F166C00000000;
|
||||
defparam \Mux1~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LABCELL_X7_Y1_N0
|
||||
cyclonev_lcell_comb \Mux0~0 (
|
||||
// Equation(s):
|
||||
// \Mux0~0_combout = ( !\op[2]~input_o & ( (((\adder_unit|OUT_1 [3] & ((!\op[3]~input_o ))))) ) ) # ( \op[2]~input_o & ( (!\op[3]~input_o & ((!\op[0]~input_o & ((!\op[1]~input_o & (\A[3]~input_o & \B[3]~input_o )) # (\op[1]~input_o & (!\A[3]~input_o
|
||||
// $ (!\B[3]~input_o ))))) # (\op[0]~input_o & (!\op[1]~input_o $ (((!\A[3]~input_o & !\B[3]~input_o ))))))) ) )
|
||||
|
||||
.dataa(!\op[0]~input_o ),
|
||||
.datab(!\op[1]~input_o ),
|
||||
.datac(!\A[3]~input_o ),
|
||||
.datad(!\B[3]~input_o ),
|
||||
.datae(!\op[2]~input_o ),
|
||||
.dataf(!\op[3]~input_o ),
|
||||
.datag(!\adder_unit|OUT_1 [3]),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\Mux0~0_combout ),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \Mux0~0 .extended_lut = "on";
|
||||
defparam \Mux0~0 .lut_mask = 64'h0F0F166C00000000;
|
||||
defparam \Mux0~0 .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X6_Y1_N0
|
||||
cyclonev_lcell_comb \adder_unit|OUT_CIN[0] (
|
||||
// Equation(s):
|
||||
// \adder_unit|OUT_CIN [0] = ( \A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) ) # ( !\A[3]~input_o & ( \adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # ( \A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( !\B[3]~input_o ) ) ) # (
|
||||
// !\A[3]~input_o & ( !\adder_unit|OUT_1 [3] & ( \B[3]~input_o ) ) )
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(!\B[3]~input_o ),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.datae(!\A[3]~input_o ),
|
||||
.dataf(!\adder_unit|OUT_1 [3]),
|
||||
.datag(gnd),
|
||||
.cin(gnd),
|
||||
.sharein(gnd),
|
||||
.combout(\adder_unit|OUT_CIN [0]),
|
||||
.sumout(),
|
||||
.cout(),
|
||||
.shareout());
|
||||
// synopsys translate_off
|
||||
defparam \adder_unit|OUT_CIN[0] .extended_lut = "off";
|
||||
defparam \adder_unit|OUT_CIN[0] .lut_mask = 64'h3333CCCCCCCC3333;
|
||||
defparam \adder_unit|OUT_CIN[0] .shared_arith = "off";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: MLABCELL_X8_Y13_N0
|
||||
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
|
||||
// Equation(s):
|
||||
|
||||
|
||||
Reference in new issue
Block a user