Added all Testbenches to Modelsim and confirmed working operation

Quartus/A1_Q3/simulation/questa/asu.svo

@@ -17,7 +17,7 @@
 // PROGRAM "Quartus Prime"
 // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
 
-// DATE "09/10/2026 14:02:02"
+// DATE "09/15/2026 10:01:28"
 
 // 
 // Device: Altera 5CGXFC5C6F27C7 Package FBGA672
@@ -36,12 +36,12 @@ module asu (
 	OUT_1,
 	COUT,
 	OUT_CIN);
-input 	[0:0] op;
-input 	[3:0] A;
-input 	[3:0] B;
-output 	[3:0] OUT_1;
-output 	[0:0] COUT;
-output 	[0:0] OUT_CIN;
+input 	logic [0:0] op ;
+input 	logic [3:0] A ;
+input 	logic [3:0] B ;
+output 	logic [3:0] OUT_1 ;
+output 	logic [0:0] COUT ;
+output 	logic [0:0] OUT_CIN ;
 
 // Design Ports Information
 // OUT_1[0]	=>  Location: PIN_F7,	 I/O Standard: 2.5 V,	 Current Strength: Default