TroubleElectrical/FPGA_Uni
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Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
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Quartus/A1_Q3/output_files/asu.map.rpt
+8 -8
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for asu
Thu Sep 10 14:01:01 2026
Tue Sep 15 10:00:22 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -44,7 +44,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 10 14:01:01 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 10:00:22 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
@@ -271,12 +271,12 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Thu Sep 10 14:00:44 2026
Info: Processing started: Tue Sep 15 10:00:06 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A1_Q3 -c asu
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 1
Info (12023): Found entity 1: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4
Info (12127): Elaborating entity "asu" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
@@ -286,9 +286,9 @@ Info (21057): Implemented 21 device resources after synthesis - the final resour
Info (21059): Implemented 6 output pins
Info (21061): Implemented 6 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 436 megabytes
Info: Processing ended: Thu Sep 10 14:01:01 2026
Info: Elapsed time: 00:00:17
Info: Total CPU time (on all processors): 00:00:33
Info: Peak virtual memory: 439 megabytes
Info: Processing ended: Tue Sep 15 10:00:22 2026
Info: Elapsed time: 00:00:16
Info: Total CPU time (on all processors): 00:00:32