TroubleElectrical/FPGA_Uni
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Added all Testbenches to Modelsim and confirmed working operation

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TroubleElectrical committed 2026-09-15 15:15:00 +10:00
1 parent c4ebde7692
commit 05361dcf70
349 files changed
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Quartus/A1_Q3/output_files/asu.flow.rpt
+10 -10
View File
@@ -1,5 +1,5 @@
Flow report for asu
Thu Sep 10 14:02:02 2026
Tue Sep 15 10:01:28 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,7 +41,7 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Sep 10 14:02:02 2026 ;
; Flow Status ; Successful - Tue Sep 15 10:01:28 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; asu ;
; Top-level Entity Name ; asu ;
@@ -68,7 +68,7 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/10/2026 14:00:45 ;
; Start date & time ; 09/15/2026 10:00:07 ;
; Main task ; Compilation ;
; Revision Name ; asu ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ on the Quartus Prime software download page.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 7209694329158.178901284503666 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 253029099468756.178943040705122 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@@ -101,12 +101,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 419 MB ; 00:00:32 ;
; Fitter ; 00:00:36 ; 1.0 ; 1387 MB ; 00:00:50 ;
; Assembler ; 00:00:07 ; 1.0 ; 511 MB ; 00:00:07 ;
; Timing Analyzer ; 00:00:07 ; 1.0 ; 780 MB ; 00:00:07 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:01:08 ; -- ; -- ; 00:01:37 ;
; Analysis & Synthesis ; 00:00:16 ; 1.0 ; 422 MB ; 00:00:32 ;
; Fitter ; 00:00:40 ; 1.0 ; 1380 MB ; 00:00:51 ;
; Assembler ; 00:00:08 ; 1.0 ; 521 MB ; 00:00:08 ;
; Timing Analyzer ; 00:00:08 ; 1.0 ; 785 MB ; 00:00:08 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:01:14 ; -- ; -- ; 00:01:40 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+