Added all Testbenches to Modelsim and confirmed working operation
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@@ -1,3 +1,5 @@
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`ifndef LU_H_SV
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`define LU_H_SV
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module lu #(parameter width = 2) (
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input logic [1:0] op,
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input logic [2**width-1:0] A,
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@@ -10,7 +12,8 @@ module lu #(parameter width = 2) (
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2'b01: Y = A | B;
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2'b10: Y = A ^ B;
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2'b11: Y = ~(A | B);
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default: Y = '0;
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default:Y = '0;
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endcase
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end
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endmodule
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endmodule
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`endif
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