Added all Testbenches to Modelsim and confirmed working operation

This commit is contained in:
TroubleElectrical committed 2026-09-15 15:15:00 +10:00
1 parent c4ebde7692
commit 05361dcf70
349 files changed
+15719 -1096

No files matched your search

+5 -2
View File
@@ -1,3 +1,5 @@
`ifndef LU_H_SV
`define LU_H_SV
module lu #(parameter width = 2) (
input logic [1:0] op,
input logic [2**width-1:0] A,
@@ -10,7 +12,8 @@ module lu #(parameter width = 2) (
2'b01: Y = A | B;
2'b10: Y = A ^ B;
2'b11: Y = ~(A | B);
default: Y = '0;
default:Y = '0;
endcase
end
endmodule
endmodule
`endif