Added all Testbenches to Modelsim and confirmed working operation

ModelSim/asu.sv

@@ -1,3 +1,6 @@
+`ifndef ASU_H_SV
+`define ASU_H_SV
+
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
@@ -7,7 +10,8 @@ module asu #(parameter width = 2)(
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
-        operand = (B ^ {(2**width){op}});
+        //operand = (B ^ {(2**width){op}});
+        operand = op == 1'b0 ? B : ~B;
         {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
     end
 
@@ -15,3 +19,4 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 endmodule
+`endif