Added project to modelsim

This commit is contained in:
TroubleElectrical committed 2026-11-05 14:25:34 +11:00
1 parent 38fa35fccd
commit 00b2087860
22 files changed
+581 -297

No files matched your search

+177 -127
View File
@@ -11,32 +11,32 @@ cModel Technology
d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
valu
Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
Z1 !s110 1792115142
Z1 !s110 1793848891
!i10b 1
!s100 kh0:K2RRk@<XUA5?_0ad>1
!s100 KP25E<`D0[YGcmY_0OYR>3
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
Im?EZg:mSI^D?=D>QBY^1B0
I9jL53QmOM7UI;=OA3U@eg3
Z3 VDg1SIo80bB@j0V0VzS_@n1
S1
Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
Z5 w1792113810
Z5 w1792115823
8alu.sv
Falu.sv
!i122 179
L0 10 33
!i122 215
L0 10 35
Z6 OV;L;2020.1;71
r1
!s85 0
31
Z7 !s108 1792115141.000000
Z8 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
Z7 !s108 1793848891.000000
Z8 !s107 gatereg.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv|
Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv|
!i113 1
Z10 o-work work -sv
Z11 tCvgOpt 0
valu_tb
R0
Z12 !s110 1792115141
Z12 !s110 1793848695
!i10b 1
!s100 8=>8o`KV]hRM]V8AV?S[C1
R2
@@ -47,13 +47,13 @@ R4
Z13 w1789355084
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
!i122 168
!i122 190
L0 3 214
R6
r1
!s85 0
31
R7
Z14 !s108 1793848695.000000
!s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv|
!i113 1
@@ -61,19 +61,44 @@ R10
R11
vassignment2
R0
R1
R12
!i10b 1
!s100 9I6c?eD<Ld>]amhL__2Jz1
!s100 H2eJB`][V_?PYNI3VTRV10
R2
IFfHj7VAM^H^0]`kMd62bZ2
IXC<TonD>N5]eBIk8QocLJ3
R3
S1
R4
R5
w1792119882
8assignment2.sv
Fassignment2.sv
!i122 179
L0 15 91
!i122 201
L0 15 99
R6
r1
!s85 0
31
R14
Z15 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
Z16 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv|
!i113 1
R10
R11
vassignment3
R0
R1
!i10b 1
!s100 K6T8de>1WT94z3K=N1kLg0
R2
IMP2VlhaonMhKfg0_Nm3;Y0
R3
S1
R4
w1793848882
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
!i122 215
L0 14 81
R6
r1
!s85 0
@@ -97,7 +122,7 @@ R4
w1790228118
8asu.sv
Fasu.sv
!i122 179
!i122 215
L0 4 21
R6
r1
@@ -119,16 +144,16 @@ IcS>Hk9oO:RGFmfdUY9[i90
R3
S1
R4
Z14 w1789513270
Z17 w1789513270
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
!i122 171
!i122 193
L0 3 120
R6
r1
!s85 0
31
R7
R14
!s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv|
!i113 1
@@ -136,7 +161,7 @@ R10
R11
vByteIM
R0
R12
Z18 !s110 1793848955
!i10b 1
!s100 ]V5Di195@?V=P`Y?PM;U=0
R2
@@ -144,18 +169,18 @@ Ie:hP;^zFCE^LSAOVoDF6C3
R3
S1
R4
w1792112374
w1793848949
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
!i122 172
!i122 218
L0 3 12
R6
r1
!s85 0
31
R7
Z19 !s108 1793848955.000000
!s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
!i113 1
R10
R11
@@ -170,10 +195,10 @@ IN9L1dbI=^fl9KlmLIEFaZ0
R3
S1
R4
Z15 w1792112234
Z21 w1792112234
8control_unit.sv
Fcontrol_unit.sv
!i122 179
!i122 215
L0 5 31
R6
r1
@@ -185,6 +210,31 @@ R9
!i113 1
R10
R11
vgatereg
R0
R1
!i10b 1
!s100 7OH6NXT3_@J5T^khK_kBU1
R2
IfbEO5[]8TkZIHMTR<?J]83
R3
S1
R4
w1793848262
8gatereg.sv
Fgatereg.sv
!i122 215
L0 1 21
R6
r1
!s85 0
31
R7
R8
R9
!i113 1
R10
R11
vinstruction_classifier
R0
R1
@@ -195,10 +245,10 @@ I[MC9A^:kRAc`nk8<MdaKg2
R3
S1
R4
Z16 w1790228042
Z22 w1790228042
8instruction_classifier.sv
Finstruction_classifier.sv
!i122 179
!i122 215
L0 3 18
R6
r1
@@ -223,13 +273,13 @@ R4
R13
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
!i122 175
!i122 197
L0 2 51
R6
r1
!s85 0
31
R7
R14
!s107 instruction_classifier.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv|
!i113 1
@@ -245,10 +295,10 @@ In<Vi_TenOEn@V0998749H1
R3
S1
R4
R5
w1792113810
8instruction_counter.sv
Finstruction_counter.sv
!i122 179
!i122 215
L0 4 20
R6
r1
@@ -270,11 +320,11 @@ IObN^<8?MCaP;K@UKCVaP^1
R3
S1
R4
R16
R22
8lu.sv
Flu.sv
!i122 179
Z17 L0 3 16
!i122 215
Z23 L0 3 16
R6
r1
!s85 0
@@ -298,13 +348,13 @@ R4
w1788926090
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
!i122 178
!i122 200
L0 3 58
R6
r1
!s85 0
31
R7
R14
!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
!i113 1
@@ -312,19 +362,44 @@ R10
R11
vmips_tb
R0
R1
R12
!i10b 1
!s100 kG?GBRChF[jJll1:hnGSE3
!s100 e[AQZIQL1WhhBkg43KN<21
R2
IY51_GQHHW95C`9PL^lW1^1
IjhKJIgZdj`E=HnkaeNg780
R3
S1
R4
R5
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
!i122 179
L0 16 103
!i122 201
L0 16 108
R6
r1
!s85 0
31
R14
R15
R16
!i113 1
R10
R11
vram
R0
R1
!i10b 1
!s100 dZKNfO2TYfeLbPoNKW=hB0
R2
IDZl^==D[@o2_3Ol@OIBJh0
R3
S1
R4
w1792473740
8ram.sv
Fram.sv
!i122 215
L0 4 23
R6
r1
!s85 0
@@ -335,84 +410,59 @@ R9
!i113 1
R10
R11
vram
R0
R1
!i10b 1
!s100 KIM1Bhf3dZb;O;EN9OH^^3
R2
IKXXONS>@k4@GP6o<Rk0zM0
R3
S1
R4
R5
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
!i122 180
L0 4 23
R6
r1
!s85 0
31
Z18 !s108 1792115142.000000
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv|
!i113 1
R10
R11
vregister_file
R0
R1
!i10b 1
!s100 TM=bHR22b5BF7BGjf7QYh2
R2
IeQ`65;PU]l@K@hnj8YkL62
I4OUYbMgQ4IJBD?0blX]Lm2
R3
S1
R4
R15
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
!i122 181
R21
8register_file.sv
Fregister_file.sv
!i122 215
L0 4 25
R6
r1
!s85 0
31
R18
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv|
R7
R8
R9
!i113 1
R10
R11
vrom
R0
R1
R18
!i10b 1
!s100 Vd76Vlo;I1?9UcSC7fcOP0
!s100 zLh]ZiD;FcdhG3I]1fk3P2
R2
I:a:Y?o9P[59dd<zBhnkfn0
I8o3_6E:`aQh^;J7VVYZIJ2
R3
S1
R4
w1792114203
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
!i122 182
R21
8rom.sv
From.sv
!i122 218
L0 4 18
R6
r1
!s85 0
31
R18
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv|
R19
Z24 !s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv|
R20
!i113 1
R10
R11
vseven_seg
R0
R1
Z25 !s110 1793848696
!i10b 1
!s100 ^3LXNA>i`]oD>7BNB:Rd?3
R2
@@ -420,41 +470,41 @@ IedFU7?nB5ZOibY?bC8=L41
R3
S1
R4
R16
R22
8seven_seg.sv
Fseven_seg.sv
!i122 185
!i122 207
L0 3 23
R6
r1
!s85 0
31
R18
Z19 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
Z26 !s108 1793848696.000000
Z27 !s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
Z28 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv|
!i113 1
R10
R11
vseven_seg_4digit
R0
R1
R25
!i10b 1
!s100 MRn_YTIW^S4cR39n=0RMi0
!s100 kl;BlN=e=UfChCC`DZJA01
R2
IYaD1MHdmne1KMOgV5M^f70
IS1jLgB;Q?W`6]WHX6bTgl1
R3
S1
R4
w1791866874
w1792119097
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
!i122 184
!i122 206
L0 5 37
R6
r1
!s85 0
31
R18
R26
!s107 seven_seg.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv|
!i113 1
@@ -462,7 +512,7 @@ R10
R11
vseven_seg_tb
R0
R1
R25
!i10b 1
!s100 jPijM2]zTRBV8TFdD?Q`I1
R2
@@ -473,15 +523,15 @@ R4
w1788418794
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
!i122 185
!i122 207
L0 3 66
R6
r1
!s85 0
31
R18
R19
R20
R26
R27
R28
!i113 1
R10
R11
@@ -495,24 +545,24 @@ IzJzhQo`olGLa0f4lM55A42
R3
S1
R4
R16
R22
8shifter.sv
Fshifter.sv
!i122 187
R17
!i122 215
R23
R6
r1
!s85 0
31
R18
Z21 !s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
Z22 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
R7
R8
R9
!i113 1
R10
R11
vshifter_tb
R0
R1
R25
!i10b 1
!s100 TiConQ4:_WTd:PLNNG`Po3
R2
@@ -520,18 +570,18 @@ Ia6ohf92lD=P<P]lDi667i2
R3
S1
R4
R14
R17
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
!i122 187
!i122 209
L0 2 76
R6
r1
!s85 0
31
R18
R21
R22
R26
!s107 shifter.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv|
!i113 1
R10
R11
@@ -539,24 +589,24 @@ vsign_extender
R0
R1
!i10b 1
!s100 VOYzaEd320YMo:nYU=@hG2
!s100 dXL[XDH1LfSe`PJjMiOTD2
R2
Ic?f[J?J3HD0]DeV]c1EoN3
I0BX4cd5>`EdI:oOG868Jh2
R3
S1
R4
R15
8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
!i122 188
L0 4 15
w1792644107
8sign_extender.sv
Fsign_extender.sv
!i122 215
L0 4 12
R6
r1
!s85 0
31
R18
!s107 /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv|
R7
R8
R9
!i113 1
R10
R11