diff --git a/ModelSim/Assignment_2.cr.mti b/ModelSim/Assignment_2.cr.mti index 3c10b2c..62ca311 100644 --- a/ModelSim/Assignment_2.cr.mti +++ b/ModelSim/Assignment_2.cr.mti @@ -116,6 +116,14 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: seven_seg_tb +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module lu +-- Compiling module lu_tb + +Top level modules: + lu_tb + } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module asu @@ -124,13 +132,12 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: asu_tb -} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module lu --- Compiling module lu_tb +-- Compiling module gatereg Top level modules: - lu_tb + gatereg } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 @@ -156,15 +163,6 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: instruction_counter -} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv -Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module asu --- Compiling module lu --- Compiling module alu - -Top level modules: - alu - } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module rom @@ -174,6 +172,15 @@ Top level modules: rom ByteIM +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu + +Top level modules: + alu + } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module seven_seg @@ -190,6 +197,26 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: instruction_classifier_tb +} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module rom +-- Compiling module ram +-- Compiling module register_file +-- Compiling module instruction_counter +-- Compiling module instruction_classifier +-- Compiling module control_unit +-- Compiling module asu +-- Compiling module lu +-- Compiling module alu +-- Compiling module shifter +-- Compiling module sign_extender +-- Compiling module gatereg +-- Compiling module assignment3 + +Top level modules: + shifter + assignment3 + } {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module register_file diff --git a/ModelSim/Assignment_2.mpf b/ModelSim/Assignment_2.mpf index 09c2ff3..6d0337f 100644 --- a/ModelSim/Assignment_2.mpf +++ b/ModelSim/Assignment_2.mpf @@ -410,51 +410,55 @@ ConcurrentFileLimit = 40 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 22 +Project_Files_Count = 24 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv -Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv -Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792114203 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv -Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv -Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv -Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792473740 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv -Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv -Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv -Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228118 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228118 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv -Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1790228042 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv -Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv -Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792119882 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv -Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788418794 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv -Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv -Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv -Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788418794 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv +Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv +Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789513270 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv +Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1793848262 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv -Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv -Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv -Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792113810 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv +Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792644107 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv +Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv -Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792112374 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv -Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1791866874 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848949 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv +Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792115823 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv -Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv -Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv +Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1792119097 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_22 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv +Project_File_P_22 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1793848882 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_23 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv +Project_File_P_23 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ModelSim/alu.sv.bak b/ModelSim/alu.sv.bak new file mode 100644 index 0000000..9f447b0 --- /dev/null +++ b/ModelSim/alu.sv.bak @@ -0,0 +1,20 @@ +`include "asu.v" +`include "lu.v" + +// flags[0:0] = Cout +// flags[1:1] = Overflow +module alu #(width=8)(input logic [3:0] op, + input logic [width-1:0] A, input logic [width-1:0] B. + output logic [width-1:0] OUT_1, output logic flags[1:0]); + + logic [width-1:0] asu_out; + logic [1:0] asu_flags; + logic [0:0] asu_op; + asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]); + + logic [width-1:0] lu_out; + lu #(width) logic_unit(op[1:0], A, B, lu_out); + + // Cout = asu_flags[0] + // Overflow = asu_flags[0] ^ asu_flags[1] +endmodule \ No newline at end of file diff --git a/ModelSim/assignment2.sv b/ModelSim/assignment2.sv index eb13b83..1fcf369 100644 --- a/ModelSim/assignment2.sv +++ b/ModelSim/assignment2.sv @@ -91,8 +91,15 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( `ifdef QUARTUS_SYNTH // Temporary Test output // assign PC_Reg_Display = 16'hC342; - - assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; + // assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; + always_comb begin + if (HID_PC == 1'b1) begin + PC_Reg_Display = (HID_Hi_Low) ? pc_addr[31:16] : pc_addr[15:0]; + end + else begin + PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0]; + end + end seven_seg_4digit display ( .num(PC_Reg_Display), @@ -101,6 +108,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) ( .segments2(out_seg_2), .segments3(out_seg_3) ); -`endif +`endif // code for board test outputs only + endmodule `endif diff --git a/ModelSim/assignment2.sv.bak b/ModelSim/assignment2.sv.bak new file mode 100644 index 0000000..ed1d9f7 --- /dev/null +++ b/ModelSim/assignment2.sv.bak @@ -0,0 +1,19 @@ +`include "rom.sv" +`include "ram.sv" +`include "instruction_counter.sv" +`include "instruction_classifier.sv" +`include "alu.sv" + + +module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk); + + logic [romsz-1:0] pc_addr; + logic [0:0] pc_we; + logic [2**width-1:0] instruction; + + instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr); + ROM rom #(romsz, 2**width)(); + RAM ram #(ramsz, 2**width)(); + alu alu #(width)(); + +endmodule \ No newline at end of file diff --git a/ModelSim/assignment3.sv b/ModelSim/assignment3.sv new file mode 100644 index 0000000..d796d80 --- /dev/null +++ b/ModelSim/assignment3.sv @@ -0,0 +1,95 @@ +`ifndef ASS_3_SV +`define ASS_3_SV + +`include "rom.sv" +`include "ram.sv" +`include "register_file.sv" +`include "instruction_counter.sv" +`include "control_unit.sv" +`include "alu.sv" +`include "shifter.sv" +`include "sign_extender.sv" +`include "gatereg.sv" + +module assignment3 #(width=5, romsz=9, ramsz=10)( + input logic [0:0] clk, input logic [0:0] rst + ); + logic [31:0] regs_out [32]; + logic [2**width-1:0] pc_addr, pc_addr_2; + logic [2**width-1:0] pc_addr_write; + logic [0:0] pc_we; + // TODO: Verify if we need a clk gating on pc_addr + instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); + gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2); + + + logic [2**width-1:0] rom_rd; + logic [2**width-1:0] rom_addr; + logic [2**width-1:0] instruction, instruction_1; + rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd); + gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr); + gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction); + gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1); + + + logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw; + logic [3:0] cu_alu_fn, ALU_FN; + logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD; + control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0], + cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw + ); + gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST); + gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC); + gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN); + + gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B); + gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE); + + gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE); + gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD); + + logic [2**width-1:0] regf_rs, regf_rs_1; + logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2; + logic [7:0] regf_a3, regf_a3_2; + logic [2**width-1:0] rd, rd_mem, rd_alu; + assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu; + assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16]; + // TODO: Connect inputs + gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2); + register_file #(width, 5) REGS ( + ~clk, REG_WE, + regf_a3_2[4:0], rd, + instruction[25:21], regf_rs, + instruction[20:16], regf_rt, + regs_out + ); + gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1); + gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1); + gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2); + + logic [2**width-1:0] sign_ext_imm, rt_imm; + sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm); + gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm); + + + logic [2**width-1:0] alu_out, alu_out_1, alu_out_2; + logic [3:0] alu_flags, alu_flags_1; + alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags); + gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1); + gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2); + gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1); + assign rd_alu = alu_out_2; + + logic [2**width-1:0] new_pc_addr, new_pc_addr_1; + assign new_pc_addr = (rt_imm << 2) + pc_addr_2; + gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1); + + + assign pc_addr_write = new_pc_addr_1; + assign pc_we = B & alu_flags_1[2]; + logic [2**width-1:0] mem_out, mem_out_1; + ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out); + gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1); + assign rd_mem = mem_out_1; +endmodule +`endif diff --git a/ModelSim/assignment3.sv.bak b/ModelSim/assignment3.sv.bak new file mode 100644 index 0000000..9c96fa9 --- /dev/null +++ b/ModelSim/assignment3.sv.bak @@ -0,0 +1,95 @@ +`ifndef ASS_3_SV +`define ASS_3_SV + +`include "rom.sv" +`include "ram.sv" +`include "register_file.sv" +`include "instruction_counter.sv" +`include "control_unit.sv" +`include "alu.sv" +`include "shifter.sv" +`include "sign_extender.sv" +`include "gatereg.sv" + +module assignment3 #(width=5, romsz=9, ramsz=10)( + input logic [0:0] clk, input logic [0:0] rst + ); + logic [31:0] regs_out [32]; + logic [2**width-1:0] pc_addr, pc_addr_2; + logic [2**width-1:0] pc_addr_write; + logic [0:0] pc_we; + // TODO: Verify if we need a clk gating on pc_addr + instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); + gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2); + + + logic [2**width-1:0] rom_rd; + logic [2**width-1:0] rom_addr; + logic [2**width-1:0] instruction, instruction_1; + rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd); + gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr); + gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction); + gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1); + + + logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw; + logic [3:0] cu_alu_fn, ALU_FN; + logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD; + control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0], + cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw + ); + gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST); + gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC); + gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN); + + gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B); + gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE); + + gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE); + gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD); + + logic [2**width-1:0] regf_rs, regf_rs_1; + logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2; + logic [7:0] regf_a3, regf_a3_2; + logic [2**width-1:0] rd, rd_mem, rd_alu; + assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu; + assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16]; + // TODO: Connect inputs + gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2); + register_file #(width, 5) REGS ( + ~clk, REG_WE, + regf_a3_2[4:0], rd, + instruction[25:21], regf_rs, + instruction[20:16], regf_rt, + regs_out + ); + gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1); + gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1); + gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2); + + logic [2**width-1:0] sign_ext_imm, rt_imm; + sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm); + gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm); + + + logic [2**width-1:0] alu_out, alu_out_1, alu_out_2; + logic [3:0] alu_flags, alu_flags_1; + alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags); + gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1); + gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2); + gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1); + assign rd_alu = alu_out_2; + + logic [2**width-1:0] new_pc_addr, new_pc_addr_1; + assign new_pc_addr = (rt_imm << 2) + pc_addr_2; + gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1); + + + assign pc_addr_write = new_pc_addr_1; + assign pc_we = B & alu_flags_1[2]; + logic [2**width-1:0] mem_out, mem_out_1; + ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out); + gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1); + assign rd_mem = mem_out_1; +endmodule +`endif diff --git a/ModelSim/asu.sv.bak b/ModelSim/asu.sv.bak new file mode 100644 index 0000000..eb4fd6f --- /dev/null +++ b/ModelSim/asu.sv.bak @@ -0,0 +1,16 @@ +module asu #(width=8)(input logic [0:0] op, + input logic[width-1:0] A, input logic[width-1:0] B, + output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN); + + logic [width-1:0] operand; + always_comb begin + // A + (sub) ? B : -B + // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis + operand = (B ^ {(width){op}}); + {COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op}; + end + + // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported? + // Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture + assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1]; +endmodule diff --git a/ModelSim/gatereg.sv b/ModelSim/gatereg.sv new file mode 100644 index 0000000..7c4d604 --- /dev/null +++ b/ModelSim/gatereg.sv @@ -0,0 +1,21 @@ +module gatereg #(width, ndelay=1)( + input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en, + input logic [2**width-1:0] in, output logic [2**width-1:0] out +); + logic [2**width-1:0] hold_value[ndelay]; + + assign out = hold_value[ndelay-1]; + always_ff @( posedge clk ) begin + if (rst) begin + for (integer i = 0; i < ndelay; ++i) begin + hold_value[i] <= {(2**width){1'b0}}; + end + end else if (en) begin + hold_value[0] <= in; + for (integer i = 1; i < ndelay; ++i) begin + hold_value[i] <= hold_value[i-1]; + end + end + end + +endmodule \ No newline at end of file diff --git a/ModelSim/lu.sv.bak b/ModelSim/lu.sv.bak new file mode 100644 index 0000000..145eda2 --- /dev/null +++ b/ModelSim/lu.sv.bak @@ -0,0 +1,12 @@ +module lu #(width=8) ( + input logic [1:0] op, + input logic [width-1:0] A, input logic [width-1:0] B, + output logic [width-1:0] OUT_1); + + always_comb begin + if (op == 2'b00) OUT_1 = A & B; + else if (op == 2'b01) OUT_1 = A | B; + else if (op == 2'b10) OUT_1 = A ^ B; + else if (op == 2'b10) OUT_1 = ~(A | B); + end +endmodule \ No newline at end of file diff --git a/ModelSim/ram.sv b/ModelSim/ram.sv index 40d16dd..d380550 100644 --- a/ModelSim/ram.sv +++ b/ModelSim/ram.sv @@ -5,8 +5,8 @@ module ram #(addrwidth=9, datawidth=5)( input logic [0:0] clk, input logic [0:0] rst, input logic [addrwidth-1:0] addr, input logic [0:0] we, - input logic [datawidth-1:0] data_in, - output logic [datawidth-1:0] data_out + input logic [2**datawidth-1:0] data_in, + output logic [2**datawidth-1:0] data_out ); // TODO: Make this byte-sized, NOT word-sized! diff --git a/ModelSim/rom.sv b/ModelSim/rom.sv index 08e882a..9f9a666 100644 --- a/ModelSim/rom.sv +++ b/ModelSim/rom.sv @@ -15,7 +15,7 @@ module rom #(parameter m=7,p=4) ( `ifdef QUARTUS_SYNTH $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary `else - $readmemh("../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary + $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary `endif end endmodule // end rom module diff --git a/ModelSim/seven_seg_4digit.sv b/ModelSim/seven_seg_4digit.sv index 3ccedd4..8fcb246 100644 --- a/ModelSim/seven_seg_4digit.sv +++ b/ModelSim/seven_seg_4digit.sv @@ -13,28 +13,28 @@ module seven_seg_4digit ( // Rightmost digit seven_seg digit0 ( .num(num[3:0]), - .rbi_inv(1'b0), + .rbi_inv(1'b1), .segments(segments0) ); // Second digit from right seven_seg digit1 ( .num(num[7:4]), - .rbi_inv(1'b0), + .rbi_inv(1'b1), .segments(segments1) ); // Third digit from right seven_seg digit2 ( .num(num[11:8]), - .rbi_inv(1'b0), + .rbi_inv(1'b1), .segments(segments2) ); // Leftmost digit seven_seg digit3 ( .num(num[15:12]), - .rbi_inv(1'b0), + .rbi_inv(1'b1), .segments(segments3) ); diff --git a/ModelSim/shifter.sv.bak b/ModelSim/shifter.sv.bak new file mode 100644 index 0000000..7b84b49 --- /dev/null +++ b/ModelSim/shifter.sv.bak @@ -0,0 +1,19 @@ +`ifndef SHIFTER_H_SV +`define SHIFTER_H_SV +module shifter #(width=8)(input logic [2:0] op, + input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B, + output logic[width-1:0] OUT_1); + + always_comb begin + case (op) + 3'b000: OUT_1 = A << C; + 3'b001: OUT_1 = A >> C; + 3'b011: OUT_1 = $signed(A) >>> C; + 3'b100: OUT_1 = A << B; + 3'b101: OUT_1 = A >> B; + 3'b111: OUT_1 = $signed(A) >>> B; + default:OUT_1 = A; + endcase + end +endmodule +`endif \ No newline at end of file diff --git a/ModelSim/sign_extender.sv b/ModelSim/sign_extender.sv index a0e2ef9..38d339a 100644 --- a/ModelSim/sign_extender.sv +++ b/ModelSim/sign_extender.sv @@ -7,13 +7,10 @@ module sign_extender #(in_width=4, out_width=5)( output logic [2**out_width-1:0] ext_val ); logic [0:0] msb; - assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1); - always_comb begin - if (op) begin - ext_val = { {(2**(out_width-in_width)){msb}}, val}; - end else begin - ext_val = ({{(2**(out_width-in_width)){1'b0}}, val}); - end - end + assign msb = (val >> (in_width-1)) & 1'b1; + assign ext_val = op + ? { {(2**out_width - 2**in_width){msb}}, val } + : { {(2**out_width - 2**in_width){1'b0}}, val }; + endmodule `endif diff --git a/ModelSim/transcript b/ModelSim/transcript index e4c5b17..c45ebf8 100644 --- a/ModelSim/transcript +++ b/ModelSim/transcript @@ -4,7 +4,7 @@ # Compile of assignment2.sv was successful. # Compile of asu.sv was successful. # Compile of asu_tb.sv was successful. -# Compile of ByteIM.sv was successful. +# Compile of ByteIM.sv failed with 1 errors. # Compile of control_unit.sv was successful. # Compile of instruction_classifier.sv was successful. # Compile of instruction_classifier_tb.sv was successful. @@ -21,111 +21,12 @@ # Compile of shifter.sv was successful. # Compile of shifter_tb.sv was successful. # Compile of sign_extender.sv was successful. -# 22 compiles, 0 failed with no errors. -vsim work.mips_tb -# vsim work.mips_tb -# Start time: 12:45:51 on Oct 16,2026 -# Loading sv_std.std -# Loading work.mips_tb -# Loading work.assignment2 -# Loading work.instruction_counter -# Loading work.rom -# Loading work.ram -# Loading work.control_unit -# Loading work.instruction_classifier -# Loading work.register_file -# Loading work.sign_extender -# Loading work.alu -# Loading work.asu -# Loading work.lu -# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61 -# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -add wave -position end sim:/mips_tb/rst -add wave -position end sim:/mips_tb/clk -run -# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18) -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM -run -force -freeze sim:/mips_tb/clk 1 0, 0 {50 ns} -r 100 -force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20 -run -quit -sim -# End time: 12:47:55 on Oct 16,2026, Elapsed time: 0:02:04 -# Errors: 0, Warnings: 7 -vsim work.mips_tb -# vsim work.mips_tb -# Start time: 12:47:56 on Oct 16,2026 -# Loading sv_std.std -# Loading work.mips_tb -# Loading work.assignment2 -# Loading work.instruction_counter -# Loading work.rom -# Loading work.ram -# Loading work.control_unit -# Loading work.instruction_classifier -# Loading work.register_file -# Loading work.sign_extender -# Loading work.alu -# Loading work.asu -# Loading work.lu -# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61 -# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -add wave -position end sim:/mips_tb/clk -add wave -position end sim:/mips_tb/rst -add wave -position end sim:/mips_tb/num_errors -force -freeze sim:/mips_tb/rst 1 0 -cancel 20 -force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20 -force -freeze sim:/mips_tb/clk 0 0, 1 {50 ns} -r 100 -run -# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18) -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM -add wave -position end sim:/mips_tb/CPU/regs_out -run -quit -sim -# End time: 12:50:34 on Oct 16,2026, Elapsed time: 0:02:38 -# Errors: 0, Warnings: 6 -vsim work.mips_tb -# vsim work.mips_tb -# Start time: 12:50:36 on Oct 16,2026 -# Loading sv_std.std -# Loading work.mips_tb -# Loading work.assignment2 -# Loading work.instruction_counter -# Loading work.rom -# Loading work.ram -# Loading work.control_unit -# Loading work.instruction_classifier -# Loading work.register_file -# Loading work.sign_extender -# Loading work.alu -# Loading work.asu -# Loading work.lu -# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61 -# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9). -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64 -add wave -position end sim:/mips_tb/clk -add wave -position end sim:/mips_tb/rst -add wave -position end sim:/mips_tb/num_errors -add wave -position end sim:/mips_tb/CPU/regs_out -run -# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18) -# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM -# End time: 12:55:34 on Oct 16,2026, Elapsed time: 0:04:58 -# Errors: 0, Warnings: 6 +# Compile of assignment3.sv failed with 1 errors. +# Compile of gatereg.sv was successful. +# 24 compiles, 2 failed with 2 errors. +# Compile of assignment3.sv failed with 1 errors. +# Compile of assignment3.sv failed with 1 errors. +# Compile of assignment3.sv was successful. +# Compile of ByteIM.sv failed with 1 errors. +# Compile of ByteIM.sv failed with 1 errors. +# Compile of ByteIM.sv was successful. diff --git a/ModelSim/work/_info b/ModelSim/work/_info index 7f05651..d203404 100644 --- a/ModelSim/work/_info +++ b/ModelSim/work/_info @@ -11,32 +11,32 @@ cModel Technology d/home/oliver/intelFPGA/20.1/modelsim_ase/bin valu Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3 -Z1 !s110 1792115142 +Z1 !s110 1793848891 !i10b 1 -!s100 kh0:K2RRk@1 +!s100 KP25E<`D0[YGcmY_0OYR>3 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1 -Im?EZg:mSI^D?=D>QBY^1B0 +I9jL53QmOM7UI;=OA3U@eg3 Z3 VDg1SIo80bB@j0V0VzS_@n1 S1 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim -Z5 w1792113810 +Z5 w1792115823 8alu.sv Falu.sv -!i122 179 -L0 10 33 +!i122 215 +L0 10 35 Z6 OV;L;2020.1;71 r1 !s85 0 31 -Z7 !s108 1792115141.000000 -Z8 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| -Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| +Z7 !s108 1793848891.000000 +Z8 !s107 gatereg.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv| +Z9 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv| !i113 1 Z10 o-work work -sv Z11 tCvgOpt 0 valu_tb R0 -Z12 !s110 1792115141 +Z12 !s110 1793848695 !i10b 1 !s100 8=>8o`KV]hRM]V8AV?S[C1 R2 @@ -47,13 +47,13 @@ R4 Z13 w1789355084 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv -!i122 168 +!i122 190 L0 3 214 R6 r1 !s85 0 31 -R7 +Z14 !s108 1793848695.000000 !s107 lu.sv|asu.sv|alu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv| !i113 1 @@ -61,19 +61,44 @@ R10 R11 vassignment2 R0 -R1 +R12 !i10b 1 -!s100 9I6c?eD]amhL__2Jz1 +!s100 H2eJB`][V_?PYNI3VTRV10 R2 -IFfHj7VAM^H^0]`kMd62bZ2 +IXCN5]eBIk8QocLJ3 R3 S1 R4 -R5 +w1792119882 8assignment2.sv Fassignment2.sv -!i122 179 -L0 15 91 +!i122 201 +L0 15 99 +R6 +r1 +!s85 0 +31 +R14 +Z15 !s107 seven_seg.sv|seven_seg_4digit.sv|sign_extender.sv|shifter.sv|lu.sv|asu.sv|alu.sv|instruction_classifier.sv|control_unit.sv|instruction_counter.sv|register_file.sv|ram.sv|rom.sv|assignment2.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| +Z16 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv| +!i113 1 +R10 +R11 +vassignment3 +R0 +R1 +!i10b 1 +!s100 K6T8de>1WT94z3K=N1kLg0 +R2 +IMP2VlhaonMhKfg0_Nm3;Y0 +R3 +S1 +R4 +w1793848882 +8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv +F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv +!i122 215 +L0 14 81 R6 r1 !s85 0 @@ -97,7 +122,7 @@ R4 w1790228118 8asu.sv Fasu.sv -!i122 179 +!i122 215 L0 4 21 R6 r1 @@ -119,16 +144,16 @@ IcS>Hk9oO:RGFmfdUY9[i90 R3 S1 R4 -Z14 w1789513270 +Z17 w1789513270 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv -!i122 171 +!i122 193 L0 3 120 R6 r1 !s85 0 31 -R7 +R14 !s107 asu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv| !i113 1 @@ -136,7 +161,7 @@ R10 R11 vByteIM R0 -R12 +Z18 !s110 1793848955 !i10b 1 !s100 ]V5Di195@?V=P`Y?PM;U=0 R2 @@ -144,18 +169,18 @@ Ie:hP;^zFCE^LSAOVoDF6C3 R3 S1 R4 -w1792112374 +w1793848949 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv -!i122 172 +!i122 218 L0 3 12 R6 r1 !s85 0 31 -R7 +Z19 !s108 1793848955.000000 !s107 rom.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv| -!s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv| +Z20 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv| !i113 1 R10 R11 @@ -170,10 +195,10 @@ IN9L1dbI=^fl9KlmLIEFaZ0 R3 S1 R4 -Z15 w1792112234 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