Added project to modelsim
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@@ -4,7 +4,7 @@
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# Compile of assignment2.sv was successful.
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# Compile of asu.sv was successful.
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# Compile of asu_tb.sv was successful.
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# Compile of ByteIM.sv was successful.
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# Compile of ByteIM.sv failed with 1 errors.
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# Compile of control_unit.sv was successful.
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# Compile of instruction_classifier.sv was successful.
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# Compile of instruction_classifier_tb.sv was successful.
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@@ -21,111 +21,12 @@
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# Compile of shifter.sv was successful.
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# Compile of shifter_tb.sv was successful.
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# Compile of sign_extender.sv was successful.
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# 22 compiles, 0 failed with no errors.
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vsim work.mips_tb
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# vsim work.mips_tb
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# Start time: 12:45:51 on Oct 16,2026
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# Loading sv_std.std
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# Loading work.mips_tb
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# Loading work.assignment2
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# Loading work.instruction_counter
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# Loading work.rom
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# Loading work.ram
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# Loading work.control_unit
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# Loading work.instruction_classifier
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# Loading work.register_file
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# Loading work.sign_extender
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# Loading work.alu
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# Loading work.asu
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# Loading work.lu
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# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
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# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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add wave -position end sim:/mips_tb/rst
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add wave -position end sim:/mips_tb/clk
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run
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# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
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run
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force -freeze sim:/mips_tb/clk 1 0, 0 {50 ns} -r 100
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force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
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run
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quit -sim
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# End time: 12:47:55 on Oct 16,2026, Elapsed time: 0:02:04
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# Errors: 0, Warnings: 7
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vsim work.mips_tb
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# vsim work.mips_tb
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# Start time: 12:47:56 on Oct 16,2026
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# Loading sv_std.std
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# Loading work.mips_tb
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# Loading work.assignment2
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# Loading work.instruction_counter
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# Loading work.rom
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# Loading work.ram
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# Loading work.control_unit
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# Loading work.instruction_classifier
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# Loading work.register_file
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# Loading work.sign_extender
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# Loading work.alu
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# Loading work.asu
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# Loading work.lu
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# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
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# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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add wave -position end sim:/mips_tb/clk
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add wave -position end sim:/mips_tb/rst
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add wave -position end sim:/mips_tb/num_errors
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force -freeze sim:/mips_tb/rst 1 0 -cancel 20
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force -freeze sim:/mips_tb/clk 1 0, 0 {10 ns} -r 20
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force -freeze sim:/mips_tb/clk 0 0, 1 {50 ns} -r 100
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run
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# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
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add wave -position end sim:/mips_tb/CPU/regs_out
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run
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quit -sim
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# End time: 12:50:34 on Oct 16,2026, Elapsed time: 0:02:38
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# Errors: 0, Warnings: 6
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vsim work.mips_tb
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# vsim work.mips_tb
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# Start time: 12:50:36 on Oct 16,2026
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# Loading sv_std.std
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# Loading work.mips_tb
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# Loading work.assignment2
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# Loading work.instruction_counter
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# Loading work.rom
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# Loading work.ram
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# Loading work.control_unit
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# Loading work.instruction_classifier
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# Loading work.register_file
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# Loading work.sign_extender
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# Loading work.alu
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# Loading work.asu
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# Loading work.lu
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# ** Warning: (vsim-3015) [PCDPC] - Port size (10) does not match connection size (32) for port 'Ad'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(5).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM File: assignment2.sv Line: 61
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# ** Warning: (vsim-3015) [PCDPC] - Port size (9) does not match connection size (32) for port 'addr'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(6).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_in'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(8).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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# ** Warning: (vsim-3015) [PCDPC] - Port size (5) does not match connection size (32) for port 'data_out'. The port definition is at: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv(9).
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/RAM File: assignment2.sv Line: 64
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add wave -position end sim:/mips_tb/clk
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add wave -position end sim:/mips_tb/rst
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add wave -position end sim:/mips_tb/num_errors
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add wave -position end sim:/mips_tb/CPU/regs_out
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run
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# ** Warning: (vsim-PLI-3408) Too few data words read on line 18 of file "../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex". Expected 1024, found 18. : /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv(18)
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# Time: 0 ns Iteration: 0 Instance: /mips_tb/CPU/ROM
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# End time: 12:55:34 on Oct 16,2026, Elapsed time: 0:04:58
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# Errors: 0, Warnings: 6
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# Compile of assignment3.sv failed with 1 errors.
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# Compile of gatereg.sv was successful.
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# 24 compiles, 2 failed with 2 errors.
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# Compile of assignment3.sv failed with 1 errors.
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# Compile of assignment3.sv failed with 1 errors.
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# Compile of assignment3.sv was successful.
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# Compile of ByteIM.sv failed with 1 errors.
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# Compile of ByteIM.sv failed with 1 errors.
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# Compile of ByteIM.sv was successful.
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