Added project to modelsim

This commit is contained in:
TroubleElectrical committed 2026-11-05 14:25:34 +11:00
1 parent 38fa35fccd
commit 00b2087860
22 files changed
+581 -297

No files matched your search

+5 -8
View File
@@ -7,13 +7,10 @@ module sign_extender #(in_width=4, out_width=5)(
output logic [2**out_width-1:0] ext_val
);
logic [0:0] msb;
assign msb = (val & {1'b1, {(in_width-1){1'b0}}}) >> (in_width-1);
always_comb begin
if (op) begin
ext_val = { {(2**(out_width-in_width)){msb}}, val};
end else begin
ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
end
end
assign msb = (val >> (in_width-1)) & 1'b1;
assign ext_val = op
? { {(2**out_width - 2**in_width){msb}}, val }
: { {(2**out_width - 2**in_width){1'b0}}, val };
endmodule
`endif