Added project to modelsim

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TroubleElectrical committed 2026-11-05 14:25:34 +11:00
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`ifndef SHIFTER_H_SV
`define SHIFTER_H_SV
module shifter #(width=8)(input logic [2:0] op,
input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
output logic[width-1:0] OUT_1);
always_comb begin
case (op)
3'b000: OUT_1 = A << C;
3'b001: OUT_1 = A >> C;
3'b011: OUT_1 = $signed(A) >>> C;
3'b100: OUT_1 = A << B;
3'b101: OUT_1 = A >> B;
3'b111: OUT_1 = $signed(A) >>> B;
default:OUT_1 = A;
endcase
end
endmodule
`endif