Added project to modelsim

ModelSim/ram.sv

@@ -5,8 +5,8 @@ module ram #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk, input logic [0:0] rst,
     input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
-    input logic [datawidth-1:0] data_in,
-    output logic [datawidth-1:0] data_out
+    input logic [2**datawidth-1:0] data_in,
+    output logic [2**datawidth-1:0] data_out
 );
 
     // TODO: Make this byte-sized, NOT word-sized!