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FPGA_Uni/ModelSim/alu.sv.bak
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`include "asu.v"
`include "lu.v"
// flags[0:0] = Cout
// flags[1:1] = Overflow
module alu #(width=8)(input logic [3:0] op,
input logic [width-1:0] A, input logic [width-1:0] B.
output logic [width-1:0] OUT_1, output logic flags[1:0]);
logic [width-1:0] asu_out;
logic [1:0] asu_flags;
logic [0:0] asu_op;
asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
logic [width-1:0] lu_out;
lu #(width) logic_unit(op[1:0], A, B, lu_out);
// Cout = asu_flags[0]
// Overflow = asu_flags[0] ^ asu_flags[1]
endmodule