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FPGA_Uni
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f8ea90e41d9796f0294345f3ef1534fa9ceed759
FPGA_Uni
/
Quartus
/
A1_Q2
/
simulation
T
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TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
..
questa
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00