53 lines
1.7 KiB
Systemverilog
53 lines
1.7 KiB
Systemverilog
`include "instruction_classifier.sv"
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module instruction_classifier_tb();
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logic [5:0] op;
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logic [6:0] C;
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logic [5:0] ops[12];
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logic [6:0] C_exp[12];
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instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]);
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integer error_count;
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initial begin
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ops[0] = 6'b000000;
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C_exp[0] = 7'b1000000;
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ops[1] = 6'b000001;
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C_exp[1] = 7'b0100000;
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ops[2] = 6'b000010;
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C_exp[2] = 7'b0010000;
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ops[3] = 6'b000100;
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C_exp[3] = 7'b0001000;
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ops[4] = 6'b001000;
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C_exp[4] = 7'b0000100;
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ops[5] = 6'b010000;
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C_exp[5] = 7'b0000010;
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ops[6] = 6'b100000;
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C_exp[6] = 7'b0000001;
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ops[7] = 6'b000011;
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C_exp[7] = 7'b0010000;
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ops[8] = 6'b000101;
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C_exp[8] = 7'b0001000;
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ops[9] = 6'b001001;
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C_exp[9] = 7'b0000100;
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ops[10] = 6'b010001;
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C_exp[10] = 7'b0000010;
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ops[11] = 6'b100001;
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C_exp[11] = 7'b0000001;
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error_count = 0;
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$display("Beginning Instruction Classifier tests");
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for (integer N = 0; N < $size(ops); ++N) begin
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op = ops[N];
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#1;
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if (C != C_exp[N]) begin
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$display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]);
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error_count = error_count + 1;
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end
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$display("\tInstruction 0b%b produced 0b%b when 0b%b was expected", op, C, C_exp[N]);
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count);
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end
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endmodule |