FPGA_Uni

.cmp.kpt

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2_partition_pins.json

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(0).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(0).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(1).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(1).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(2).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(2).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(3).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(3).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(4).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(4).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(5).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(5).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(6).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(6).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(7).cnf.cdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(7).cnf.hdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(8).cnf.cdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(8).cnf.hdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(9).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(9).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(10).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(10).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(11).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(11).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(12).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(12).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(13).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(13).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(14).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(14).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(15).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(15).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(16).cnf.cdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(16).cnf.hdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(17).cnf.cdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(17).cnf.hdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(18).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(18).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(19).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(19).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(20).cnf.cdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(20).cnf.hdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.(21).cnf.cdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(21).cnf.hdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(22).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(22).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(23).cnf.cdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(23).cnf.hdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(24).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(24).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(25).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(25).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(26).cnf.cdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(26).cnf.hdb

Added Register Display Code

2026-10-15 14:35:10 +11:00

assignment2.(27).cnf.cdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(27).cnf.hdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(28).cnf.cdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(28).cnf.hdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(29).cnf.cdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(29).cnf.hdb

Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)

2026-10-13 15:12:00 +11:00

assignment2.(30).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(30).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(31).cnf.cdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(31).cnf.hdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(32).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(32).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(33).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(33).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(34).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(34).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(35).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(35).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(36).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(36).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(37).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(37).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(38).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(38).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(39).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(39).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(40).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(40).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(41).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(41).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(42).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(42).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(43).cnf.cdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(43).cnf.hdb

Updated Assignment2 with better register file module insantiation

2026-10-15 15:07:41 +11:00

assignment2.(44).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(44).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(45).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(45).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(46).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(46).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(47).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(47).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(48).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(48).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(49).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(49).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(50).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(50).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(51).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(51).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(52).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(52).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(53).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(53).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(54).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(54).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(55).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(55).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(56).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(56).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(57).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(57).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(58).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(58).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(59).cnf.cdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(59).cnf.hdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.(60).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(60).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(61).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(61).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(62).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(62).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(63).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(63).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(64).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(64).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(65).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(65).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(66).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(66).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(67).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(67).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(68).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(68).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(69).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(69).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(70).cnf.cdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(70).cnf.hdb

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.(71).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(71).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(72).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(72).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(73).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(73).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(74).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(74).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(75).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(75).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(76).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(76).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(77).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(77).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(78).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(78).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(79).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(79).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(80).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(80).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(81).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(81).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(82).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(82).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(83).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(83).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(84).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(84).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(85).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(85).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(86).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(86).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(87).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(87).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(88).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(88).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(89).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(89).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(90).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(90).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(91).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(91).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(92).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(92).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(93).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(93).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(94).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(94).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(95).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(95).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(96).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(96).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(97).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(97).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(98).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(98).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(99).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(99).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(100).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(100).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(101).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(101).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(102).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(102).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(103).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(103).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(104).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(104).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(105).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(105).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(106).cnf.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.(106).cnf.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.asm.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.asm.rdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cbx.xml

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.cmp_merge.kpt

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.cmp.bpm

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cmp.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cmp.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cmp.idb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cmp.logdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cmp.rdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.cyclonev_io_sim_cache.ff_0c_fast.hsd

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.cyclonev_io_sim_cache.ff_85c_fast.hsd

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.cyclonev_io_sim_cache.ii_0c_slow.hsd

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.cyclonev_io_sim_cache.ii_85c_slow.hsd

TODO: Remove Shifter Code

2026-10-13 16:57:03 +11:00

assignment2.db_info

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.drc.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.eda.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.fit.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.hier_info

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.hif

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.lpc.html

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.lpc.rdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.lpc.txt

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map_bb.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map_bb.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map_bb.logdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.ammdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.map.bpm

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.kpt

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.logdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.map.rdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.pplq.rdb

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

assignment2.pre_map.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.ram0_ram_d7e4eb10.hdl.mif

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.ram0_register_file_16097a2d.hdl.mif

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.ram0_rom_d8639f5.hdl.mif

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.root_partition.map.reg_db.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.routing.rdb

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.rtlv_sg_swap.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.rtlv_sg.cdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.rtlv.hdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.sld_design_entry_dsc.sci

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

assignment2.sld_design_entry.sci

Updated assignment 2 dependency modules (currently 8 errors in compile)

2026-10-13 12:23:52 +11:00

assignment2.smart_action.txt

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.sta_cmp.7_H6_slow_1100mv_85c.tdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.sta.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.sta.rdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tis_db_list.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.fast_1100mv_0c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.fast_1100mv_85c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.fastest_slow_1100mv_0c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.fastest_slow_1100mv_85c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.slow_1100mv_0c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tiscmp.slow_1100mv_85c.ddb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.tmw_info

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

assignment2.vpr.ammdb

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

prev_cmp_assignment2.qmsg

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00