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TroubleElectrical/FPGA_Uni
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FPGA_Uni/Quartus/A1_Q3/simulation/questa
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TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
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asu.sft
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
asu.svo
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
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