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FPGA_Uni
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de1f346f64db3d617e4afe37232c65f1fdc5e27e
FPGA_Uni
/
Quartus
/
A1_Q2
/
db
/
lu.tiscmp.fastest_slow_1100mv_0c.ddb
T
TroubleElectrical
2208eb4f16
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
2026-09-08 15:36:51 +10:00
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