This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
d962a1b557680e37a07a23049bbfdc5de7cd5f78
FPGA_Uni
/
Quartus
/
A2
/
db
/
assignment2.sld_design_entry_dsc.sci
T
TroubleElectrical
19b07b649d
Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
2026-10-13 13:24:44 +11:00
229 B
Raw
History
View Raw
Reference in new issue
View Git Blame
Copy Permalink
