29 lines
686 B
Systemverilog
29 lines
686 B
Systemverilog
`ifndef RAM_H
|
|
`define RAM_H
|
|
|
|
module ram #(addrwidth=9, datawidth=5)(
|
|
input logic [0:0] clk, input logic [0:0] rst,
|
|
input logic [addrwidth-1:0] addr,
|
|
input logic [0:0] we,
|
|
input logic [2**datawidth-1:0] data_in,
|
|
output logic [2**datawidth-1:0] data_out
|
|
);
|
|
|
|
// TODO: Make this byte-sized, NOT word-sized!
|
|
logic [2**datawidth-1:0] mem[0:255];
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (rst) begin
|
|
for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
|
|
mem[ADDR] <= 32'b0;
|
|
end
|
|
end else if (we) begin
|
|
mem[addr] <= data_in;
|
|
end
|
|
end
|
|
assign data_out = mem[addr];
|
|
|
|
endmodule
|
|
|
|
`endif
|