21 lines
661 B
Systemverilog
21 lines
661 B
Systemverilog
module gatereg #(width, ndelay=1)(
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input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
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input logic [2**width-1:0] in, output logic [2**width-1:0] out
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);
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logic [2**width-1:0] hold_value[ndelay];
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assign out = hold_value[ndelay-1];
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always_ff @( posedge clk ) begin
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if (rst) begin
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for (integer i = 0; i < ndelay; ++i) begin
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hold_value[i] <= {(2**width){1'b0}};
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end
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end else if (en) begin
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hold_value[0] <= in;
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for (integer i = 1; i < ndelay; ++i) begin
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hold_value[i] <= hold_value[i-1];
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end
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end
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end
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endmodule |