Files
FPGA_Uni/ModelSim/rom.sv
T

25 lines
702 B
Systemverilog

`ifndef ROM_H
`define ROM_H
module rom #(parameter m=7,p=4) (
input logic [m-1:0] Ad,
output logic [2**p-1:0] Dout
);
logic [2**p-1:0] mem[2**m];
assign Dout = mem[Ad>>2]; // Because word-size versus byte size hack
//Load the program in memory
// The machine code stored in text file program.dat written in Hex format
initial begin
`ifdef QUARTUS_SYNTH
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`else
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
`endif
end
endmodule // end rom module
`endif