Files
FPGA_Uni/Quartus/A2/db/assignment2.quiproj.36761.rdr.flock
T
TroubleElectrical d962a1b557 Added code to display current PC,
Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
2026-10-16 14:27:29 +11:00

0 lines
0 B
Plaintext