26 lines
1.0 KiB
Systemverilog
26 lines
1.0 KiB
Systemverilog
`ifndef ASU_H_SV
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`define ASU_H_SV
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`include "seven_seg.sv"
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module asu #(parameter width = 2)(
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input logic [0:0] op,
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input logic[2**width-1:0] A, input logic[2**width-1:0] B,
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output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN,
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output logic[7:0] out_seg_1);
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logic [2**width-1:0] operand;
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always_comb begin
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// A + (sub) ? B : -B
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// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
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//operand = (B ^ {(2**width){op}});
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operand = op == 1'b0 ? B : ~B;
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{COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
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end
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// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
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// Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
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assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
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seven_seg dut(OUT_1, 1, out_seg_1);
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endmodule
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`endif |