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92a0cb17da7f837175c689f4bd2c5ca19e7bdb7c
FPGA_Uni
/
Quartus
/
A2
T
History
TroubleElectrical
afb6fefe1b
Updated Assignment2 with better register file module insantiation
2026-10-15 15:07:41 +11:00
..
db
Updated Assignment2 with better register file module insantiation
2026-10-15 15:07:41 +11:00
incremental_db
TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
output_files
Updated Assignment2 with better register file module insantiation
2026-10-15 15:07:41 +11:00
simulation
/questa
TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
assignment2.qpf
Made Assignment 2 Quartus Project
2026-10-13 12:04:49 +11:00
assignment2.qsf
TODO: Remove Shifter Code
2026-10-13 16:57:03 +11:00
c5_pin_model_dump.txt
Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
2026-10-13 13:24:44 +11:00