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FPGA_Uni/Quartus/A2/output_files/assignment2.sta.summary
T
TroubleElectrical 8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used
(There was a compilation error before, also compiled and tested code on board)
2026-10-22 15:53:15 +11:00

54 lines
1.2 KiB
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Timing Analyzer Summary
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Type : Slow 1100mV 85C Model Setup 'clk[0]'
Slack : -16.465
TNS : -118835.451
Type : Slow 1100mV 85C Model Hold 'clk[0]'
Slack : 0.264
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -7384.648
Type : Slow 1100mV 0C Model Setup 'clk[0]'
Slack : -16.206
TNS : -116709.205
Type : Slow 1100mV 0C Model Hold 'clk[0]'
Slack : 0.246
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : -0.538
TNS : -7717.695
Type : Fast 1100mV 85C Model Setup 'clk[0]'
Slack : -8.528
TNS : -59505.666
Type : Fast 1100mV 85C Model Hold 'clk[0]'
Slack : 0.136
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk[0]'
Slack : 0.011
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk[0]'
Slack : -7.502
TNS : -52032.389
Type : Fast 1100mV 0C Model Hold 'clk[0]'
Slack : 0.124
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk[0]'
Slack : 0.008
TNS : 0.000
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