FPGA_Uni

lu.db_info

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.cmp.ammdb

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.cmp.cdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.cmp.dfp

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.cmp.hbdb.cdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.cmp.hbdb.hdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.cmp.hbdb.sig

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.cmp.hdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.cmp.logdb

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.cmp.rcfdb

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.map.cdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.map.dpi

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.map.hbdb.cdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.map.hbdb.hb_info

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.map.hbdb.hdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.map.hbdb.sig

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.root_partition.map.hdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.root_partition.map.kpt

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.rrp.hdb

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

lu.rrs.cdb

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00