FPGA_Uni/Quartus/A2/simulation/questa/assignment2.sft at 80416e1f8a7e086059c83f31d32602eb9ab3fce8 - FPGA_Uni - Riley's Git Server

TroubleElectrical/FPGA_Uni

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TroubleElectrical 19b07b649d

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

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set tool_name "Questa Altera FPGA (SystemVerilog)"